KR20050035675A - Liquid crystal display panel and fabricating method thereof - Google Patents

Abstract

The present invention relates to a liquid crystal display panel and a method for manufacturing the same, which can reduce the number of mask processes and prevent corrosion of the shorting line.

According to an exemplary embodiment of the present invention, a liquid crystal display panel may include a gate line and a data line insulated from a substrate, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and the thin film transistor. A thin film transistor array substrate connected to at least one of the passivation layer, the gate line, and the data line, the pad having a transparent conductive layer, and exposed to the side of the substrate, the same metal as the data line; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; The passivation layer may be formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad.

Description

Liquid crystal display panel and manufacturing method therefor {LIQUID CRYSTAL DISPLAY PANEL AND FABRICATING METHOD THEREOF}

The present invention relates to a liquid crystal display panel, and more particularly, to a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes and prevent corrosion of the shorting line.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. In the liquid crystal display device, the liquid crystal display device drives the liquid crystal by an electric field formed between the pixel electrode and the common electrode disposed to face the upper and lower substrates.

The liquid crystal display includes a lower array substrate (thin film transistor array substrate) and an upper array substrate (color filter array substrate) bonded to each other, a spacer for maintaining a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap. Equipped.

The lower array substrate is composed of a plurality of signal lines and thin film transistors, and an alignment film coated thereon for liquid crystal alignment. The upper array substrate is composed of a color filter for color implementation and a black matrix for light leakage prevention, and an alignment film coated thereon for liquid crystal alignment.

In such a liquid crystal display, since the lower array substrate includes a semiconductor process and requires a plurality of mask processes, the manufacturing process is complicated, which is an important cause of an increase in manufacturing cost of the liquid crystal panel. In order to solve this problem, the lower array substrate is developing in a direction of reducing the number of mask processes. This is because one mask process includes many processes such as a thin film deposition process, a cleaning process, a photolithography process, an etching process, a photoresist stripping process, and an inspection process. Accordingly, in recent years, a four-mask process that reduces one mask process has emerged in the five-mask process, which is a standard mask process of a lower array substrate.

FIG. 1 is a plan view illustrating a lower array substrate using a conventional four mask process, and FIG. 2 is a cross-sectional view illustrating a lower array substrate taken along a line “II-II ′” in FIG. 1.

The lower array substrate illustrated in FIGS. 1 and 2 includes a gate line 2 and a data line 4 formed to intersect on the lower substrate 1 with a gate insulating layer 12 interposed therebetween, and a thin film transistor formed at each intersection thereof. 30, the pixel electrode 22 formed in the cross-sectional structure of the pixel, the gate pad 50 connected to the gate line 2, and the data pad 60 connected to the data line 4. Equipped.

The gate line 2 for supplying the gate signal and the data line 4 for supplying the data signal are formed in an intersecting structure to define the pixel region 5.

The thin film transistor 30 keeps the pixel signal of the data line 4 charged and held in the pixel electrode 22 in response to the gate signal of the gate line 2. To this end, the thin film transistor 30 includes a gate electrode 6 connected to the gate line 2, a source electrode 8 connected to the data line 4, and a drain electrode connected to the pixel electrode 22. 10). In addition, the thin film transistor 30 further includes an active layer 14 overlapping with the gate electrode 6 and the gate insulating layer 12 therebetween to form a channel between the source electrode 8 and the drain electrode 8. .

The active layer 14 also overlaps the data line 4, the data pad lower electrode 62, and the storage electrode 28. An ohmic contact layer 16 for ohmic contact with the data line 4, the source electrode 8, the drain electrode 8, and the data pad lower electrode 62 is further formed on the active layer 14.

The pixel electrode 22 is connected to the drain electrode 10 of the thin film transistor 30 through the first contact hole 40 penetrating the passivation layer 18 and is formed in the pixel region 5.

Accordingly, an electric field is formed between the pixel electrode 22 supplied with the pixel signal through the thin film transistor 30 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the lower array substrate and the upper array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 5 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The gate pad 50 is connected to a gate driver (not shown) to supply a gate signal to the gate line 2. The gate pad 50 includes a gate pad lower electrode 52 extending from the gate line 2 and a second gate hole 56 penetrating through the gate insulating layer 12 and the passivation layer 18. And a gate pad upper electrode 54 connected to 52.

The data pad 60 is connected to a data driver (not shown) to supply a data signal to the data line 4. The data pad 60 is connected to the data pad lower electrode 62 through a data pad lower electrode 62 extending from the data line 4 and a third contact hole 66 passing through the passivation layer 18. It consists of a data pad upper electrode 64.

A method of manufacturing a thin film transistor array substrate having such a configuration will be described with reference to FIGS. 3A to 3D in detail using a four mask process.

Referring to FIG. 3A, a first conductive pattern group including a gate line 2, a gate electrode 6, and a gate pad lower electrode 52 is formed on the lower substrate 1 by using a first mask process. .

In detail, the gate metal layer is formed on the lower substrate 1 through a deposition method such as a sputtering method. Subsequently, the gate metal layer is patterned by a photolithography process and an etching process using a first mask to form a first conductive pattern group including the gate line 2, the gate electrode 6, and the gate pad lower electrode 52. . Here, an aluminum metal or the like is used as the gate metal layer.

Referring to FIG. 3B, a gate insulating layer 12 is coated on the lower substrate 1 on which the first conductive pattern group is formed. A semiconductor pattern including an active layer 14 and an ohmic contact layer 16 on the gate insulating layer 12 using a second mask process; A second conductive pattern group including the data line 4, the source electrode 8, the drain electrode 10, and the data pad lower electrode 62 is formed.

In detail, the gate insulating layer 12, the amorphous silicon layer, the n + amorphous silicon layer, and the data metal layer are sequentially formed on the lower substrate 1 on which the first conductive pattern group is formed through a deposition method such as PECVD or sputtering. do. Here, as the material of the gate insulating film 12, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used. As the data metal, molybdenum (Mo), titanium, tantalum, molybdenum alloy (Mo alloy) and the like are used.

Subsequently, a photoresist pattern is formed on the data metal layer by a photolithography process using a second mask. In this case, by using a diffraction exposure mask having a diffraction exposure portion in the channel portion of the thin film transistor, the photoresist pattern of the channel portion has a lower height than other source / drain pattern portions.

Subsequently, the source / drain metal layer is patterned by a wet etching process using a photoresist pattern, so that the second conductive layer includes a data line 4, a source electrode 8, and a drain electrode 10 integrated with the source electrode 8. A pattern group is formed.

Then, the ohmic contact layer 14 and the active layer 16 are formed by simultaneously patterning the n + amorphous silicon layer and the amorphous silicon layer by a dry etching process using the same photoresist pattern.

The source / drain metal pattern and the ohmic contact layer 16 of the channel portion are etched after the photoresist pattern having a relatively low height is removed from the channel portion by an ashing process. Accordingly, the active layer 14 of the channel portion is exposed to separate the source electrode 8 and the drain electrode 10.

Subsequently, the photoresist pattern remaining on the second conductive pattern group is removed by a stripping process.

Referring to FIG. 3C, the passivation layer 18 including the first to third contact holes 20, 56, and 66 may be formed on the gate insulating layer 12 on which the second conductive pattern group is formed by using a third mask process. Is formed.

In detail, the protective film 18 is entirely formed on the gate insulating film 12 on which the second conductive pattern group is formed by a deposition method such as PECVD. Subsequently, the passivation layer 18 is patterned by a photolithography process and an etching process using a third mask to form first to third contact holes 20, 56, and 66. The first contact hole 20 penetrates the passivation layer 18 to expose the drain electrode 10, and the second contact hole 56 penetrates the passivation layer 18 and the gate insulating layer 12 to form a gate pad lower electrode ( 52 is exposed, and the third contact hole 66 penetrates through the passivation layer 18 to expose the data pad lower electrode 62. Here, when a dry etch ratio metal such as molybdenum (Mo) is used as the data metal, each of the first and third contact holes 20 and 66 penetrates to the drain electrode 10 and the data pad lower electrode 62. To expose their sides.

As the material of the protective film 18, an inorganic insulating material such as the gate insulating film 12 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB is used.

Referring to FIG. 3D, a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64 is formed on the passivation layer 18 by using a fourth mask process. do.

In detail, the transparent conductive film is apply | coated on the protective film 18 by the vapor deposition method, such as sputtering. Subsequently, the transparent conductive layer is etched through a photolithography process and an etching process using a fourth mask, thereby forming a third conductive pattern group including the pixel electrode 22, the gate pad upper electrode 54, and the data pad upper electrode 64. Is formed. The pixel electrode 22 is electrically connected to the drain electrode 10 through the first contact hole 20. The gate pad upper electrode 54 is electrically connected to the gate pad lower electrode 52 through the second contact hole 56. The data pad upper electrode 64 is electrically connected to the data lower electrode 62 through the third contact hole 66.

Herein, materials for the transparent conductive film include indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (ITZO), and indium zinc oxide (IZO). ) Is used.

As described above, the conventional thin film transistor array substrate and the method of manufacturing the same can reduce the number of manufacturing steps and reduce manufacturing costs in proportion to the case of using the 5 mask process by employing a four mask process. However, since the four mask process is still complicated and the manufacturing cost is limited, there is a need for a method of further reducing the manufacturing cost by simplifying the manufacturing process.

In addition, the thin film transistor array substrate of the conventional liquid crystal display panel is formed by a four-mask process to check for defects including short circuits and disconnection of signal lines, as shown in FIG. 4A, as shown in FIG. 4A. A gate shorting bar 80, a data pad 60, and a data shorting bar 90 connected through a data shorting line 92 are provided. After detecting whether the liquid crystal display panel is defective by using the shorting bars 80 and 90, the lower substrate 101 is cut along the cut line SCL that intersects the gate shorting line 82 and the data shorting line 92. As shown in FIG. 4B, the gate shorting line 82 and the data shorting line 92 are exposed to the side of the lower substrate 101. At this time, the gate shorting line 82 formed of a metal having low corrosion resistance, for example, aluminum or copper, is easily corroded in a high temperature and high humidity environment or an electric field applied during TFT driving, and the corrosion phenomenon propagates. Such corrosion may progress to the gate pad 50 and the data pad 60 as time passes.

Accordingly, an object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can reduce the number of mask processes.

Another object of the present invention is to provide a liquid crystal display panel and a method of manufacturing the same, which can prevent corrosion of the shorting line connecting the shorting bar and the pad.

In order to achieve the above object, a liquid crystal display panel according to the present invention includes a gate line and a data line insulated on a substrate, a thin film transistor formed at an intersection of the gate line and the data line, and a pixel electrode connected to the thin film transistor. A thin film transistor array substrate connected to at least one of a passivation layer for protecting the thin film transistor, at least one of the gate line and the data line, and having a pad formed of a transparent conductive film and exposed to the side of the substrate the same metal as the data line; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; The passivation layer may be formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad.

In order to achieve the above object, the liquid crystal display panel according to the present invention is connected to each of the gate line and the data line formed in the display area, and the transparent conductive film on the inside of the substrate based on the cutting line of the substrate, at least a portion of the transparent conductive film on the transparent conductive film A plurality of pads formed of an exposed gate metal film; A shorting bar formed on an outer side of the cut line; A shorting line connecting the pads and the shorting bar across the cut line and formed of the same metal as the data line in a region corresponding to the cut line; The shorting bar and the shorting line may be removed by a scribing process.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention comprises the steps of forming a pixel electrode and a gate pattern including a gate line, a gate electrode, a gate pad and a data pad including a transparent conductive film on a substrate Wow; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns and the pixel electrode are formed; A data pattern including a data line, a source electrode, and a drain electrode is formed on the substrate on which the semiconductor pattern and the gate insulation pattern are formed, and are connected to the gate pad and the data pad, respectively, and a shorting line is made of the same metal as the data pattern. Forming; Forming a protective film on the entire surface of the substrate to protect the thin film transistor; Forming an alignment layer on the passivation layer except for the pad region including the gate pad and the data pad; Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; And scribing the substrate such that the same metal as the data line is exposed across the shorting line to the side of the substrate.

In order to achieve the above object, a method of manufacturing a liquid crystal display panel according to the present invention includes a gate line formed on a substrate, a data line crossing the gate line to be insulated from each other to determine a pixel region, and an intersection of the gate line and the data line. A thin film transistor formed at a portion thereof, a passivation layer protecting the thin film transistor, a pixel electrode formed in the pixel region and connected to the thin film transistor, a gate pad formed of a transparent conductive layer connected to the gate line and included in the gate line, and the data line. Providing a thin film transistor array substrate connected to the substrate and having a data pad formed of the transparent conductive film and exposing the same metal as the data line on the side of the substrate; Providing a color filter array substrate facing the thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate to expose a pad region including the gate pad and the data pad; And exposing the transparent conductive film of the pad area using the color filter array substrate as a mask.

Other objects and advantages of the present invention in addition to the above object will be apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 5 to 16.

FIG. 5 is a plan view illustrating a lower array substrate of a liquid crystal display panel according to a first exemplary embodiment of the present invention, and FIG. 6 is a cross-sectional view illustrating a lower array substrate taken along the line “VI-VI ′” in FIG. 5.

5 and 6 include a display unit for implementing an image, a pad unit for supplying a driving signal to signal lines of the display unit, and a shorting unit for inspecting a defect of the display unit.

The display unit has a gate line 102 and a data line 104 formed on the lower substrate 101 with the gate insulating pattern 112 interposed therebetween, a thin film transistor 130 formed at each intersection thereof, and a cross structure thereof. And a storage capacitor 140 formed at an overlapping portion of the pixel electrode 122 and the gate line 102.

The gate line 102 for supplying the gate signal and the data line 104 for supplying the data signal are formed in an intersecting structure to define the pixel region 105.

The thin film transistor 130 keeps the pixel signal of the data line 104 charged and maintained in the pixel electrode 122 in response to the gate signal of the gate line 102. To this end, the thin film transistor 130 may include a gate electrode 106 connected to the gate line 102, a source electrode 108 connected to the data line 104, and a drain electrode connected to the pixel electrode 122. 110). In addition, the thin film transistor 130 further includes an active layer 114 that forms a channel between the source electrode 108 and the drain electrode 110 while overlapping the gate electrode 106 and the gate insulating pattern 112 therebetween. do. An ohmic contact layer 116 for ohmic contact with the data line 104, the drain electrode 110, and the storage electrode 128 is further formed on the active layer 114.

The pixel electrode 122 is directly connected to the drain electrode 110 of the thin film transistor 130 and formed in the pixel region 105. The pixel electrode 122 includes a transparent conductive film 170 formed to be exposed in the pixel region 105, and a gate metal film 172 overlapping the drain electrode 110 on the transparent conductive film 172.

Accordingly, an electric field is formed between the pixel electrode 122 supplied with the pixel signal through the thin film transistor 130 and the common electrode (not shown) supplied with the reference voltage. This electric field causes the liquid crystal molecules between the thin film transistor array substrate and the color filter array substrate to rotate by dielectric anisotropy. The light transmittance passing through the pixel region 105 is changed according to the degree of rotation of the liquid crystal molecules, thereby realizing grayscale.

The pad portion includes a gate pad 150 extending from the gate line 102 and a data pad 160 extending from the data line 104.

The gate pad 150 is connected to a gate driver (not shown) to supply a gate signal generated by the gate driver to the gate line 102 through the gate link 152. The gate pad 150 has a structure in which the transparent conductive layer 170 included in the gate link 152 connected to the gate line 102 is exposed.

The data pad 160 is connected to a data driver (not shown) to supply a data signal generated by the data driver to the data line 104 through the data link 168. The data pad 160 has a structure in which the transparent conductive layer 170 included in the data link 168 connected to the data line 104 is exposed. Here, the data link 168 includes a data link lower electrode 162 formed at the same time as the gate link 152 and a data link upper electrode 166 connected to the data line 104.

The shorting part is supplied with an inspection signal to inspect the defect of the signal line including the gate line 102 and the data line 104 and the defect of the thin film transistor 130, and the signal lines 102 and 104 of the liquid crystal display panel during the manufacturing process. A shorting bar is connected to a ground voltage source (GND) to block the static electricity transmitted to the side to protect the thin film transistor 130 from static electricity.

To this end, the shorting bar includes a gate shorting bar 180 connected to the gate line 102 through the gate pad 150, and a data shorting bar 190 connected to the data line 104 through the data pad 160. do.

The gate shorting bar 180 has a structure in which a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170 are stacked. The gate shorting bar 180 is electrically connected to the gate pad 150 through the gate shorting line 182.

The data shorting bar 190 has a structure in which a transparent conductive film 170 and a gate metal film 172 formed on the transparent conductive film 170 are stacked. The data shorting bar 190 is electrically connected to the data pad 160 through the data shorting line 192.

The gate shorting line 182 and the data shorting line 192 may be formed of the same metal as the data line 104. For example, molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and MoW It is formed of a metal resistant to corrosion.

The gate shorting line 182 is connected to the gate shorting bar 180 through the first shorting contact hole 184 penetrating through the gate insulating film 112, the active layer 114, and the ohmic contact layer 116. 112 is connected to the gate pad 150 through the second shorting contact hole 186 passing through the active layer 114 and the ohmic contact layer 116. The data shorting line 192 is connected to the data shorting bar 190 through a third shorting contact hole 194 penetrating through the gate insulating layer 112, the active layer 114, and the ohmic contact layer 116. 112, a fourth shorting contact hole 196 penetrating through the active layer 114 and the ohmic contact layer 116 is connected to the data pad 160.

As such, the shorting lines 182 and 192 are formed of a metal that is resistant to corrosion, and are formed to expose the metal that is resistant to corrosion on the side of the lower substrate 101 during the scribing process. This is to prevent the gate metal film from being exposed to the side by the scribing process to be corroded when the shorting lines 182 and 192 of the region corresponding to the scribing line SCL are formed to include the gate metal film.

7A to 7C are cross-sectional views illustrating a method of manufacturing a lower array substrate of a liquid crystal display panel according to the present invention.

Referring to FIG. 7A, the pixel electrode 122 is formed on the lower substrate 101 by a first mask process; Two-layer gate line 102, gate electrode 106, gate link 152, gate pad 150, data pad 160, data link lower electrode 162, gate shorting bar 180, data A gate pattern including the shorting bar 190 is formed.

To this end, the transparent conductive film 170 and the gate metal film 172 are sequentially formed on the lower substrate 101 through a deposition method such as sputtering. Here, the transparent conductive film 170 may be formed of indium tin oxide (ITO), tin oxide (TO), indium tin zinc oxide (IZO), and indium zinc oxide (IZO). A transparent conductive material such as) is used, and a metal such as aluminum (Al) -based metal, molybdenum (Mo), copper (Cu), or the like is used for the gate metal film 172. Subsequently, the transparent conductive film 170 and the gate metal film 172 are patterned by a photolithography process and an etching process using a first mask to form the pixel electrode 122; Two-layer gate line 102, gate electrode 106, gate link 152, gate pad 150, data pad 160, data link lower electrode 162, gate shorting bar 180, data A gate pattern including the shorting bar 190 is formed.

Referring to FIG. 7B, the gate insulating pattern 112 may be formed on the lower substrate 101 on which the gate pattern is formed; A semiconductor pattern including the active layer 114 and the ohmic contact layer 116 is formed.

To this end, the gate insulating film and the first and second semiconductor layers are sequentially formed on the lower substrate 101 on which the gate pattern is formed through a deposition method such as PECVD or sputtering. Herein, an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx) is used as the material of the gate insulating film, and the first semiconductor layer is made of amorphous silicon without doping impurities, and the second semiconductor layer is made of N. Amorphous silicon doped with impurities of type or P type is used. Subsequently, the first and second semiconductor layers and the gate insulating layer are patterned by a photolithography process and an etching process using a second mask to form a gate line 102, a gate electrode 106, a gate link 152, and a data link 162. ) And a semiconductor pattern including an active insulating layer 114 and an ohmic contact layer 116 having a width wider than the gate pattern is formed on the gate insulating pattern 112. The first to fourth shorting contact holes 184, 186, 194 and 196 may be formed to expose portions of the gate shorting bar 180, the gate pad 150, the data shorting bar 190, and the data pad 160, respectively. In this case, when the width of the semiconductor pattern is smaller than the width of the gate electrode 106, the channel characteristics are deteriorated. Therefore, the semiconductor pattern is formed wider than the width of the gate electrode 106.

Referring to FIG. 7C, the data line 104, the source electrode 108, and the drain electrode are formed on the lower substrate 101 on which the gate insulating pattern 112, the semiconductor pattern, and the first to fourth shorting contact holes 184, 186, 194, and 196 are formed. A data pattern including the data link upper electrode 166, the gate shorting line 182, and the data shorting line 192 is formed. The gate metal film 172 included in the data pad 160, the gate pad 150, and the pixel electrode 122 is removed to expose the transparent conductive film 170. The third mask process will be described in detail with reference to FIGS. 8A to 8E as follows.

As shown in FIG. 8A, the data metal layer 109 and the photoresist layer 228 are sequentially formed on the lower substrate 101 on which the semiconductor pattern is formed by a deposition method such as sputtering. Here, the data metal layer 109 is made of a metal such as molybdenum (Mo), copper (Cu), or the like.

Then, the third mask 220, which is a partial exposure mask, is aligned above the lower substrate 101. The third mask 220 includes a mask substrate 222 made of a transparent material, a blocking portion 224 formed in the blocking region S2 of the mask substrate 222, and a partial exposure region S3 of the mask substrate 222. The formed diffraction exposure part 226 (or semi-transmissive part) is provided. Here, the region where the mask substrate 222 is exposed becomes the exposure region S1. After exposing and developing the photoresist film 228 using the third mask 220, as shown in FIG. 8B, the blocking part 224 and the diffraction exposure part 226 of the third mask 220 may be formed. A photoresist pattern 230 having a step is formed in the blocking region S2 and the partial exposure region S3. That is, the photoresist pattern 230 formed in the partial exposure region S3 has a second height lower than that of the photoresist pattern 230 having the first height formed in the blocking region S2.

The data metal layer 109 is patterned by a wet etching process using the photoresist pattern 230 as a mask, so that the storage electrode 128, the data line 104, the source electrode 108 connected to the data line 104, and the drain are formed. A data pattern including an electrode 110, a data link upper electrode 166 connected to the other side of the data line 104, a gate shorting line 182, and a data shorting line 192 is formed, and is formed below the data pattern. The gate metal layer 172 is removed by using the gate insulating pattern 112 as a mask to expose the transparent conductive layer 170 included in the data pad 160, the gate pad 150, and the pixel electrode 122.

The active layer 114 and the ohmic contact layer 116 are formed along the data pattern by a dry etching process using the photoresist pattern 230 as a mask. At this time, the active layer 114 and the ohmic contact layer 116 positioned in the remaining region except for the active layer 114 and the ohmic contact layer 116 overlapping the data pattern are removed. This is to prevent a short circuit between cells due to the semiconductor pattern including the active layer 114 and the ohmic contact layer 116.

Subsequently, in the ashing process using an oxygen (O ₂ ) plasma, the photoresist pattern 230 having the second height in the partial exposure region S3 is removed as shown in FIG. 8C, and the blocking region S2 is removed. The photoresist pattern 230 having the first height h1 is in a state where the height is lowered. In the etching process using the photoresist pattern 230, the data metal layer and the ohmic contact layer 116 formed in the channel portion of the thin film transistor, ie, the channel portion of the thin film transistor, are removed, thereby draining the drain electrode 110 and the source electrode 108. This is separated. The photoresist pattern 230 remaining on the data pattern is removed by a stripping process as shown in FIG. 8D.

Subsequently, a protective film 118 is formed on the entire surface of the substrate 101 on which the data pattern is formed, as shown in FIG. 8E. As the passivation layer 118, an inorganic insulating material such as the gate insulating pattern 112 or an organic insulating material such as an acryl-based organic compound having a low dielectric constant, BCB, or PFCB may be used.

FIG. 9 is a plan view illustrating a lower array substrate of a liquid crystal display panel according to a second exemplary embodiment of the present invention, and FIG. 10 is a bottom array substrate of a liquid crystal display panel taken along a line "Ⅹ-Ⅹ" in FIG. 9. It is a cross section.

9 and 10 except that the gate shorting bar 280 and the data shorting bar 290 are formed of a metal that is strong in comparison with the lower array substrate shown in FIGS. 5 and 6. Has the same components. Accordingly, detailed description of the same components will be omitted.

The gate shorting bar 280 is formed of the same metal as the data line 104. For example, the gate shorting bar 280 is made of a corrosion resistant metal such as molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and MoW. Is formed. The gate shorting bar 280 is electrically connected to the gate pad 150 through the gate shorting line 282. The gate shorting line 282a extends from the gate shorting bar 280 to cross the scribing line SCL, and the second gate shorting line extending from the gate pad 150. 282b. The first and second gate shorting lines 282a and 282b are electrically connected to each other through the first insulating contact hole 284 penetrating through the gate insulating layer 112, the active layer 114, and the ohmic contact layer 116. Here, the first gate shorting line 182a is formed of a metal that is strong against the same type as the gate shorting bar 180, and the second gate shorting line 182b is formed of the transparent conductive film 170, similarly to the gate pad 150. The gate metal film 172 formed on the transparent conductive film 170 is formed.

The data shorting bar 190 is formed of the same metal as the data line 104. For example, the data shorting bar 190 may be formed of a corrosion resistant metal such as molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and MoW. Is formed. The data shorting bar 190 is electrically connected to the data pad 160 through the data shorting line 192. The data shorting line 192 extends from the data shorting bar 190 to cross the scribing line SCL, and the first data shorting line 192a and the second data shorting line extended from the data pad 160. 192b. The first and second data shorting lines 192a and 192b are electrically connected to each other through the gate insulating layer 112 and the second shorting contact hole 194 passing through the active layer 114 and the ohmic contact layer 116. Here, the first data shorting line 192a is formed of a metal resistant to the same type as the data shorting bar 190, and the second data shorting line 192b is the same as the data pad 160, the transparent conductive film 170, The gate metal film 172 formed on the transparent conductive film 170 is formed.

As described above, the shorting lines 182 and 192 of the region corresponding to the scribing region are formed of a metal that is resistant to corrosion, and are formed to expose the metal that is resistant to corrosion on the side of the lower substrate 101 during the scribing process. This is to prevent the gate metal film from being exposed to the side by the scribing process to be corroded when the shorting lines 182 and 192 of the region corresponding to the scribing line SCL are formed to include the gate metal film.

Looking at the method of manufacturing the lower array substrate of the liquid crystal display panel, as shown in FIG. 11A by the first mask process, the gate line 106, the gate electrode 102, the second gate shorting line 282b, and the second A gate pattern including the data shorting line 292b, the gate pad 150, and the data pad 160 is formed. As shown in FIG. 11B, the gate insulating layer 112 and the semiconductor patterns 114 and 116 having the first and second shorting contact holes 284 and 294 are formed by the second mask process. As shown in FIG. 11C by the third mask process, the gate shorting bar 280, the data shorting bar 290, the first gate shorting line 282a and the first data shorting line 292a and the source electrode 108 are used. And a data pattern including the drain electrode 110, the data line 104, and the data link upper electrode 166, and the transparency included in the gate pad 150, the data pad 160, and the pixel electrode 122. The front film 170 is exposed. Thereafter, a passivation layer 180 for protecting the thin film transistor 130 is formed on the entire lower substrate 101.

FIG. 12 is a plan view illustrating a lower array substrate of a liquid crystal display panel according to a third exemplary embodiment of the present invention, and FIG. 13 illustrates a lower array substrate of a liquid crystal display panel taken along a line “XIII-XIII ′” in FIG. 12. It is a cross section.

12 and 13 may expose the transparent conductive film 170 included in the gate shorting bar 380 and the data shorting bar 390 as compared with the lower array substrate shown in FIGS. 5 and 6. It has the same components except that it is formed. Accordingly, detailed description of the same components will be omitted.

The gate shorting bar 380 is formed to have a structure in which a transparent conductive layer 170 and a gate metal layer 172 exposing the transparent conductive layer are exposed to overlap the gate shorting line 382 on the transparent conductive layer 170. . The gate shorting bar 380 is electrically connected to the gate pad 150 through the gate shorting line 382.

The data shorting bar 390 is formed to have a structure in which a transparent conductive film 170 and a gate metal film 172 are formed on the transparent conductive film 170 so as to overlap the data shorting line 392 and expose the transparent conductive film. . The data shorting bar 390 is electrically connected to the data pad 160 through the data shorting line 392.

The gate shorting line 382 and the data shorting line 392 are formed of the same metal as the data line 104. For example, molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) and MoW It is formed of a metal resistant to corrosion.

The gate shorting line 382 is directly connected to the gate metal film 172 included in each of the gate shorting bar 380 and the gate pad 150. The data shorting line 392 is connected to the gate metal film 172 included in each of the data shorting bar 390 and the data pad 160.

As described above, the shorting lines 382 and 392 are formed of a metal that is resistant to corrosion, and are formed to expose a metal that is resistant to corrosion on the side of the lower substrate 101 during the scribing process. This is to prevent the gate metal film 172 from being exposed to the side by the scribing process and to be corroded when the shorting lines 382 and 392 in the region corresponding to the scribing line SCL are formed to include the gate metal film. .

Looking at the method of manufacturing the lower array substrate of the liquid crystal display panel, as shown in FIG. 14A by the first mask process, the gate line 102, the gate electrode 106, the gate shorting bar 380, and the gate pad 150 are formed. A gate pattern including a data shorting bar 390 and a data pad 160; The pixel electrode 122 including the gate metal film 172 is formed. As shown in FIG. 14B, a gate insulating layer and a semiconductor pattern exposing the gate shorting bar 380, the gate pad 150, the data shorting bar 390, and the data pad 160 are formed by the second mask process. As shown in FIG. 14C by a third mask process, a data pattern including a data line 104, a source electrode 108, a drain electrode 110, a gate shorting line 382 and a data shorting line 392. Is formed. The gate metal layer 172 included in the pixel electrode 122, the gate shorting bar 380, the gate pad 150, the data shorting bar 390, and the data pad 160 is patterned using the data pattern as a mask. As a result, the transparent conductive film 170 contained therein is exposed.

15 is a cross-sectional view illustrating a liquid crystal display panel including lower array substrates according to first to third embodiments of the present invention.

The liquid crystal display panel illustrated in FIG. 15 includes an upper array substrate 300 and a lower array substrate 302 bonded by a material 254.

The upper array substrate 300 is formed with an upper array 252 including a black matrix and a color filter formed on the upper substrate 250. In the lower array substrate 302, an area overlapping the upper array substrate 300 is protected by the protection pattern 304, and a pad area that is not overlapped with the upper array substrate 300 includes the gate pad 150 and the data pad ( The transparent conductive film 170 included in the 160 is formed to be exposed.

Referring to the manufacturing method of the liquid crystal display panel, first, the upper array substrate 300 and the lower array substrate 302 illustrated in FIG. 6 are separately formed and then bonded to the real material 254. Thereafter, the protective layer 118 of the lower array substrate 302 shown in FIG. 6 is patterned by a pad opening process using the upper array substrate 300 as a mask, thereby forming a protective pattern 304 in the display area and displaying a non-display. The gate pad 150 of the region and the transparent conductive film 170 of the data pad 160 are exposed. Then, the non-display area including the gate shorting part and the data shorting part is cut based on the scribing line by the scribing process. At this time, since the transparent conductive film 170 is exposed to the side surface of the substrate 101 cut by the scribing line SCL, corrosion of the metal is prevented.

Meanwhile, in the pad opening process, each pad exposed by the upper array substrate 300 is sequentially scanned by using the plasma generated by the atmospheric pressure plasma generator, or the pads are collectively scanned by the pad unit to form the gate pad 150 and The transparent conductive film 170 of the data pad 160 is exposed. Alternatively, a plurality of liquid crystal cells in which the upper array substrate 300 and the lower array substrate 302 are bonded to each other are inserted into the chamber, and then the protective layer 118 of the pad region exposed by the upper array substrate 300 is removed using atmospheric pressure plasma. Etching exposes the transparent conductive layer 170 of the gate pad 150 and the data pad 160. Alternatively, the entire liquid crystal cell, to which the upper array substrate 300 and the lower array substrate 302 are bonded, may be immersed in an etchant, or only a pad region including the gate pad 150 and the data pad 160 may be immersed in the etchant to form a gate pad ( 150 and the transparent conductive film 170 of the data pad 160 are exposed.

16 is a cross-sectional view illustrating another embodiment of a liquid crystal display panel including the lower array substrate according to the first to third embodiments of the present invention.

The liquid crystal display panel illustrated in FIG. 16 includes an upper array substrate 300 and a lower array substrate 302 bonded by a material 254.

The upper array substrate 300 is formed with an upper array 252 including a black matrix and a color filter formed on the upper substrate 250. In the lower array substrate 302, the display area defined by the alignment layer 282 is protected by the protection pattern 118, and the gate pad 150 and the data pad of the pad area included in an area overlapping with the alignment layer 282. The transparent conductive film 170 of 160 is formed to be exposed. In this case, the protective pattern 118 is patterned and formed by an etching process using the alignment layer 382 as a mask. Then, the non-display area including the gate shorting part and the data shorting part is cut based on the scribing line by the scribing process. At this time, since the transparent conductive film 170 is exposed to the side surface of the substrate 10 cut by the scribing line SCL, corrosion of the metal is prevented.

As described above, the liquid crystal display panel and the method of manufacturing the same according to the present invention are exposed to a metal that is resistant to electrical corrosion in the region corresponding to the scribing line and the shorting line crossing the scribing line to connect the pad and the shorting bar. Form. That is, the shorting line is formed of data metal including molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and MoW. Accordingly, a strong metal is exposed to the side of the substrate after the scribing process to prevent corrosion of the signal line.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a plan view showing a conventional thin film transistor array substrate.

FIG. 2 is a cross-sectional view of the thin film transistor array substrate of FIG. 1 taken along the line " I-I '"

3A through 3D are cross-sectional views sequentially illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 2.

4A and 4B are plan views and cross-sectional views illustrating gate shorting bars and data shorting bars extended from the gate pads and the data pads shown in FIGS. 1 and 2.

5 is a plan view illustrating a thin film transistor array substrate according to a first exemplary embodiment of the present invention.

FIG. 6 is a cross-sectional view of the thin film transistor array substrate of FIG. 5 taken along the line "VI-VI '".

7A to 7C are cross-sectional views illustrating in detail a method of manufacturing the thin film transistor array substrate illustrated in FIG. 6.

8A to 8E are cross-sectional views for describing a third mask process in a method of manufacturing the thin film transistor array substrate illustrated in FIG. 7C in detail.

9 is a plan view illustrating a thin film transistor array substrate according to a second exemplary embodiment of the present invention.

FIG. 10 is a cross-sectional view of the thin film transistor array substrate of FIG. 9 taken along the line "VII-VII". FIG.

11A to 11C are cross-sectional views illustrating in detail a method of manufacturing the thin film transistor array substrate illustrated in FIG. 10.

12 is a plan view illustrating a thin film transistor array substrate according to a third exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the thin film transistor array substrate of FIG. 12 taken along the line "XIII-XIII '".

14A to 14C are cross-sectional views illustrating a method of manufacturing the thin film transistor array substrate illustrated in FIG. 13 in detail.

15 is a cross-sectional view illustrating a liquid crystal display panel including a thin film transistor array substrate according to the first to third embodiments of the present invention.

16 is a cross-sectional view illustrating a liquid crystal display panel including a thin film transistor array substrate according to first to third embodiments of the present invention.

<Description of Symbols for Main Parts of Drawings>

2,102: gate line 4,104: data line

6,106: gate electrode 8,108: source electrode

10,110 drain electrode 12 gate insulating film

14,114 active layer 16,116 ohmic contact layer

18,118: protective film 20,56,66,120: contact hole

22,122: pixel electrode 30,130: storage electrode

40,140: Storage capacitor 50,150: Gate pad

52: gate pad lower electrode 54: gate pad upper electrode

60, 160: data pad 62: data pad lower electrode

64: data pad upper electrode 112: gate insulating pattern

152: gate link 168: data link

170: transparent conductive film 172: gate metal film

180,280,380: Gate shorting bar 190,290,390: Data shorting bar

Claims (36)

A gate line and a data line insulated from each other with a gate insulating pattern interposed therebetween, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode connected to the thin film transistor, and a thin film transistor for protecting the thin film transistor A thin film transistor array substrate having a pad connected to at least one of a passivation layer, the gate line, and a data line and having a pad formed of a transparent conductive layer, the same metal being exposed on the side of the substrate as the data line; A color filter array substrate opposed to and bonded to the thin film transistor array substrate; And the passivation layer is formed in an area overlapping the color filter array substrate to expose the transparent conductive layer included in the pad. The method of claim 1, The pad A gate pad connected to the gate line and formed of the transparent conductive film included in the gate line; And a data pad connected to the data line and formed of the transparent conductive film. The method of claim 1, A shorting bar formed on the substrate and removed by a scribing process; And a shorting line connecting the shorting bar and the pad and formed of the same metal as the data line exposed to the side surface of the substrate by being removed based on the cutting line of the substrate by the scribing process. Display panel. The method of claim 3, wherein And the shorting bar comprises a transparent conductive film and a gate metal film formed on the transparent conductive film. The method of claim 4, wherein And the shorting line is connected to the shorting bar and the pad through first and second contact holes exposing the shorting bar and the pad, respectively. The method of claim 5, wherein And each of the first and second contact holes exposes the shorting bar and the pad through the gate insulating pattern and the semiconductor pattern formed on the shorting bar and the pad. The method of claim 3, wherein And the shorting bar is formed of the same metal as the shorting line and is integrally formed with the shorting bar. The method of claim 7, wherein And the shorting line is connected to the pad through a third contact hole exposing the pad. The method of claim 8, And the third contact hole exposes the pad through the gate insulating pattern and the semiconductor pattern formed on the pad. The method of claim 3, wherein And the shorting bar and the pad are formed of a transparent conductive film and a gate metal film overlapping the shorting line on the transparent conductive film. The method of claim 1, And the data line is formed of a metal having high corrosion resistance including molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta), and MoW. The method of claim 1, And an alignment layer formed on the protective layer in the same pattern as the protective layer. The method of claim 1, The thin film transistor is A gate electrode connected to the gate line; A source electrode connected to the data line; A drain electrode facing the source electrode; And a semiconductor pattern overlapping the gate electrode and the gate insulating pattern, and forming a channel portion between the source electrode and the drain electrode. The method of claim 13, And the gate line and the gate electrode are formed of the transparent conductive film and a gate metal film formed on the transparent conductive film. A plurality of pads connected to each of the gate line and the data line formed in the display area and formed of a transparent conductive film inside the substrate, the gate metal film exposing at least a portion of the transparent conductive film on the transparent conductive film; A shorting bar formed on an outer side of the cut line; A shorting line connecting the pads and the shorting bar across the cut line and formed of the same metal as the data line in a region corresponding to the cut line; And the shorting bar and the shorting line are removed by a scribing process. Forming gate patterns including a gate line, a gate electrode, a gate pad, and a data pad including a transparent conductive film and a pixel electrode on the substrate; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns and the pixel electrode are formed; A data pattern including a data line, a source electrode, and a drain electrode is formed on the substrate on which the semiconductor pattern and the gate insulation pattern are formed, and are connected to the gate pad and the data pad, respectively, and a shorting line is made of the same metal as the data pattern. Forming; Forming a protective film on the entire surface of the substrate to protect the thin film transistor; Forming an alignment layer on the passivation layer except for the pad region including the gate pad and the data pad; Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; And scribing the substrate such that the same metal as the data line is exposed to the side of the substrate across the shorting line. The method of claim 16, And exposing a transparent conductive film included in the pixel electrode, the gate pad, and the data pad using at least one of the data pattern, the gate insulating pattern, and the semiconductor pattern as a mask. Manufacturing method. The method of claim 16, And forming a shorting bar connected to the shorting line. The method of claim 18, Forming the shorting bar is And a gate metal film formed on the transparent conductive film and formed at the same time as the gate pattern. The method of claim 19, Forming the shorting line And forming a shorting line connected to the shorting bar and the pad through first and second contact holes through the gate insulating pattern and the semiconductor pattern to expose the shorting bar and the pad. Method of manufacturing the panel. The method of claim 18, Forming the shorting bar is And the shorting bar is formed of the same metal as the shorting line. The method of claim 21, Forming the shorting line And forming a shorting line connected to the pad through a third contact hole through the gate insulating pattern and the semiconductor pattern to expose the pad. The method of claim 18, Wherein the shorting bar and the pad are formed of a transparent conductive film and a gate metal film overlapping the shorting line on the transparent conductive film. The method of claim 16, And the shorting line is formed of a metal having high corrosion resistance including molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) and MoW. The method of claim 16, Exposing the transparent conductive film included in the pad area by removing the protective film formed to cover the pad area using the alignment layer as a mask; Printing an alignment layer on the substrate on which the protective layer is formed; And etching the passivation layer formed to cover at least one of the gate pad and the data pad by using the alignment layer as a mask. A gate line formed on a substrate, a data line crossing the gate line to be insulated from each other to determine a pixel area, a thin film transistor formed at an intersection of the gate line and the data line, a protective film protecting the thin film transistor, and a pixel And a pixel electrode formed in the pixel electrode connected to the thin film transistor, a gate pad connected to the gate line and formed of a transparent conductive film included in the gate line, and a data pad connected to the data line and formed of the transparent conductive film. Providing a thin film transistor array substrate in which the same metal as the line is exposed; Providing a color filter array substrate facing the thin film transistor array substrate; Bonding the thin film transistor array substrate and the color filter array substrate to expose a pad region including the gate pad and the data pad; And exposing a transparent conductive film in a pad area using the color filter array substrate as a mask. The method of claim 26, Preparing the thin film transistor array substrate Forming gate patterns and pixel electrodes including a gate line, a gate electrode, a gate pad, and a data pad including a transparent conductive film on the substrate; Forming a semiconductor pattern and a gate insulating pattern on a substrate on which the gate patterns and the pixel electrode are formed; Forming a data pattern including a data line, a source electrode and a drain electrode on the substrate on which the semiconductor pattern and the gate insulation pattern are formed, and a shorting line connected to each of the gate pad and the data pad; Forming a protective film on the substrate on which the data pattern is formed; And scribing the substrate across the shorting line. The method of claim 27, And exposing a transparent conductive film included in the pixel electrode, the gate pad, and the data pad using at least one of the data pattern, the gate insulating pattern, and the semiconductor pattern as a mask. Manufacturing method. The method of claim 27, And forming a shorting bar connected to the shorting line. The method of claim 29, Forming the shorting bar is And a gate metal film formed on the transparent conductive film, the gate metal film formed on the transparent conductive film simultaneously with the gate pattern. The method of claim 30, Forming the shorting line And forming a shorting line connected to the shorting bar and the pad through first and second contact holes through the gate insulating pattern and the semiconductor pattern to expose the shorting bar and the pad. Method of manufacturing the panel. The method of claim 29, Forming the shorting bar is And the shorting bar is formed of the same metal as the shorting line. The method of claim 32, Forming the shorting line And forming a shorting line connected to the pad through a third contact hole through the gate insulating pattern and the semiconductor pattern to expose the pad. The method of claim 29, Wherein the shorting bar and the pad are formed of a transparent conductive film and a gate metal film overlapping the shorting line on the transparent conductive film. The method of claim 26, And the shorting line is formed of a metal having high corrosion resistance including molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum (Ta) and MoW. The method of claim 26, Exposing the transparent conductive film of the pad area using the color filter array substrate as a mask And removing the protective layer of the pad area by an etching process using the color filter array substrate as a mask.