KR20050028740A - Method for testing semiconductor chip - Google Patents

Abstract

A method for testing a semiconductor chip is provided to efficiently use the area of a semiconductor chip by using a scribe line formed between adjacent semiconductor chips, thereby singulating a plurality of semiconductor chips. A plurality of semiconductor chips(203,204) including circuit devices are formed in a semiconductor substrate. A scribe line is formed between adjacent chips to singulate the plurality of semiconductor chips. A test circuit(211) is formed in the scribe line. The plurality of semiconductor chips are tested by using the test circuit. The output signal of the test circuit is applied to a probe card(202) for transferring a power supply voltage or a function signal to the plurality of semiconductor chip so as to test the plurality of semiconductor chips.

Description

Semiconductor chip test method {METHOD FOR TESTING SEMICONDUCTOR CHIP}

The present invention relates to a semiconductor chip test method, and more particularly, to a semiconductor chip test method for testing a semiconductor chip using a scribe line.

Once the fabrication process of the semiconductor chip has been completed, the semiconductor chip test is performed to measure various characteristics of each semiconductor chip formed on the semiconductor substrate before entering the cutting step for the package process. .

The semiconductor chip test is a process for finding defects in a process such as a semiconductor substrate manufacturing process or an assembly process to remove defective products and to select only good products.

If a manufacturing defect or a design and function inconsistency is found through the semiconductor chip test, a failure analysis is performed to investigate the exact cause thereof, thereby increasing the productivity of the semiconductor chip. .

In the semiconductor chip test, the DC characteristics and the AC characteristics of the semiconductor chip are measured by using tester equipment. In the case of measuring the DC characteristics of the semiconductor chip test, voltage is applied to each electrode of the semiconductor chip, and a current is measured or a current is measured to measure the voltage so that the stability, power consumption, and leakage of power wiring inside the semiconductor chip are measured. ) Measure current, etc.

In the case of measuring the AC characteristic of the semiconductor chip test, a pulse signal is applied to an input terminal of the semiconductor chip so that a transition time (rising time, falling time) of an output signal, a voltage level recognizing a high state or a low state, an input / output propagation delay Dynamic characteristics such as time and access time (tRAC, tCAC, tCAA) are measured.

In the related art, in order to perform a semiconductor chip test, a separate test circuit must be formed in the semiconductor chip, so that an area of the semiconductor chip is increased and the test circuit may affect the operation of the semiconductor chip.

Accordingly, an object of the present invention is to provide a semiconductor chip test method for testing a semiconductor chip using a scribe line formed between adjacent semiconductor chips so that a plurality of semiconductor chips are individualized.

In order to achieve the above object, in the semiconductor chip test method according to an embodiment of the present invention, a plurality of semiconductor chips including circuit elements are formed, and the plurality of semiconductor chips are disposed between adjacent semiconductor chips to be individualized. A semiconductor chip test for testing the plurality of semiconductor chips in a semiconductor substrate having a scribe line, wherein the test circuit is formed on the scribe line and the plurality of semiconductor chips are tested using the test circuit. .

The semiconductor chip test method according to another embodiment of the present invention is characterized by testing the plurality of semiconductor chips by applying an output signal of the test circuit to a probe card that delivers a power voltage or a function signal to the plurality of semiconductor chips. do.

The semiconductor chip test method according to another embodiment of the present invention is characterized in that the test circuit is a frequency multiplier.

Hereinafter, a semiconductor chip test method according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view of a semiconductor chip and a scribe line formed on a semiconductor substrate.

A plurality of integrated circuit (IC) semiconductor chips 101 including various circuit elements (MOS transistors, capacitors, resistors, etc.) by performing various semiconductor chip manufacturing processes on a semiconductor substrate (not shown). To 104).

After the manufacturing process is completed, the semiconductor substrate is cut to individualize the plurality of integrated circuit semiconductor chips 101 to 104. In order to protect the plurality of integrated circuit semiconductor chips 101 to 104 from the cutting, an empty space necessary for the cutting is formed between adjacent integrated circuit semiconductor chips, and the empty space is a scribe line (111 to 116). It is called). Circuit elements constituting the integrated circuit semiconductor chip are not formed in the scribe lines 111 to 116.

By forming a test circuit in the scribe lines 111 to 116, the area of the integrated circuit semiconductor chip is not increased since the test circuit does not need to be formed in the integrated circuit semiconductor chip.

Conventionally, a test element group (TEG) is formed in the scribe line in order to examine electrical characteristics of various elements constituting the integrated circuit semiconductor chip. The test device group is then electrically tested to determine whether devices in the plurality of integrated circuit semiconductor chips formed on a semiconductor substrate are properly formed.

Since the test device group is formed using the same process as the process used to form devices in the plurality of integrated circuit semiconductor chips, measuring the electrical characteristics of the test device group in the plurality of integrated circuit semiconductor chips It is like measuring the electrical characteristics of the devices formed.

In addition, an alignment key for aligning positions of the plurality of integrated circuit semiconductor chips is also formed in the scribe line during a fabrication process.

However, in the current trend of increasing the density of the integrated circuit semiconductor chip, the area of the scribe line is increasing as the area of the integrated circuit semiconductor chip is reduced. Therefore, the area of the scribe line in which the test device group or the alignment key is not formed is also increased.

In the integrated circuit semiconductor chip test sheet, the test timing is determined not by the operating frequency of the integrated circuit semiconductor chip but by the frequency of the pulse signal provided by the tester equipment.

For example, if an integrated circuit semiconductor chip can operate at 400 MHz, but the tester equipment is operated at 50 MHz, the integrated circuit semiconductor chip will have to be tested at 50 MHz.

In order to solve the above-mentioned problem, recently, an MRS (Mode Register Set) is used to test an integrated circuit semiconductor chip at a frequency higher than that of a pulse signal provided by tester equipment.

However, when using such a test method, a separate test circuit for testing using the MRS must be formed in the integrated circuit semiconductor chip, thereby increasing the area of the integrated circuit semiconductor chip.

Therefore, without forming a separate test circuit in the integrated circuit semiconductor chip that can be tested using the MRS, as shown in Figure 2, if formed in the scribe line 211 integrated circuit semiconductor chip (203, 204) The area of is not increased.

The integrated circuit semiconductor chip may be tested using the output signal of the test circuit 211 as an input signal of the integrated circuit semiconductor chip. When the semiconductor substrate is tested, the output signal of the test circuit 211 may be used as an input signal of the integrated circuit semiconductor chip by using a probe card 202 that transmits a power supply voltage or a motion signal to the integrated circuit semiconductor chip.

The probe card 202 arranges electrodes to transmit power voltages or function signals to the test circuit 211 as well as an integrated circuit semiconductor chip.

In the case of forming a frequency multiplying circuit that increases or doubles the frequency as the test circuit 211 in the scribe line, the test circuit 211 receives a pulse signal provided from the tester equipment at the time of testing. The pulse signal having a frequency higher than that of the pulse signal is supplied to the probe card 202, and the probe card 202 transfers the pulse signal of the high frequency supplied by the test circuit 211 to the integrated circuit semiconductor chip. This allows the testing of integrated circuit semiconductor chips with pulse signals at higher frequencies than that provided by the tester equipment.

The frequency multiplying circuit can be simply implemented using an Exclusive or Logic Operation Gate 301 of the other two pulse signals provided from the tester equipment, as shown in FIG.

When the two pulse signals In1 and In2 provided from the tester equipment have the same frequency but different start points of the signals, when the two pulse signals In1 and In2 are logically ORed, the two pulses The frequency of the output pulse signal out becomes twice the frequency of the input pulse signal because the signal becomes high only when the state of the signal is different.

Since the integrated circuit semiconductor chip test time increases proportionally as the density of the integrated circuit semiconductor chip increases, a built-in self test (BIST) circuit formed in the integrated circuit semiconductor chip may also be formed in the scribe line. Can be.

In addition to the test on the semiconductor substrate, it can be tested in the same manner as described above in a module in which multiple integrated circuit semiconductor chips are assembled at the same time.

Although the embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains (ie, those skilled in the art) should know that the present invention may be embodied in other specific forms without changing its technical spirit or essential features. It will be appreciated that it may be practiced.

Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

It is intended that the scope of the invention be indicated by the following claims rather than the foregoing description, and that all changes or modifications derived from the claims and their equivalents shall be included within the scope of the invention. Should be.

According to the present invention made as described above, by using a scribe line (Scribe Line) formed between adjacent semiconductor chips in order to individualize the plurality of semiconductor chips, by using the area of the semiconductor chip efficiently Can be.

1 is a plan view of a semiconductor chip and a scribe line formed on a semiconductor substrate.

2 is a cross-sectional view showing a semiconductor chip test method according to the present invention.

3 is a diagram illustrating a frequency double circuit for a semiconductor chip test method according to an exemplary embodiment of the present invention.

(Explanation of symbols for the main parts of the drawing)

101 to 104: semiconductor chip

111 to 116 scribe lines

201: tester equipment

202: probe card

203: test circuit

301: frequency double circuit

Claims (3)

In the semiconductor chip test, a plurality of semiconductor chips including circuit elements are formed, and the plurality of semiconductor chips are tested in a semiconductor substrate in which a scribe line is formed between adjacent semiconductor chips so that the plurality of semiconductor chips are individualized. In A test circuit is formed on the scribe line, and the plurality of semiconductor chips are tested using the test circuit. The method of claim 1, And testing the plurality of semiconductor chips by applying an output signal of the test circuit to a probe card that delivers a power voltage or a function signal to the plurality of semiconductor chips. The method of claim 2, The test circuit is a semiconductor chip test method, characterized in that the frequency multiplier.