KR20050027466A - Thin film transistor having a black matrix and method for fabricating a polysilicon used in tft - Google Patents
Thin film transistor having a black matrix and method for fabricating a polysilicon used in tft Download PDFInfo
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- KR20050027466A KR20050027466A KR1020030063751A KR20030063751A KR20050027466A KR 20050027466 A KR20050027466 A KR 20050027466A KR 1020030063751 A KR1020030063751 A KR 1020030063751A KR 20030063751 A KR20030063751 A KR 20030063751A KR 20050027466 A KR20050027466 A KR 20050027466A
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- thin film
- film transistor
- polycrystalline silicon
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- 239000011159 matrix material Substances 0.000 title claims abstract description 29
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 29
- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 title claims description 22
- 229920005591 polysilicon Polymers 0.000 title description 2
- 238000002425 crystallisation Methods 0.000 claims abstract description 30
- 229910052751 metal Inorganic materials 0.000 claims abstract description 27
- 239000002184 metal Substances 0.000 claims abstract description 27
- 230000008025 crystallization Effects 0.000 claims abstract description 23
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000007790 solid phase Substances 0.000 claims abstract description 8
- 239000012212 insulator Substances 0.000 claims abstract description 5
- 239000010410 layer Substances 0.000 claims description 65
- 239000010408 film Substances 0.000 claims description 17
- 230000005684 electric field Effects 0.000 claims description 12
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 10
- 238000010438 heat treatment Methods 0.000 claims description 8
- 229910004205 SiNX Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052804 chromium Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 230000007423 decrease Effects 0.000 claims description 4
- 229910052750 molybdenum Inorganic materials 0.000 claims description 4
- 229910052709 silver Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 229910052721 tungsten Inorganic materials 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims description 3
- 239000004973 liquid crystal related substance Substances 0.000 claims description 2
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910005881 NiSi 2 Inorganic materials 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000005499 laser crystallization Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000012071 phase Substances 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78633—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device with a light shield
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02587—Structure
- H01L21/0259—Microstructure
- H01L21/02595—Microstructure polycrystalline
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/326—Application of electric currents or fields, e.g. for electroforming
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- Thin Film Transistor (AREA)
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Abstract
Description
[산업상 이용분야][Industrial use]
본 발명은 블랙 매트릭스를 포함하는 박막 트랜지스터 및 이 박막 트랜지스터에 사용되는 다결정 실리콘의 제조 방법에 관한 것으로, 더욱 상세하게는 고상 결정화법에 의하여 형성되는 다결정 실리콘의 제조 방법 및 이 다결정 실리콘을 사용하는 박막 트랜지스터에 관한 것이다. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor comprising a black matrix and a method for producing polycrystalline silicon used in the thin film transistor, and more particularly, to a method for producing polycrystalline silicon formed by a solid phase crystallization method and a thin film using the polycrystalline silicon. It relates to a transistor.
[종래 기술] [Prior art]
종래 다결정 실리콘 형성 방법으로는 고상 결정화법(solid phase crystallization: SPC)이 있다. 이 방법은 저가의 장비를 사용할 수 있는 장점이 있으나 결정화 온도가 높고 결정화 시간이 길기 때문에 유리 기판을 사용할 수 없는 단점이 있다. Conventional polycrystalline silicon formation methods include solid phase crystallization (SPC). This method has the advantage of using inexpensive equipment but has a disadvantage in that a glass substrate cannot be used because of high crystallization temperature and long crystallization time.
저온에서 결정화할 경우 제조 단가가 낮고, 대면적화가 가능하며 반도체 소자로 이용될 경우 성능면에서 고온 다결정 물질과 저온 결정화 방법이 유리하다. 상기와 같은 요구에 의해 400 ℃ 이하의 저온에서 결정화할 수 있는 레이저 결정화법이 제시되었는데, 이 방법은 그 산물이 우수한 특성을 갖는 장점이 있으나 균일한 결정을 얻기 어렵고 고가의 장비 및 낮은 생산성으로 인하여 대면적 기판 위에 제작할 경우 문제점이 있다. When the crystallization at low temperature, low production cost, large area is possible, and when used as a semiconductor device, high temperature polycrystalline material and low temperature crystallization method are advantageous in terms of performance. The laser crystallization method that can crystallize at a low temperature below 400 ℃ by the above requirements has been proposed, this method has the advantage that the product has excellent characteristics, but difficult to obtain uniform crystals, due to expensive equipment and low productivity There is a problem when fabricating on a large area substrate.
다른 저온 결정화 방법으로 금속 유도 결정화(Metal Induced Crystallization; MIC)법이 있는데, 이 방법은 특정 금속을 비정질 물질에 접촉하게 하여 비정질 물질이 결정화 온도를 낮추는 방법이다. 그 예로, 니켈 금속에 의한 다결정 실리콘의 제조 방법에서, 니켈 실리사이드의 마지막 상인 NiSi2가 결정화 핵으로 작용하여 결정화를 촉진하게 된다. 실제로 NiSi2는 실리콘과 동일한 구조를 가지며, 비정질 실리콘의 결정화 핵으로 작용하여 (111) 방향으로 결정화를 촉진한다.Another low temperature crystallization method is Metal Induced Crystallization (MIC) method, in which a specific metal is brought into contact with an amorphous material so that the amorphous material lowers the crystallization temperature. For example, in the method for producing polycrystalline silicon by nickel metal, NiSi 2 , the last phase of nickel silicide, acts as a crystallization nucleus to promote crystallization. In fact, NiSi 2 has the same structure as silicon, and acts as a crystallization nucleus of amorphous silicon to promote crystallization in the (111) direction.
이와 같은 금속 유도 결정화 방법에서 전기장을 인가함으로써 열처리 시간이 매우 짧아지고, 열처리 온도도 매우 낮아지게 되는데, 인가하는 전기장의 세기가 커질수록 그 효과는 증가된다. In such a metal-induced crystallization method, by applying an electric field, the heat treatment time is very short and the heat treatment temperature is also very low. As the intensity of the applied electric field increases, the effect increases.
그러나, 전기장의 세기가 커질수록 열처리되는 비정질 물질을 통해 흐르는 전류의 양이 증가하게 되고, 이로 인해 원하지 않는 급격한 온도 상승을 초래할 수 있다. 즉, 발열 효과(Joule Heating)로 인해 전기장의 세기를 크게 하는 데에는 한계가 있어, 결정화 시간 단축 및 결정화 온도 감소에도 한계가 있다.However, as the intensity of the electric field increases, the amount of current flowing through the amorphous material to be heat-treated increases, which may result in an unexpected sudden temperature rise. That is, there is a limit in increasing the intensity of the electric field due to the heating effect (Joule Heating), there is also a limit in shortening the crystallization time and reducing the crystallization temperature.
본 발명은 위에서 설명한 바와 같은 문제점을 해결하기 위하여 안출된 것으로서, 본 발명의 목적은 고상 결정화법의 사용하여 비정질 실리콘을 결정화시킬 때 발열 효과를 이용하여 낮은 결정화 온도에서 빠른 시간 내에 비정질 실리콘을 결정화하는 다결정 실리콘의 제조 방법 및 이를 사용하는 박막트랜지스터를 제공하는 것이다. SUMMARY OF THE INVENTION The present invention has been made to solve the problems described above, and an object of the present invention is to crystallize amorphous silicon in a short time at a low crystallization temperature by using an exothermic effect when crystallizing amorphous silicon using a solid phase crystallization method. The present invention provides a method of manufacturing polycrystalline silicon and a thin film transistor using the same.
본 발명은 상기한 목적을 달성하기 위하여, 본 발명은 The present invention to achieve the above object, the present invention
절연 기판,Insulation board,
상기 절연 기판 상에 형성된 블랙 매트릭스 층,A black matrix layer formed on the insulating substrate,
상기 블랙 매트릭스 층 상부에 형성되는 버퍼층, 및 A buffer layer formed on the black matrix layer, and
상기 버퍼층 상에 고상 결정화법에 의하여 형성된 다결정 실리콘을 포함하는 것을 특징으로 하는 박막 트랜지스터를 제공한다. Provided is a thin film transistor comprising polycrystalline silicon formed on the buffer layer by solid phase crystallization.
또한, 본 발명은 In addition, the present invention
절연 기판 상에 블랙 매트릭스 층을 형성하는 단계,Forming a black matrix layer on the insulating substrate,
상기 블랙 매트릭스 층위에 버퍼층을 형성하는 단계,Forming a buffer layer on the black matrix layer,
상기 버퍼층 상에 비정질 실리콘층을 형성하는 단계, Forming an amorphous silicon layer on the buffer layer,
상기 비정질 실리콘 층상에 금속 박막층을 형성하는 단계, 및Forming a metal thin film layer on the amorphous silicon layer, and
상기 금속 박막층에 전계 또는 자계를 인가하는 동시에 기판을 열처리하여 상기 비정질 실리콘층을 다결정 실리콘으로 결정화하는 단계를 포함하는 것을 특징으로 하는 다결정 실리콘의 제조 방법을 제공한다. And applying a electric field or a magnetic field to the metal thin film layer and heat-treating the substrate to crystallize the amorphous silicon layer into polycrystalline silicon.
이하, 본 발명을 첨부한 도면을 참조하여 더욱 상세히 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in more detail.
도 1a 및 도 1b는 본 발명의 일실시예에 따른 다결정 실리콘의 제조 방법을 나타내는 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing polycrystalline silicon according to an embodiment of the present invention.
도 1a 및 도 1b를 참조하면, 기판(10) 위에 블랙 매트릭스 층(20)을 형성한다. 상기 블랙 매트릭스 층(20)은 증착되는 두께 방향으로 금속 성분의 농도는 증가하고 절연성 투명막의 농도는 감소하는 MIHL(Metal Insulator Hybrid Layer)을 사용한다. 1A and 1B, a black matrix layer 20 is formed on the substrate 10. The black matrix layer 20 uses a metal insulator hybrid layer (MIHL) in which the concentration of the metal component increases and the concentration of the insulating transparent film decreases in the thickness direction in which the black matrix layer 20 is deposited.
상기 MIHL 중 상기 절연성 투명막으로는 SiO2 또는 SiNx를 사용하고, 상기 금속 성분으로는 Al, Cr, Mo, W, Ti, Ag, 및 Cu로 이루어진 군에서 선택되는 1종의 금속을 사용한다.Among the MIHL, SiO 2 or SiNx is used as the insulating transparent film, and one metal selected from the group consisting of Al, Cr, Mo, W, Ti, Ag, and Cu is used as the metal component.
상기 MIHL은 절연성 투명막과 금속 성분을 공증착 또는 공스퍼터링(채-sputtering)의 방법으로 증착한다. The MIHL deposits an insulating transparent film and a metal component by a method of co-deposition or co-sputtering.
위와 같이 블랙 매트릭스 층(20)을 형성한 후 상기 블랙 매트릭스 층(20) 상부에 버퍼층(30)을 형성한다. 상기 버퍼층(30)으로는 뒤에 형성될 다결정 실리콘과의 계면특성을 위하여 SiO2를 사용하거나 기판으로부터 발생되는 알칼리 이온의 패시베이션(passivation)을 위하여 SiO2/SiNx의 이중막을 사용할 수 있다.After the black matrix layer 20 is formed as above, the buffer layer 30 is formed on the black matrix layer 20. As the buffer layer 30, SiO 2 may be used for interfacial properties with polycrystalline silicon to be formed later, or a double layer of SiO 2 / SiN x may be used for passivation of alkali ions generated from a substrate.
이어서, 상기 버퍼층(30) 상부에 비정질 실리콘(40)을 PECVD(Plazma Enhanced Chemical Vapor Deposition) 또는 LPCVD(Low Pressure Chemical Vapor Deposition) 등의 증착 방법으로 형성한다. Subsequently, amorphous silicon 40 is formed on the buffer layer 30 by a deposition method such as plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD).
그리고 나서, 비정질 실리콘층(40)의 양단에 전기장을 인가할 수 있는 전극(50)을 형성한다. 자계장을 인가하는 경우에는 자석을 위치시킨다.Then, the electrode 50 capable of applying an electric field to both ends of the amorphous silicon layer 40 is formed. When a magnetic field is applied, the magnet is placed.
계속해서, 전계 또는 자계(50)를 인가하고 동시에 기판을 열처리하여 상기 비정질 실리콘층(40)을 결정화시킨다. Subsequently, the amorphous silicon layer 40 is crystallized by applying an electric field or a magnetic field 50 and simultaneously heat-treating the substrate.
이때, 전계를 인가시키는 경우에는 인가 전압이 40 내지 60V/cm 이고, 인가 시간은 1시간 이하, 열처리 온도는 600 ℃ 이하인 것이 바람직하다. At this time, when applying an electric field, it is preferable that an applied voltage is 40-60V / cm, an application time is 1 hour or less and heat processing temperature is 600 degrees C or less.
또한, 자계를 인가하는 경우에는 자기장의 세기는 200 내지 800 Gauss이고, 인가 시간은 1 시간이하, 열처리 온도는 600 ℃ 이하인 것이 바람직하다.In addition, when the magnetic field is applied, the strength of the magnetic field is 200 to 800 Gauss, the application time is preferably 1 hour or less, and the heat treatment temperature is preferably 600 ° C. or less.
이와 같은 공정을 거치게 되면, 비정질 실리콘은 발열 효과(Joule Heating) 에 의하여 통상의 방법보다 더욱 빠른 시간에 비정질 실리콘이 녹으면서 결정을 형성하게 되어 다결정 실리콘(41)의 형성을 촉진하게 된다. Through such a process, the amorphous silicon melts the amorphous silicon at a faster time than the conventional method by the heating effect, thereby promoting the formation of the polycrystalline silicon 41.
도 2a 내지 도 2e는 위의 다결정 실리콘 박막의 제조 방법을 사용하여 박막 트랜지스터를 제조하는 방법을 순서적으로 도시한 단면도이다. 2A through 2E are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor using the above method of manufacturing a polycrystalline silicon thin film.
도 2a 및 도 2b를 참조하면, 위에서 설명한 방법과 동일한 방법으로 다결정실리콘 층을 형성한다. 2A and 2B, a polysilicon layer is formed in the same manner as described above.
상기 블랙 매트릭스 층(20)은 3000-4000 Å의 두께로 형성하는 것이 바람직하며, 상기 버퍼층(30)은 2000 내지 5000 Å의 두께로 형성하는 것이 바람직하다. The black matrix layer 20 is preferably formed to a thickness of 3000-4000 mm 3, and the buffer layer 30 is preferably formed to a thickness of 2000-5000 mm 3.
다결정 실리콘층(40)을 형성한 후 전극 또는 자석(50)을 제거한다. 그리고 나서, 도 2c에 도시된 바와 같이, 다결정 실리콘층(41)을 패터닝하고, 상기 패터닝된 다결정 실리콘층(41) 상부에 기판 전면에 걸쳐 게이트 절연막(60)으로 실리콘 산화막 또는 실리콘 질화막을 형성한다. After forming the polycrystalline silicon layer 40, the electrode or the magnet 50 is removed. Then, as shown in FIG. 2C, the polycrystalline silicon layer 41 is patterned, and a silicon oxide film or a silicon nitride film is formed on the patterned polycrystalline silicon layer 41 as the gate insulating film 60 over the entire substrate. .
그리고나서, 상기 게이트 절연막(60) 상부에 게이트 전극(70)을 형성한다. 상기 게이트 전극(70)은 단일 전극을 사용하여도 되고 이중 전극을 사용할 수도 있다. Then, the gate electrode 70 is formed on the gate insulating film 60. The gate electrode 70 may use a single electrode or a double electrode.
계속해서, 도 2d에 도시된 바와 같이, 상기 게이트 전극(70)을 마스크로 하여 이온 주입 공정을 시행하여 게이트 전극(70)의 양측의 다결정 실리콘층(41)에 이온을 주입하여 소스/드레인 영역을 형성하고, 결정화 온도보다 낮은 온도에서 활성화시킨 다음, 상기 게이트 전극(70) 상부에 기판 전면에 걸쳐 층간 절연막(80)을 형성한다. Subsequently, as shown in FIG. 2D, an ion implantation process is performed using the gate electrode 70 as a mask to inject ions into the polycrystalline silicon layer 41 on both sides of the gate electrode 70 to thereby source / drain regions. Is formed, activated at a temperature lower than the crystallization temperature, and then an interlayer insulating film 80 is formed on the gate electrode 70 over the entire substrate.
이어서, 도 2e에 도시된 바와 같이, 상기 다결정 실리콘층(41)의 일부가 노출되도록 층간 절연막(80)과 게이트 절연막(60)을 식가하여 비아홀을 형성하고, 상기 비아홀을 금속으로 충전시킨 후 패터닝하여 소스/드레인 전극(90, 100)을 형성한다. Subsequently, as shown in FIG. 2E, the interlayer insulating film 80 and the gate insulating film 60 are etched to expose a portion of the polycrystalline silicon layer 41 to form via holes, and the via holes are filled with metal and then patterned. To form the source / drain electrodes 90 and 100.
이상과 같이 형성된 박막 트랜지스터는 블랙 매트릭스 층(20)은 증착되는 두께 방향으로 금속 성분의 농도는 증가하고 절연성 투명막의 농도는 감소하는 MIHL(Metal Insulator Hybrid Layer)을 사용하며, 상기 MIHL 중 상기 절연성 투명막은 SiO2 또는 SiNx이고, 상기 금속 성분으로는 Al, Cr, Mo, W, Ti, Ag, 및 Cu로 이루어진 군에서 선택되는 1종의 금속을 사용한다.The thin film transistor formed as described above uses a metal insulator hybrid layer (MIHL) in which the concentration of the metal component increases and the concentration of the insulating transparent film decreases in the thickness direction in which the black matrix layer 20 is deposited. The film is SiO 2 or SiNx, and the metal component uses one metal selected from the group consisting of Al, Cr, Mo, W, Ti, Ag, and Cu.
한편, 적층되는 블랙 매트릭스 층(20)의 두께는 3000 내지 4000 Å인 것이 바람직하다.On the other hand, the thickness of the stacked black matrix layer 20 is preferably 3000 to 4000 mm 3.
또한, 블랙 매트릭스 층 상부에 형성되는 상기 버퍼층으로는 SiO2 또는 SiO2/SiNx 중 하나의 물질을 사용하며, 상기 버퍼층의 적층 두께는 2000 내지 5000 Å인 것이 바람직하다.In addition, as the buffer layer formed on the black matrix layer, one of SiO 2 or SiO 2 / SiN x is used, and the stacking thickness of the buffer layer is preferably 2000 to 5000 mm 3.
이와 같이 제조된 박막 트랜지스터는 평판 표시 소자에 사용될 수 있으며, 바람직하기로는 유기 전계 발광 소자 또는 액정 표시 소자에 사용된다.The thin film transistor manufactured as described above may be used in a flat panel display device, and is preferably used in an organic light emitting device or a liquid crystal display device.
이상과 같이 본 발명에서는 고상 결정화법을 사용하여 비정질 실리콘의 결정화시 기판과 버퍼층 사이에 블랙 매트릭스층을 형성하여서 열처리할 때 전계 또는 자계를 인가하는 경우 발열 효과(joule heating)를 이용함으로써 결정화 시간 및 결정화 온도를 낮추면서도 결정화를 촉진시킬 수 있다. As described above, in the present invention, when a black matrix layer is formed between the substrate and the buffer layer during the crystallization of amorphous silicon using the solid phase crystallization method, when an electric field or a magnetic field is applied, crystallization time and It is possible to promote crystallization while lowering the crystallization temperature.
도 1a 및 도 1b는 본 발명의 일실시예에 따른 다결정 실리콘의 제조 방법을 나타내는 단면도이다.1A and 1B are cross-sectional views illustrating a method of manufacturing polycrystalline silicon according to an embodiment of the present invention.
도 2a 내지 도 2e는 본 발명의 다결정 실리콘 박막의 제조 방법을 사용하여 박막 트랜지스터를 제조하는 방법을 순서적으로 도시한 단면도이다. 2A to 2E are cross-sectional views sequentially illustrating a method of manufacturing a thin film transistor using the method of manufacturing a polycrystalline silicon thin film of the present invention.
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| KR100730154B1 (en) * | 2005-10-18 | 2007-06-19 | 삼성에스디아이 주식회사 | Flat panel display device and manufacturing method thereof |
| WO2009066949A2 (en) * | 2007-11-21 | 2009-05-28 | Jae-Sang Ro | Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same |
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| KR100730154B1 (en) * | 2005-10-18 | 2007-06-19 | 삼성에스디아이 주식회사 | Flat panel display device and manufacturing method thereof |
| WO2009066949A2 (en) * | 2007-11-21 | 2009-05-28 | Jae-Sang Ro | Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same |
| WO2009066949A3 (en) * | 2007-11-21 | 2009-08-27 | Jae-Sang Ro | Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same |
| KR100946808B1 (en) * | 2007-11-21 | 2010-03-11 | 주식회사 엔씰텍 | Fabricating method of polycrystalline silicon thin film, polycrystalline silicon thin film fabricated using the same, and thin film transistor comprising the same |
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