KR20020090429A - Process for crystallizing amorphous silicon and its application - fabricating method of thin film transistor and TFT-LCD - Google Patents

Abstract

PURPOSE: A poly crystallizing method and method for fabricating a thin film transistor and a liquid crystal display device are provided to control an amount of metal by using a metal collecting layer, thereby supplying a proper amount for uniform crystallization. CONSTITUTION: A poly crystallizing method includes the steps of forming a buffer layer(202) on an insulating substrate(201), forming an amorphous silicon layer(203) on the buffer layer, forming a metal thin film layer(204) on the amorphous silicon layer, forming a metal collecting layer(204a) on the metal thin film layer, and crystallizing the amorphous silicon layer to a poly crystalline silicon by heating the substrate simultaneously with applying electric fields to the surface resistance heating material via electrodes.

Description

Process for crystallizing amorphous silicon and its application-fabricating method of thin film transistor and TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor, and more particularly, to a polycrystallization method using an electric field applied metal induction crystallization method, and a method for manufacturing a thin film transistor and a liquid crystal display device using the same.

Although TFT-LCDs have high density and large area, and display and driving circuits are fabricated on the same substrate, there is an urgent need for increasing mobility of thin film transistors, which are switching elements. It is difficult to satisfy this advantage with a thin film transistor (a-Si: H TFT).

Recently, polycrystalline silicon TFTs (Poly-Si TFTs) have attracted much attention as a method for effectively solving these problems. Since polycrystalline silicon TFTs have high mobility, they have the advantage of allowing peripheral circuits to be integrated on glass substrates, thus attracting much attention in terms of reducing production costs.

In addition, polycrystalline silicon TFTs have higher mobility than amorphous silicon TFTs, and are advantageous as switching elements of high-resolution panels, and are suitable for projection panels in which a lot of light is emitted due to less photocurrent compared to amorphous silicon TFTs.

There have been many reports on the method of fabricating polycrystalline silicon, and there are largely a method of directly depositing polycrystalline silicon and a method of forming polycrystalline silicon by depositing amorphous silicon and then crystallizing.

The former methods include Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Among them, the LPCVD method has a substrate temperature of 550 ° C. or higher. Due to the use of expensive silica or quartz, the manufacturing cost is high, which is not suitable for mass production. In the case of PECVD, the SiF ₄ / SiH ₄ / H ₂ mixed gas can be deposited at 400 ° C. or lower, but it is difficult to suppress the grains. It is known to have serious problems.

The latter method, that is, a method of depositing and crystallizing amorphous silicon includes a solid phase crystallization (SPC) method and an excimer laser annealing (ELA) method.

The ELA method is a method of crystallizing a thin film in an instant by administering an excimer laser having a strong energy in an amorphous silicon thin film to form a polycrystalline silicon thin film having a large crystal grain size and excellent crystallinity. This is possible. However, the ELA method requires an expensive accessory equipment, such as an excimer laser, and thus can be said to have a limitation in mass production and large area LCD driving TFTs.

Solid phase crystallization is mainly a method of crystallizing an amorphous silicon thin film by using a furnace heating method in a furnace. Likewise, polycrystalline silicon thin film having excellent crystallinity can be produced, but is crystallized because it proceeds by solid phase reaction. Due to the slow reaction rate, a long crystallization time of several tens of hours or more is required at a high temperature of 600 ° C. or more.

In addition to the above methods, a lot of research has recently been conducted to lower the crystallization temperature in order to use polycrystalline silicon in the manufacture of large-area liquid crystal display devices, one of which is a metal induced crystallization method and furthermore, Electric field enhanced metal induced crystallization (ESD), which applies an electric field to induction crystallization and improves the rate of crystallization, is also being studied.

According to these methods, when a specific type of metal is contacted with amorphous silicon, the crystallization temperature of the amorphous silicon can be lowered to 500 ° C. or lower, and the metal induction crystallization effect is known to occur in various kinds of metals.

Metal-induced crystallization differs in causing crystallization depending on the type of metal. That is, the crystallization phenomenon may vary depending on the type of metal in contact with the hydrogenated amorphous silicon (a-Si: H).

For example, metals such as aluminum (Al), gold (Au), and silver (Ag) are governed by the diffusion of silicon (Si) at the interface with amorphous silicon. In other words, at the interface between the metal and the silicon, a metastable silicide phase is formed by diffusion of silicon, and the silicide lowers the crystallization energy to promote the crystallization of silicon.

In contrast, in metals such as nickel (Ni) and titanium (Ti), diffusion of metals by annealing is dominant. That is, a silicide phase is formed by metal diffusion from the metal and silicon interface in the direction of the silicon layer, and the silicide promotes crystallization and lowers the crystallization temperature.

Hereinafter, a polycrystallization method according to the prior art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of crystallizing an amorphous silicon thin film according to the prior art.

As shown in FIG. 1A, a buffer layer 102 is formed of a silicon oxide film (SiO ₂ ) on an insulating substrate 101, an amorphous silicon 103 is deposited on the buffer layer, and then a metal thin film layer serving as a crystallization catalyst. 104 is formed in the amorphous silicon layer. Here, nickel (Ni) or the like is used as the metal thin film layer 104.

As shown in FIG. 1B, an electrode 105 for applying an electric field on the metal thin film layer 104 is added. Molybdenum (Mo) is used as the material for the electrode.

Subsequently, a predetermined electric field is applied to the electrode 105, and at the same time, a heat treatment is performed. As shown in FIG. 1C, as a result of the crystallization of FIG. As a result, a silicide phase (NiSi ₂ ) is formed. The silicide (NiSi ₂ ) promotes crystallization of the silicon thin film to crystallize the amorphous silicon thin film into the polycrystalline silicon thin film 106 in a state where the crystallization temperature is lowered.

However, the conventional polycrystallization method as described above has the following problems.

After crystallization of the amorphous silicon layer, the unreacted metal 104a (see FIG. 1C) remains on the polycrystalline silicon layer, causing leakage current, and also degrading the crystallization reaction rate due to surface heat loss and defects in the crystal grains after crystallization. There are disadvantages such as the presence of defects such as (Point defect).

The present invention has been made to solve the above problems, the object of the present invention is to provide a polycrystallization method for improving the device characteristics of the thin film transistor by minimizing the amount of the unreacted metal.

Another object of the present invention is to provide a method for manufacturing a thin film transistor and a liquid crystal display using the polycrystallization method.

1A to 1C are cross-sectional views for explaining a polycrystallization method according to the related art.

Figure 2a to 2d is a cross-sectional view for explaining the polycrystallization method according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using the polycrystallization method of the present invention.

Explanation of symbols for the main parts of the drawings

201: substrate 202: buffer layer

203: amorphous silicon layer 204: metal thin film layer

204a: metal collecting layer

The polycrystallization method of the present invention for achieving the above object comprises the steps of forming a buffer layer on an insulating substrate, forming an amorphous silicon layer on the buffer layer, forming a metal thin film layer on the amorphous silicon layer; And forming a metal collection layer on the metal thin film layer, and applying an electric field to the metal thin film layer and simultaneously heat-treating the substrate to crystallize the amorphous silicon layer into polycrystalline silicon.

The method of manufacturing a thin film transistor using the polycrystallization method as described above includes forming a buffer layer on an insulating substrate, forming an amorphous silicon layer on the buffer layer, and forming a metal thin film layer on the amorphous silicon layer. And forming a metal collection layer on the metal thin film layer, applying an electric field to the metal thin film layer, and heat treating a substrate to crystallize the amorphous silicon layer, and crystallizing the amorphous silicon layer. Forming a semiconductor layer of the shape, forming a gate insulating film on the entire surface of the substrate including the semiconductor layer, forming a gate electrode on a predetermined portion of the gate insulating film, and overlapping the gate electrode in the semiconductor layer. Forming a source / drain region by ion doping a region that is not Activating a layer, forming an interlayer insulating layer on the semiconductor layer and the gate electrode, exposing a portion of the source / drain region, and forming a source electrode and a drain electrode to be connected to the exposed source / drain region. It is made, including the process.

In addition, the method of manufacturing a liquid crystal display device using the thin film transistor as described above may include preparing a first substrate and a second substrate, forming a buffer layer on the first substrate, and forming an amorphous silicon layer on the buffer layer. Forming a metal thin film layer on the amorphous silicon layer, forming a metal collecting layer on the metal thin film layer, applying an electric field to the metal thin film layer, and heat treating the substrate to simultaneously heat the substrate. Crystallizing the crystal, forming the island-like semiconductor layer after crystallizing the amorphous silicon layer, forming a gate insulating film on the entire surface including the semiconductor layer, and forming a gate electrode at a predetermined portion on the gate insulating film. And forming a gate line, and doping a region of the semiconductor layer that does not overlap the gate electrode. / Forming a drain region, activating the semiconductor layer, forming a first insulating film on the semiconductor layer and the gate electrode, and then exposing the source / drain region, and the exposed source / Forming a source / drain electrode and data lines so as to be connected to the drain region, forming a pixel electrode electrically connected to the drain electrode, and forming a liquid crystal layer between the first substrate and the second substrate. Characterized in that comprises a.

Hereinafter, a polycrystallization method and a method of manufacturing a thin film transistor using the same according to the present invention will be described in detail with reference to the drawings.

2A through 2D are cross-sectional views illustrating a polycrystallization method according to the present invention, and FIGS. 3A through 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

As shown in FIG. 2A, after forming a buffer layer 202 made of a silicon oxide film or a silicon nitride film on the insulating substrate 201 by chemical vapor deposition, SiH ₄ and H _{2 are} mixed on the buffer layer 202. The gas is formed using a plasma enhanced chemical vapor deposition method to form an amorphous silicon (a-Si: H) layer 203.

Here, the buffer layer 202 prevents the impurity component of the glass substrate 201 from diffusing into the amorphous silicon layer 203, and blocks the heat inflow into the glass substrate 201 in a future crystallization process. .

Thereafter, the metal thin film layer 204 is formed on the amorphous silicon layer 203 by using a sputtering method. In this case, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt), etc. are used as the metal thin film layer 204, and the deposition amount is 1 × 10 ¹⁸ when converted into the number of atoms per unit volume. (Atomic number) / cm <^3> or more.

The metal collecting layer 204a is formed on the metal thin film layer 204. In this case, the metal collection layer 204a is formed of amorphous silicon doped with phosphorus (P) ions or an n + amorphous silicon layer using SiH ₄ and PH ₃ gas.

As shown in FIG. 2B, the left and right predetermined portions of the metal collecting layer 204a are etched to expose the metal thin film layer 204, and then an electrode for applying an electric field on the exposed metal thin film layer 204 ( 205) is added. In this case, as the material for the electrode 205, molybdenum (Mo), graphite, or the like is used.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205 and the substrate is heat-treated at the same time to crystallize the amorphous silicon layer. At this time, it is preferable that the applied voltage is set to 10 to 500 V / cm, the application time is 15 to 300 minutes, and the heat treatment temperature of the substrate is set to 400 to 600 ° C.

Through this process, as shown in FIG. 2D, the amorphous silicon layer 203 is crystallized into the polycrystalline silicon layer 206. The crystallization process is as follows.

The metal thin film layer is solid phase diffused to an amorphous silicon layer to form metal silicide. For example, nickel (Ni) forms nickel silicide (NiSi ₂ ).

The metal silicide acts as a catalyst for crystallization of amorphous silicon, that is, a crystallization nucleus, and uniform crystallization of amorphous silicon proceeds at a high crystallization rate due to the crystallization nucleus.

On the other hand, during the crystallization process, some of the metal moves to the metal collection layer and is paired with phosphorus (P) of the metal collection layer (see FIG. 2C). As a result, the amount of metal in the silicon layers 203 and 206 as a whole. And the amount of metal in the metal collection layer is saturated to an equivalent concentration with respect to the metal solubility at the crystallization temperature, and can be controlled to 1 × 10 ¹⁴ (atomic number) / cm ³ or less.

Referring to the thin film transistor manufacturing method using the polycrystallization method as follows.

First, as shown in FIG. 3A, the buffer layer 202 and the amorphous silicon layer (a-Si: H) 203 made of silicon oxide (SiO ₂ ) material are formed on the insulating substrate 201 by chemical vapor deposition. Form sequentially.

Thereafter, the metal thin film layer 204 is formed on the amorphous silicon layer 203 by sputtering. In this case, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt), etc. are used as the metal thin film layer 204, and the deposition amount is 1 × 10 ¹⁸ when converted into the number of atoms per unit volume. (Atomic number) / cm <^3> or more.

A metal collecting layer is formed on the metal thin film layer 204. In this case, the metal collection layer 204a is formed of amorphous silicon doped with phosphorus (P) ions or an n + amorphous silicon layer using SiH ₄ and PH ₃ gas.

Subsequently, as shown in FIG. 3B, the left and right predetermined portions of the metal collecting layer 204a are etched to expose the metal thin film layer 204, and then an electric field is applied to the exposed metal thin film layer 204. An electrode 205 is added. In this case, as the material for the electrode 205, molybdenum (Mo), graphite, or the like is used.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205, and at the same time, the insulating substrate is heat-treated to crystallize the amorphous silicon layer 203. At this time, the voltage applied to the electrode 205 is 10 to 500V / cm, the application time is about 15 to 300 minutes, the heat treatment temperature is preferably set to 400 to 600 ℃.

After the crystallization of the amorphous silicon layer 203 into the polycrystalline silicon layer 206 through the above process, as shown in FIG. 3C, the polycrystalline silicon layer 206 is patterned into an island shape, and then the polycrystalline silicon layer is formed. A gate insulating film 207 made of silicon oxide film or silicon nitride film is formed on the entire surface of the substrate including 206. Subsequently, a double metal layer of AlNd and Mo is sequentially stacked on the gate insulating layer 207 by sputtering, and then patterned to form a gate electrode 208 having a double layer structure.

3D, n + ions are implanted into the polycrystalline silicon layer 206 on both sides of the gate electrode 208 through an ion implantation process using the gate electrode 208 as a mask to form a source / drain region. After the formation and activation at a temperature lower than the crystallization temperature, an interlayer insulating film 209 is formed on the entire surface of the substrate including the gate electrode 208.

Subsequently, as shown in FIG. 3E, the interlayer insulating layer 209 and the gate insulating layer 207 are etched to expose a predetermined region of the n + ion-doped polycrystalline silicon layer 206 to form a via hole. After stacking the metal layers of AlNd and Mo in order to sufficiently fill the via holes, and forming the source / drain electrodes 210 and 211 by patterning, the thin film transistor manufacturing process using the polycrystallization method according to the present invention is performed. Is complete.

Hereinafter, a method of manufacturing a liquid crystal display using the above-described thin film transistor manufacturing process will be described.

4A to 4F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention.

First, as shown in FIG. 4A, after forming a buffer layer 202 made of a silicon oxide film on the first substrate 201a, a plasma chemical vapor phase using SiH ₄ and H ₂ mixed gas is formed on the buffer layer 202. An amorphous silicon layer 203 is formed by vapor deposition.

Although not shown in the drawings, a metal thin film layer and a metal collecting layer are sequentially formed on the amorphous silicon layer.

Thereafter, as shown in FIG. 4B, the amorphous silicon layer 203 is crystallized through the above-described crystallization process, and then, as shown in FIG. 4C, the amorphous silicon layer 203 may be used as a channel layer of a thin film transistor. Pattern it into island shapes so that it Thereafter, after forming the gate insulating film 207 made of silicon nitride film or silicon oxide film on the entire surface including the island-shaped polycrystalline silicon layer 206, after laminating a double metal layer of AlNd and Mo on the gate insulating film, Patterning forms a gate electrode 208 and a gate line (not shown) of the thin film transistor.

Thereafter, as shown in FIG. 4D, n + ions are implanted into the polycrystalline silicon layer 206 using the gate electrode 208 as a mask to form and activate a source / drain region, and then the gate electrode 208 and An interlayer insulating film 209 is formed on the entire surface including the gate line.

Subsequently, as shown in FIG. 4E, the interlayer insulating film 209 and the gate insulating film 207 are sequentially removed so that a predetermined portion of the source / drain region of the polysilicon layer 206 implanted with the n + ion is exposed. After the formation, the AlNd and Mo double metal films are formed to sufficiently fill the via holes, and then patterned to form the source electrode 210 and the drain electrode 211 of the thin film transistor.

Thereafter, as shown in FIG. 4F, the first protective layer 212 made of silicon nitride and the second protective layer 213 made of BCB (Benzocyclobutene) are sequentially stacked on the entire surface including the source / drain electrodes 210 and 211. Thereafter, a contact hole is formed to expose the drain electrode 211.

Thereafter, a transparent conductive film such as indium tin oxide (ITO) is formed on the entire surface of the substrate including the contact hole, and then patterned to form a pixel electrode 214 electrically connected to the drain electrode 211 through the contact hole. .

Subsequently, although not shown in the drawings, a liquid crystal layer is formed between the first substrate 201a and the second substrate opposite to the manufacturing process of the liquid crystal display device according to the present invention.

Here, a color filter layer for expressing color is formed on the second substrate, and a black matrix pattern is formed to prevent light from being transmitted to the thin film transistor, the gate line, and the data line formed on the first substrate 201a. The common electrode for applying an electrical signal to the liquid crystal layer is formed together with the pixel electrode 214.

As described above, the polycrystallization method of the present invention and a method of manufacturing a thin film transistor and a liquid crystal display device using the same have the following effects.

It is possible to control the amount of metal using the metal collecting layer, it is possible to provide the advantages of eliminating various problems due to the conventional unreacted metal and the appropriate amount of metal required for the crystallization reaction.

Claims (12)

Forming a buffer layer on the insulating substrate; Forming an amorphous silicon layer on the buffer layer; Forming a metal thin film layer on the amorphous silicon layer; Forming a metal collecting layer on the metal thin film layer; And applying an electric field to the metal thin film layer and simultaneously heat treating the substrate to crystallize the amorphous silicon layer into polycrystalline silicon. The polycrystallization method according to claim 1, wherein the deposition amount of the metal thin film layer is about 1 × 10 ¹⁸ (atomic number) / cm ³ in terms of the number of atoms per unit volume. The polycrystallization method according to claim 1, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The polycrystallization method of claim 1, wherein the metal collection layer is formed of amorphous silicon doped with phosphorus (P) ions or an n + amorphous silicon layer using SiH ₄ and PH ₃ gas. The method of claim 1, wherein crystallizing the amorphous silicon, The voltage applied to the metal thin film layer is about 10 to 500V / cm, the time to apply is about 15 to 300 minutes, the heat treatment temperature is in the range of 400 to 600 ℃ polycrystalline crystal method. Preparing a first substrate and a second substrate, Forming a buffer layer on the first substrate; Forming an amorphous silicon layer on the buffer layer; Forming a metal thin film layer on the amorphous silicon layer; Forming a metal collecting layer on the metal thin film layer; Applying an electric field to the metal thin film layer and simultaneously heat treating the substrate to crystallize the amorphous silicon layer; Crystallizing the amorphous silicon layer, and then forming an island-like semiconductor layer; Forming a gate insulating film on the entire surface including the semiconductor layer; Forming gate electrodes and gate lines at predetermined portions on the gate insulating film; Forming a source / drain region by doping ions in the semiconductor layer; Activating the semiconductor layer; Forming an interlayer insulating film on the semiconductor layer and the gate electrode, and then exposing a portion of the source / drain region; Forming source / drain electrodes and data lines to be connected to the exposed semiconductor layer; Forming a pixel electrode electrically connected to the drain electrode; And forming a liquid crystal layer between the first substrate and the second substrate. The method of claim 6, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The method of claim 6, wherein the deposition amount of the metal thin film layer is about 1 × 10 ¹⁸ (atomic number) / cm ³ in terms of the number of atoms per unit volume. The method of claim 6, wherein the step of crystallizing the amorphous silicon, And a voltage applied to the metal thin film layer is about 10 to 500 V / cm, an application time is about 15 to 300 minutes, and a heat treatment temperature is in a range of 400 to 600 ° C. The method of claim 6, wherein the source / drain electrodes are formed of a double layer of AlNd and Mo. The method of claim 6, wherein the metal collecting layer is formed of amorphous silicon doped with phosphorus (P) ions or an n + amorphous silicon layer using SiH ₄ and PH ₃ gases. The method of claim 6, Forming a silicon nitride film and a double insulating film of BCB on the entire surface including the source / drain electrodes; And partially connecting the pixel electrode to the pixel electrode by partially etching the double insulating layer to expose the drain electrode.