KR100525435B1 - Process for crystallizing amorphous silicon and its application - fabricating method of TFT-LCD - Google Patents

Abstract

The present invention relates to a polycrystallization method for neutralizing the electrical polarity of an unreacted metal present on a polycrystalline silicon layer after crystallization of amorphous silicon, and a method for manufacturing a thin film transistor and a liquid crystal display device using the same. Forming a buffer layer on an insulating substrate, forming an amorphous silicon layer on the buffer layer, forming a metal thin film layer on the amorphous silicon layer, and forming electrodes on left and right predetermined regions on the metal thin film layer And crystallizing the amorphous silicon layer into a polycrystalline silicon layer by applying an electric field to the electrode and heat treating the substrate; forming a gate insulating film on the entire surface of the substrate including the polycrystalline silicon layer; Dopants are implanted into regions corresponding to the polycrystalline silicon layer on the It characterized in that comprises the system.

Description

Polycrystallization method and manufacturing method of liquid crystal display using the same {Process for crystallizing amorphous silicon and its application-fabricating method of TFT-LCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a polycrystalline silicon thin film transistor, and more particularly, to a polycrystallization method using an electric field applied metal induction crystallization method and a liquid crystal display device manufacturing method using the same.

Although TFT-LCDs have high density and large area, and display and driving circuits are fabricated on the same substrate, there is an urgent need for increasing mobility of thin film transistors, which are switching elements. It is difficult to satisfy this advantage with a thin film transistor (a-Si: H TFT).

Recently, polycrystalline silicon TFTs (Poly-Si TFTs) have attracted much attention as a method for effectively solving these problems. Since polycrystalline silicon TFTs have high mobility, they have the advantage of allowing peripheral circuits to be integrated on glass substrates, thus attracting much attention in terms of reducing production costs.

In addition, polycrystalline silicon TFTs have higher mobility than amorphous silicon TFTs, and are advantageous as switching elements of high-resolution panels, and are suitable for projection panels in which a lot of light is emitted due to less photocurrent compared to amorphous silicon TFTs.

There have been many reports on the method of fabricating polycrystalline silicon, and there are largely a method of directly depositing polycrystalline silicon and a method of forming polycrystalline silicon by depositing amorphous silicon and then crystallizing.

The former methods include Low Pressure Chemical Vapor Deposition (LPCVD) and Plasma Enhanced Chemical Vapor Deposition (PECVD). Among them, the LPCVD method has a substrate temperature of 550 ° C. or higher. Due to the use of expensive silica or quartz, the manufacturing cost is high and not suitable for mass production. In the case of PECVD, the SiF ₄ / SiH ₄ / H ₂ mixed gas can be deposited at 400 ° C. or lower, but it is difficult to suppress the grains. It is known to have serious problems.

The latter method, that is, a method of depositing and crystallizing amorphous silicon includes a solid phase crystallization (SPC) method and an excimer laser annealing (ELA) method.

The ELA method is a method of crystallizing a thin film in an instant by administering an excimer laser having a strong energy in an amorphous silicon thin film to form a polycrystalline silicon thin film having a large crystal grain size and excellent crystallinity. This is possible. However, the ELA method requires an expensive accessory equipment, such as an excimer laser, and thus can be said to have a limitation in mass production and large area LCD driving TFTs.

Solid phase crystallization is mainly a method of crystallizing an amorphous silicon thin film by using a furnace heating method in a furnace. Likewise, polycrystalline silicon thin film having excellent crystallinity can be produced, but is crystallized because it proceeds by solid phase reaction. The reaction rate is slow and requires a long crystallization time of several tens of hours or more at a high temperature of 600 ° C or higher.

In addition to the above methods, a lot of research has recently been conducted to lower the crystallization temperature in order to use polycrystalline silicon in the manufacture of large-area liquid crystal display devices, one of which is a metal induced crystallization method and furthermore, Electric field enhanced metal induced crystallization (ESD), which applies an electric field to induction crystallization and improves the rate of crystallization, is also being studied.

According to these methods, when a specific type of metal is contacted with amorphous silicon, the crystallization temperature of the amorphous silicon can be lowered to 500 ° C. or lower, and the metal induction crystallization effect is known to occur in various kinds of metals.

Metal-induced crystallization differs in causing crystallization depending on the type of metal. That is, the crystallization phenomenon may vary depending on the type of metal in contact with the hydrogenated amorphous silicon (a-Si: H).

For example, metals such as aluminum (Al), gold (Au), and silver (Ag) are governed by the diffusion of silicon (Si) at the interface with amorphous silicon. That is, at the interface between metal and silicon, a metastable silicide phase is formed by diffusion of silicon, and the silicide lowers the crystallization energy to promote crystallization of silicon.

In contrast, in metals such as nickel (Ni) and titanium (Ti), diffusion of metals by annealing is dominant. That is, a silicide phase is formed by metal diffusion from the metal and silicon interface in the direction of the silicon layer, and the silicide promotes crystallization and lowers the crystallization temperature.

Hereinafter, a polycrystallization method according to the prior art will be described with reference to the accompanying drawings.

1A to 1C are cross-sectional views illustrating a method of crystallizing an amorphous silicon thin film according to the prior art.

As shown in FIG. 1A, a buffer layer 102 is formed of a silicon oxide film (SiO ₂ ) on an insulating substrate 101, an amorphous silicon 103 is deposited on the buffer layer, and then a metal thin film layer serving as a crystallization catalyst. 104 is formed in the amorphous silicon layer. Here, nickel (Ni) or the like is used as the metal thin film layer 104.

As shown in Fig. 1B, an electrode 105 for applying an electric field to the metal thin film layer is added. Molybdenum (Mo) is used as the material for the electrode.

Subsequently, a predetermined electric field is applied to the electrode 105, and at the same time, a heat treatment is performed. As shown in FIG. 1C, as a result of the crystallization of FIG. As a result, a silicide phase (NiSi ₂ ) is formed. The silicide (NiSi ₂ ) promotes crystallization of the silicon thin film to crystallize the amorphous silicon thin film into the polycrystalline silicon thin film 106 in a state where the crystallization temperature is lowered.

However, the conventional polycrystallization method as described above has the following problems.

After crystallization of amorphous silicon to polycrystalline silicon, unreacted metal 104a (see FIG. 1C) remains on the polycrystalline silicon layer, causing leakage of current through the channel layer, thereby causing serious problems in the characteristics of the thin film transistor. Cause it to occur.

The polycrystallization method according to the present invention has been made to solve the above problems, and an object thereof is to provide a stable polycrystallization method by neutralizing the polarity of the metal remaining on the polycrystalline silicon layer.

Another object of the present invention is to provide a method for manufacturing a thin film transistor and a liquid crystal display using the polycrystallization method.

The polycrystallization method of the present invention for achieving the above object comprises the steps of forming a buffer layer on an insulating substrate, forming an amorphous silicon layer on the buffer layer, forming a metal thin film layer on the amorphous silicon layer; Forming an electrode in a predetermined left and right region on the metal thin film layer, applying an electric field to the electrode, and heat treating a substrate to crystallize the amorphous silicon layer, and crystallizing the amorphous silicon layer, followed by island shape. Forming a semiconductor layer, forming a gate insulating film on the entire surface of the substrate including the semiconductor layer, and implanting a dopant into a region corresponding to the polycrystalline silicon layer on the gate insulating film. .

The method of manufacturing a thin film transistor using the polycrystallization method as described above includes forming a buffer layer on an insulating substrate, forming an amorphous silicon layer on the buffer layer, and forming a metal thin film layer on the amorphous silicon. Forming an electrode in a predetermined left and right region on the metal thin film layer; applying an electric field to the electrode; and heat treating a substrate to crystallize the amorphous silicon layer; and crystallizing the amorphous silicon layer. Forming a semiconductor layer, forming a gate insulating film on the entire surface including the semiconductor layer, injecting a dopant into a region corresponding to the semiconductor layer on the gate insulating film, and Forming a gate electrode and not overlapping the gate electrode in the semiconductor layer Forming a source / drain region by ion doping an inverse, activating the semiconductor layer, and forming an interlayer insulating film on the semiconductor layer and the gate electrode, and then exposing a portion of the source / drain region And forming a source electrode and a drain electrode to be connected to the exposed source / drain region.

In addition, the method of manufacturing a liquid crystal display device using the thin film transistor as described above may include preparing a first substrate and a second substrate, forming a buffer layer on the first substrate, and forming an amorphous silicon layer on the buffer layer. Forming a metal thin film layer on the amorphous silicon layer, forming an electrode in predetermined left and right regions on the metal thin film layer, applying an electric field to the electrode, and simultaneously heat-treating the substrate to heat the amorphous silicon layer. Crystallizing, forming an island-like semiconductor layer after crystallizing the amorphous silicon layer, forming a gate insulating film on the entire surface including the semiconductor layer, and forming a polycrystalline silicon layer on the gate insulating film. Implanting a dopant in a region of the insulating film; Forming a source / drain region by doping a region not overlapping with the gate electrode in the semiconductor layer, activating the semiconductor layer, and a first insulating film on the semiconductor layer and the gate electrode Forming a source / drain region, forming a source / drain electrode and data lines to be connected to the exposed source / drain region, and a pixel electrode electrically connected to the drain electrode. And forming a liquid crystal layer between the first substrate and the second substrate.

Hereinafter, a polycrystallization method and a method of manufacturing a thin film transistor using the same according to the present invention will be described with reference to the drawings.

2A through 2D are cross-sectional views illustrating a polycrystallization method according to the present invention, and FIGS. 3A through 3G are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

As shown in FIG. 2A, after forming the silicon oxide film buffer layer 202 on the insulating substrate 201, plasma chemical vapor deposition of SiH ₄ and H ₄ mixed gas on the buffer layer 202 is performed. The amorphous silicon (a-Si: H) layer 203 is formed using a chemical vapor deposition method.

As shown in FIG. 2B, a metal thin film layer 204 is formed on the amorphous silicon layer 203 by sputtering. In this case, as the metal thin film layer 204, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt), or the like is used, and the deposition thickness in order not to adversely affect the operation characteristics of the device after completion of the device. Is limited to trace amounts of 1.25 to 100 Å.

Next, an electrode 205 for applying an electric field to left and right predetermined regions on the metal thin film layer 204 is added. Molybdenum (Mo), graphite (Graphite) and the like are used as the material for the electrode 205.

The amorphous silicon layer is crystallized by applying an electric field having a predetermined condition to the electrode 205 and simultaneously heat-treating the substrate. At this time, the applied voltage is 30 to 100 V / cm, the application time is 15 minutes to 2 hours, and the heat treatment temperature of the substrate is about 300 to 580 ° C.

As shown in FIG. 2C, the amorphous silicon layer is crystallized into the polycrystalline silicon layer 206 by the crystallization process of FIG. 2B. The crystallization process is as follows.

The metal thin film layer is solid phase diffused to an amorphous silicon layer to form metal silicide. For example, nickel (Ni) forms nickel silicide (NiSi ₂ ). At this time, since the hydrogen component of the amorphous silicon is removed, the reaction between the metal and the amorphous silicon can be maximized.

The metal silicide acts as a catalyst for crystallization of amorphous silicon, that is, a crystallization nucleus, and uniform crystallization of amorphous silicon proceeds at a high crystallization rate due to the crystallization nucleus.

At this time, the portion 204a of the metal thin film layer does not react with amorphous silicon and remains in a metal state, and these metals serve to cause a fatal leakage current in the thin film transistor device in the future.

As shown in FIG. 2D, a gate insulating film made of silicon oxide (SiO ₂ ) is formed on the entire surface of the substrate including the polycrystalline silicon layer. An n- or p-type dopant is implanted over the gate insulating layer to neutralize the polarity of the unreacted metal 204a on the polycrystalline silicon.

At this time, the dopant implanted according to the electrical polarity of the unreacted metal 204a is applied differently. The dopant is phosphorus (P, Phosphorus) is applied in the case of the n-type, boron (B, Boron) is used as the p-type dopant.

Since the implantation amount of the dopant is about 10 ¹² dose / cm ² , it does not significantly affect the n + ion doping performed after the formation of the gate electrode on the gate insulating layer in the future. For reference, the n + ion doping amount is about 10 ¹⁵ dose / cm ² .

Referring to the thin film transistor manufacturing process using the polycrystallization method as follows.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor using a polycrystallization method according to the present invention.

First, as shown in FIG. 3A, the buffer layer 202 and the amorphous silicon layer (a-Si: H) 203 made of silicon oxide (SiO ₂ ) material are formed on the insulating substrate 201 by chemical vapor deposition. Laminate sequentially. Here, the buffer layer 202 is to prevent the impurity component of the insulating substrate 201 to diffuse into the amorphous silicon layer 203, the amorphous silicon layer 203 is plasma using SiH ₄ and H ₂ mixed gas It is formed by chemical vapor deposition (PECVD).

As shown in FIG. 3B, a metal thin film layer 204 is formed on the amorphous silicon layer 203 by sputtering. In this case, as the metal thin film layer 204, chromium (Cr), palladium (Pd), nickel (Ni), platinum (Pt), and the like are used, and in order not to adversely affect the operation characteristics of the device after the completion of the deposition thickness is It is limited to the trace amount of 1.25 ~ 100Å.

Subsequently, an electrode 205 for applying an electric field to left and right predetermined regions on the metal thin film layer 204 is added. In this case, as the material of the electrode 205, molybdenum (Mo), graphite, or the like is used.

Thereafter, an electric field having a predetermined condition is applied to the electrode 205 and the substrate is heat-treated at the same time to crystallize the amorphous silicon layer 203. At this time, the voltage applied to the electrode 205 is 30 to 100V / cm, the application time is about 15 minutes to 2 hours, and the heat treatment temperature is preferably set to 300 to 580 ℃.

After the crystallization of the amorphous silicon layer 203 into the polycrystalline silicon layer 206 through the above process, as shown in FIG. 3C, the polycrystalline silicon layer 206 is patterned into an island shape, and then the polycrystalline silicon layer is formed. A gate insulating film 207 made of silicon oxide film or silicon nitride film is formed on the entire surface of the substrate including 206 by chemical vapor deposition.

On the other hand, the unreacted metal 204a, which failed to react with amorphous silicon, remains on the polycrystalline silicon layer 206 formed by the polycrystallization method, and this unreacted metal will seriously affect the device characteristics of the thin film transistor in the future. This requires processing.

That is, an n- or p-type dopant is implanted onto the gate insulating layer 207 to neutralize the polarity of the unreacted metal 204a on the polycrystalline silicon layer.

Subsequently, as shown in FIG. 3D, a double metal layer of AlNd and Mo is sequentially stacked on the gate insulating film 207 by sputtering, and then patterned to form a gate electrode 208 having a double film structure. .

Subsequently, a source / drain region is formed by implanting n + ions into the polycrystalline silicon layer 206 on both sides of the gate electrode 208 through an ion implantation process using the gate electrode 208 as a mask and having a temperature lower than the crystallization temperature. After activation, the interlayer insulating film 209 is formed on the entire surface of the substrate including the gate electrode 208.

As shown in FIG. 3E, a via hole is formed by etching the interlayer insulating layer 209 and the gate insulating layer 207 so that a predetermined region of the n + ion-doped polycrystalline silicon layer 206 is exposed. After stacking AlNd and Mo double metal layers in order to sufficiently fill the via holes, and patterning the source / drain electrodes 210 and 211 to form the thin film transistor manufacturing process using the polycrystallization method according to the present invention, the process is completed. do.

Hereinafter, a method of manufacturing a liquid crystal display using the above-described thin film transistor manufacturing process will be described.

4A to 4F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device according to the present invention.

As shown in FIG. 4A, after forming the buffer layer 202 made of silicon oxide film on the first substrate 201a, the plasma chemical vapor deposition method using SiH ₄ and H ₄ mixed gas is performed on the buffer layer 202. An amorphous silicon layer 203 is formed.

Thereafter, as shown in FIG. 4B, the amorphous silicon layer 203 is crystallized through the aforementioned crystallization process, and then, as shown in FIG. 4C, the amorphous silicon layer 203 may be used as a channel layer of a thin film transistor. Pattern it into island shapes so that it Thereafter, after forming the gate insulating film 207 of silicon nitride film or silicon oxide film on the entire surface including the island-shaped polycrystalline silicon layer 206, the electrical polarity of the unreacted metal remaining on the polycrystalline silicon layer 206 Is neutralized by injection of an n- or p-type dopant.

Subsequently, a double metal layer of AlNd and Mo is stacked on the gate insulating layer, and then patterned to form a gate electrode 208 and a gate line (not shown) of the thin film transistor.

Thereafter, as shown in FIG. 4D, n + ions are implanted into the polycrystalline silicon layer 206 using the gate electrode 208 as a mask to form and activate a source / drain region, and then the gate electrode 208 and An interlayer insulating film 209 is formed on the entire surface including the gate line.

Subsequently, as shown in FIG. 4E, the interlayer insulating film 209 and the gate insulating film 207 are sequentially removed so that a predetermined portion of the source / drain region of the polysilicon layer 206 implanted with the n + ion is exposed. After the formation, the AlNd and Mo double metal films are formed to sufficiently fill the via holes, and then patterned to form the source electrode 210 and the drain electrode 211 of the thin film transistor.

Thereafter, as shown in FIG. 4F, the first passivation layer 212 made of silicon nitride and the second passivation layer 213 made of benzocyclobutene (BCB) are sequentially stacked on the entire surface including the source / drain electrodes 210 and 211. After that, a contact hole is formed to expose the drain electrode 211.

Thereafter, a transparent conductive film such as indium tin oxide (ITO) is formed on the entire surface of the substrate including the contact hole, and then patterned to form a pixel electrode 214 electrically connected to the drain electrode 211 through the contact hole. .

Subsequently, although not shown in the drawings, a liquid crystal layer is formed between the first substrate 201a and the second substrate opposite to the manufacturing process of the liquid crystal display device according to the present invention.

Here, a color filter layer for expressing color is formed on the second substrate, and a black matrix pattern is formed to prevent light from being transmitted to the thin film transistor, the gate line, and the data line formed on the first substrate 201a. The common electrode for applying an electrical signal to the liquid crystal layer is formed together with the pixel electrode 214.

As described above, the method of manufacturing the polycrystalline silicon thin film transistor of the present invention has the following effects.

After crystallization of amorphous silicon, a stable thin film transistor device can be provided by neutralizing the polarity of the unreacted metal remaining on the polycrystalline silicon layer.

1A to 1C are cross-sectional views illustrating a method of crystallizing amorphous silicon according to the prior art.

Figures 2a to 2d is a cross-sectional view for explaining the electric field applied metal crystallization method according to the present invention.

3A to 3E are cross-sectional views illustrating a method of manufacturing a thin film transistor using the polycrystallization method of the present invention.

4A to 4F are cross-sectional views illustrating a method of manufacturing a liquid crystal display device using the polycrystallization method of the present invention.

Explanation of symbols for the main parts of the drawings

201: insulating substrate 202: buffer layer

204a: unreacted metal 206: polycrystalline silicon layer

207: gate insulating film

Claims (16)

Forming a buffer layer on the insulating substrate; Forming an amorphous silicon layer on the buffer layer; Forming a metal thin film layer on the amorphous silicon layer; Forming electrodes in left and right predetermined regions on the metal thin film layer; Crystallizing the amorphous silicon layer by applying an electric field to the electrode and heat treating the substrate; Crystallizing the amorphous silicon layer, and then forming an island-like semiconductor layer; Forming a gate insulating film on an entire surface of the substrate including the semiconductor layer; And injecting a dopant into the entire surface of the semiconductor layer. The polycrystallization method according to claim 1, wherein the metal thin film layer has a thickness of about 1.25 to about 100 GPa. The polycrystallization method according to claim 1, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The method of claim 1, wherein the electrode is formed of molybdenum (Mo) or graphite (Graphite). The method of claim 1, wherein crystallizing the amorphous silicon, The voltage applied to the electrode is 30 to 100V / cm, the time to apply is 15 minutes to 2 hours, the heat treatment temperature is in the range of 300 to 580 ℃ characterized in that the polycrystallization method. The polycrystallization method according to claim 1, wherein the dopant injects n- or p-type dopants, respectively, according to the electrical polarity of the unreacted metal remaining on the polycrystalline silicon layer. 7. The method of claim 6 wherein said n-type dopant is phosphorus (P) and said p-type dopant is boron (B). Preparing a first substrate and a second substrate, Forming a buffer layer on the first substrate; Forming an amorphous silicon layer on the buffer layer; Forming a metal thin film layer on the amorphous silicon layer; Forming electrodes in left and right predetermined regions on the metal thin film layer; Crystallizing the amorphous silicon layer by applying an electric field to the electrode and heat treating the substrate; Crystallizing the amorphous silicon layer, and then forming an island-like semiconductor layer; Forming a gate insulating film on the entire surface including the semiconductor layer; Implanting a dopant into a region corresponding to the semiconductor layer on the gate insulating film; Forming gate electrodes and gate lines at predetermined portions on the gate insulating film; Forming a source / drain region by doping ions in the semiconductor layer; Activating the semiconductor layer; Forming an interlayer insulating film on the semiconductor layer and the gate electrode, and then exposing a portion of the source / drain region; Forming source / drain electrodes and data lines to be connected to the exposed semiconductor layer; Forming a pixel electrode electrically connected to the drain electrode; And forming a liquid crystal layer between the first substrate and the second substrate. The method of claim 8, wherein the metal thin film layer has a thickness of about 1.25 to about 100 microns. The method of claim 8, wherein the metal thin film layer is formed of any one of chromium (Cr), palladium (Pd), nickel (Ni), and platinum (Pt). The method of claim 8, wherein the electrode is formed of one of molybdenum (Mo) and graphite. The method of claim 8, wherein the crystallization of the amorphous silicon is characterized in that the voltage applied to the electrode is 30-100V / cm, the application time is 15 minutes to 2 hours, the heat treatment temperature is in the range of 300 to 580 ℃. Liquid crystal display device manufacturing method. 9. The method of claim 8, wherein the dopant injects n- or p-type dopants, respectively, according to the electrical polarity of the unreacted metal remaining on the polycrystalline silicon layer. The method of claim 13, wherein the n-type dopant is phosphorus (P), and the p-type dopant is boron (B). 10. The method of claim 8, wherein the source / drain electrodes are formed of a double layer of AlNd and Mo. The method of claim 8, Forming a silicon nitride film and a double insulating film of BCB on the entire surface including the source / drain electrodes; And partially connecting the pixel electrode to the pixel electrode by partially etching the double insulating layer to expose the drain electrode.