KR20050024947A - Thin film transistor array panel and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A TFT(Thin Film Transistor) substrate and a method for manufacturing the same are provided to prevent contact defect of wiring due to step difference at a connection part connected to an outside driving circuit, thereby enhancing contact reliability of the connection part during connecting the outside driving circuit to the connection part, by forming a passivation layer to have a taper configuration at the connection part such that the boundaries of the passivation layer have smooth inclination angles. CONSTITUTION: A TFT substrate comprises a plurality of signal lines, a plurality of TFTs electrically connected to the signal lines, a passivation layer(180) covering the signal lines and the TFTs, and a plurality of pixel electrodes formed on the passivation layer and electrically connected to the TFTs. A connection part is formed at a peripheral region of the TFT substrate for mounting an outside driving circuit, wherein the outside driving circuit is connected to the TFT substrate through the connection part. The passivation layer has a taper configuration at the connection part. The passivation layer has the first region(184) having a connection hole(182) for exposing a data line(179), the second region(188) thicker than the first region, and the third region(186) between the first region and the second region. The third region slopes to have a smooth inclination angles ranging 5 to 10 degree angles.

Description

Thin film transistor array panel and method for manufacturing the same {Thin film transistor array panel and method for manufacturing the same}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array panel and a method of manufacturing the same, and more particularly, to a thin film transistor array panel having a contact portion for connecting to a driving circuit at an end portion of a signal line and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two substrates on which electrodes are formed and a liquid crystal layer interposed therebetween, and rearranges the liquid crystal molecules of the liquid crystal layer by applying a voltage to the electrode. By controlling the amount of light transmitted.

Among the liquid crystal display devices, a liquid crystal display device having a thin film transistor for forming an electrode on each of two substrates and switching a voltage applied to the electrode is generally used. The thin film transistor is generally formed on one of two substrates.

In order to improve the display characteristics of such a liquid crystal display device, it is desirable to secure the aperture ratio of the pixel. To this end, the pixel electrode is extended to the maximum to overlap the gate line and the data line, and an insulating film made of an organic material having a low dielectric constant having a thickness of about 3 μm is disposed therebetween in order to minimize interference of signals transmitted through the wiring. Form thickly.

However, in the case of applying such a thick organic film, the step of the organic film is severely generated at the contact portion of the signal line for connecting with the output terminal of the external driving circuit. That is, the contact portion exposes a part of the signal line by removing the organic layer, but the contact hole in which the organic layer exposes the signal line in proportion to the thickness has a severe step. This causes a poor contact when the drive integrated circuit is electrically connected to the signal line using an anisotropic conductive film containing conductive particles, thereby acting as a cause of lowering the contact reliability.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same that can ensure contact reliability between a signal line and a driving integrated circuit.

In the thin film transistor array panel according to the exemplary embodiment of the present invention and the manufacturing method thereof, the protective layer has a thinner thickness than the other portion at the upper portion of the contact portion, which is the end of the signal line. At this time, in the portion where the thickness of the protective film becomes thin, the protective film has a tapered structure having a gentle inclination angle of 45 ° or less with respect to the substrate surface.

More specifically, in the thin film transistor array panel according to the exemplary embodiment of the present invention, a plurality of signal lines and thin film transistors connected to the signal lines are formed. A protective film is formed on the signal line and the thin film transistor, and a pixel electrode connected to the thin film transistor is formed thereon. At this time, each signal line has a contact portion for connecting to the outside, the protective film has a thickness thinner than the other portion on the contact portion, the protective film has a tapered structure having an inclination angle in the range of 5-10 ° in the thinning portion.

At this time, the width of the thinning portion of the protective film is preferably in the range of 10-40㎛.

The edge of the pixel electrode overlaps the signal line with the passivation layer interposed therebetween, and the passivation layer is preferably made of an organic insulating material.

The protective film has a contact hole for exposing the contact portion, and is made of the same layer as the pixel electrode, and further includes a contact member connected to the contact portion through the contact hole, and the contact hole preferably exposes the boundary of the contact portion.

The signal line includes a gate line and a data line crossing each other, and the thin film transistor includes a gate electrode that is part of the gate line, a source electrode that is part of the data line, a drain electrode connected to the pixel electrode, and a semiconductor disposed between the gate electrode and the source electrode and the drain electrode. Include.

The semiconductor may extend along the data line, and the semiconductor except for the source electrode and the drain electrode may have the same planar pattern as the data line and the drain electrode.

The pixel electrode is made of IZO or ITO.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, first, a gate line having a gate electrode is formed on a substrate, and a gate insulating film is stacked on the substrate. Next, a semiconductor layer is formed over the gate insulating film, and a data line and a drain electrode having a source electrode in contact with the semiconductor layer are formed. Subsequently, a first portion covering the semiconductor layer and having a contact hole exposing a contact portion of a gate line or a data line for connection to the outside, a second portion thicker than the first couple, and positioned between the first portion and the second portion A protective film including a third portion having a tapered structure having an inclination angle of 5-10 ° or less is formed, and then a pixel electrode connected to the drain electrode is formed.

In this case, the passivation layer is formed by a photolithography process using a mask, the mask corresponding to the first portion and the third portion, a first region transmitting only a part of the light, a second region corresponding to the contact hole and transmitting most of the light, And a third region corresponding to the third portion and blocking most of the light.

It is preferable that a slit or grating pattern is formed in the first region of the mask, and the width or spacing of the slit or grating pattern of the first region gradually increases or decreases closer to the third region.

It is preferable that the width of the slit of the first region corresponding to the first portion is constant, and the width of the light shielding pattern defining the slit of the first region corresponding to the third portion gradually increases closer to the third region.

The protective film is formed of an organic insulating material, and the pixel electrode is preferably formed of IZO or ITO.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A method of manufacturing a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention. FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along a line II-II ′. 3 is an enlarged plan view illustrating a structure of a connection unit to which an external driving integrated circuit is connected in a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 4 is a view illustrating a connection portion of FIG. 3 taken along line IV-IV ′. It is a cross section.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line protrudes downward to form a plurality of expansions 127.

The gate line 121 includes two layers having different physical properties, that is, a lower layer 211 and an upper layer 212 thereon. The upper layer 212 is formed of a metal having a low resistivity, for example, aluminum-based metal such as aluminum (Al) or an aluminum alloy, so as to reduce delay or voltage drop of the gate signal. In contrast, the lower layer 211 is a material having excellent physical, chemical and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys [eg, molybdenum alloys]. -Tungsten (MoW) alloy], chromium (Cr) and the like. An example of the combination of the lower layer 211 and the upper layer 212 may be a chromium / aluminum-neodymium (Nd) alloy. In FIG. 1, lower and upper layers of the gate electrode 124 are denoted by reference numerals 241 and 242, respectively, and lower and upper layers of the expansion unit 127 are denoted by reference numerals 271 and 272, respectively.

Side surfaces of the lower layer 211 and the upper layer 212 are inclined, respectively, and the inclination angle thereof is about 30 to 80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitors are disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively. conductor 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 123. The gate electrode 123, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the storage capacitor conductor 177 include molybdenum (Mo) and molybdenum alloy, and may include an aluminum-based conductive film in the case of a double layer or triple layer. . In the case of the double film, the aluminum-based conductive film is preferably positioned below the molybdenum-based conductive film, and in the case of the triple film, the aluminum-based conductive film is preferably positioned as an intermediate layer.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion that meets the gate line 121 to strengthen the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed portion of the semiconductor 151, an organic material or plasma chemical vapor deposition having excellent planarization characteristics and photosensitivity. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by enhanced chemical vapor deposition (PECVD) is formed.

In order to prevent the organic material of the passivation layer 180 from coming into contact with the exposed portion of the semiconductor 151 between the data line 171 and the drain electrode 175, the passivation layer 180 is formed of silicon nitride or silicon oxide under the organic layer. An insulating film can be added.

The passivation layer 180 includes a plurality of contact holes 185, 187, and 182 that respectively expose the drain electrode 175, the storage capacitor conductor 177, and the end portion 179 of the data line 171. Formed. As described above, the embodiment in which the passivation layer 180 has a contact hole 182 exposing the end portion 179 of the data line 171 connects an external data driving circuit to the data line 171 using an anisotropic conductive layer. For example, the data line 171 has a contact portion, and the end portions 179 of the data line 171 are clustered as shown in FIG. 3 in the connection portion 400 (see FIG. 3) to which the data driving circuit is connected. The end portion 179 of the data line 171 may have a wider width than the data line 171 as necessary.

On the other hand, the end portion of the gate line 121 may have a contact portion like the end portion of the data line. In this embodiment, the passivation layer 180 together with the gate insulating layer 140 may expose a plurality of end portions of the gate line 121. Has a contact hole. Alternatively, a gate driving circuit may be directly formed on the substrate 110, and in this embodiment, an end portion of the gate line 121 is connected to an output terminal of the gate driving circuit.

The contact holes 185, 187, and 182 expose the drain electrode 175, the conductor 177 for the storage capacitor, and the end portion 179 of the data line 171. The contact holes 181, 185, 187, and 182 are exposed. In order to secure contact characteristics with the conductive film formed afterwards, the aluminum-based conductive film is preferably not exposed, and when exposed, the aluminum-based conductive film is preferably removed through full etching. In this case, the boundary line of the end portion 179 of the data line 171 is exposed in the contact hole 182 exposing the end portion 179 of the data line, and the conductive contact for the drain electrode 175 and the storage capacitor is also present in the contact holes 187 and 185. The boundary of the sieve 177 may be revealed.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the drain electrode 175, and to connect the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off, thereby enhancing the voltage holding capability. In order to achieve this, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a "storage electrode". The storage capacitor is made by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitance. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 82 are connected to the end portions 179 of the data lines through the contact holes 182, respectively. The contact auxiliary member 82 is not essential to serve to protect and protect adhesiveness between each end portion 179 of the data line 171 and an external device such as a driving integrated circuit, and whether or not to apply them. Is optional. Of course, the end portion of the gate line 121 is also connected to the contact auxiliary member through the contact hole of the protective film like the end portion of the data line.

3 and 4, a contact portion, which is an end portion 179 of the data line 171, is connected to the connection portion 400 for connecting the data driving circuit using an anisotropic conductive film containing conductive particles from the outside. In an exemplary embodiment, the passivation layer 184 on the end portion 179 of the data line 171 has a thickness thinner than that of the other portion 188 including the pixel area. Therefore, in the connection part 400, when the data driving circuit is connected using an anisotropic conductive film containing conductive particles because the step difference due to the passivation layer 180 is small, it is possible to prevent the lifting phenomenon and the like, thereby ensuring contact reliability at the connection part. Can be. In this case, the protective layer 184 in the connection portion 400 preferably has a thickness of about 4,000-6,000 kPa.

In addition, the peripheral boundary of the connector 400, the portion 186 gradually thinner as the thickness of the passivation layer 180 is closer to the connector 400 has a tapered structure, which forms a circumferential boundary of the connector 400 and is inclined ( The inclination angle θ of S) is 45 ° or less with respect to the surface of the substrate 110, preferably 5-10 °. This is because when the inclination angle of the thinning part 186 which is the boundary of the connection part 400 in the manufacturing process is abrupt, ITO or IZO remains at the boundary of the connection part 400 when the contact auxiliary member 82 is formed, thereby contacting the drive circuit. Defect occurs. In the exemplary embodiment of the present invention, the inclined surface S of the portion 186 where the thickness of the passivation layer 180 becomes thin is formed at an inclination angle θ in the range of 5-10 ° with respect to the surface of the substrate 110 so that the ITO at the connection portion 400 is formed. It is possible to prevent the film or the IZO film from remaining to prevent a bad contact in the connection portion 400. At this time, the width D of the thinning portion 186 is preferably in the range of 10-40 μm.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 to 4 will be described in detail with reference to FIGS. 5 to 13 and FIGS. 1 and 4.

5, 7, 9, and 11 are layout views of the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 4 according to an embodiment of the present invention. 6, 8, 10, and 12 show the thin film transistor array panels shown in FIGS. 5, 7, 7, 9, and 11, respectively, in the VIb-VIb 'line, the VIIIb-VIIIb' line, and the Xb-Xb 'line. FIG. 13 is a cross-sectional view taken along lines XIIb-XIIb ′, and FIG. 13 is a cross-sectional view illustrating a structure of a connection part in a manufacturing method according to an exemplary embodiment of the present invention.

First, two layers of a metal film, that is, a lower metal film and an upper metal film, are sequentially stacked on an insulating substrate 110 made of transparent glass, for example, by sputtering. The lower metal film is made of a metal having excellent contact properties with IZO or ITO, for example, molybdenum, molybdenum alloy or chromium, and preferably has a thickness of about 500 kPa. The upper metal film is made of an aluminum-based metal, and preferably has a thickness of about 2,500 Å.

5 and 6, a gate including a plurality of gate electrodes 124 and a plurality of extensions 127 by sequentially patterning the upper metal layer and the lower metal layer in a photolithography process using a photoresist pattern. A line 121 is formed.

The patterning of the top layer 212, which is an aluminum-based metal, is, for example, CH3COOH (8-15%) / HNO3 (5-8%) / H3PO4, an aluminum etchant that can be etched while laterally inclining both molybdenum and aluminum. 50-60%) / H 2 O (rest) with wet etching.

As shown in Figs. 7 and 8, a three-layer film of a gate insulating film 140, intrinsic amorphous silicon and an impurity amorphous silicon layer is successively laminated, and an impurity amorphous silicon layer and an intrinsic The amorphous silicon layer is photo-etched to form a linear intrinsic semiconductor 151 including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154, respectively. As the material of the gate insulating layer 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa.

Next, as shown in FIGS. 9 and 10, a conductive film including aluminum or an aluminum alloy or chromium or molybdenum or molybdenum alloy is laminated as a single film or a multilayer film, and a photosensitive film is formed thereon, and the conductive film is patterned using an etching mask. Thus, a plurality of data lines 171 each including a plurality of source electrodes 173, a plurality of drain electrodes 175, and a plurality of conductors 177 for storage capacitors are formed.

Subsequently, the photosensitive layer on the data line 171 and the drain electrode 175 is removed or left untouched, and is exposed without being covered by the data line 171, the drain electrode 175, and the storage capacitor conductor 177. By removing the portion of the impurity semiconductor 164, the plurality of linear ohmic contacts 161 and the plurality of island type ohmic contacts 165 each including a plurality of protrusions 163 are completed, while the intrinsic semiconductor 151 thereunder. ) To expose the part. In this case, when the exposed impurity semiconductor 164 is removed using the data line 171 and the drain electrode 175 as an etching mask, the molybdenum series constituting the data line 171 and the drain electrode 175 is removed. In order to prevent the conductive film from being damaged, the impurity semiconductor 164 is etched using CF ₄ + HCl gas.

Subsequently, in order to stabilize the surface of the portion of the intrinsic semiconductor 151, oxygen plasma is preferably followed.

Next, as shown in FIGS. 11 and 12, a protective film 180 is formed by applying an organic insulating material having photosensitivity, and dry etching is performed by a photo process to form a plurality of contact holes 185, 187, and 182. . The contact holes 182, 185, and 187 expose the contacts, which are the drain electrode 175, the conductor 177 for the storage capacitor, and the end portion 179 of the data line 171. In this case, when the end portion of the gate line 121 is exposed or another thin film made of the same layer as the gate line 121 is exposed, the gate insulating layer 140 is also patterned together.

After forming the contact holes 182, 185, and 187, when the conductive film including aluminum is exposed through the contact holes 182, 185, and 197, it is preferable to remove the exposed conductive film of aluminum through the entire surface etching of the aluminum. At this time, the conductive film of aluminum is etched to the lower portion of the passivation layer 180 to generate an undercut, thereby weakly inducing a profile of another thin film to be formed later. However, the data line 171 is provided through the contact hole 182 at the contact portion. By exposing the boundary of the end portion 179, at least a portion of the undercut may be prevented from occurring so that the profile of the later formed thin film may be well induced, thereby minimizing contact resistance of the contact portion.

On the other hand, in the connecting portion 400 (see FIGS. 3 and 4), as described above, the connecting portion in which the contact portion, which is the end portion 179 of the data line 171, is gathered to securely connect the driving circuit while ensuring the contact reliability of the connecting portion. The thickness of the protective film 184 of 400 is formed thinner than that of the other portion 188. Accordingly, the passivation layer 180 may be disposed on the end portion 179 of the data line 171 to form the connection portion 400, the second portion 188 thicker than the first portion 184, and A third portion 186 that is progressively thick from first portion 184 to second portion 188. For example, in order to form the passivation layer 180, a translucent area C1 as well as a transparent area B1 and a light blocking area A1 are provided in the exposure mask 500. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal mask having only a transparent region and a light shielding region and then reflowing so that the photoresist film flows into an area where no photoresist remains.

In this case, as shown in FIG. 13, in order to form the third portion 186 of the passivation layer 180 positioned at the boundary of the connecting portion 400 having a thin thickness in a tapered structure having a gentle inclined surface S, Adjacent to A1) gradually reduces the light transmittance of the translucent region C1. To this end, the distance between the slits 510 may be gradually narrowed closer to the light shielding area A1 formed in the translucent area C1 corresponding to the third part 186. The width or spacing of the light shielding pattern 520 defining the spacing or the slit 510 is adjusted to increase or decrease. In the exemplary embodiment of the present invention, a mask having a 1.3 μm width and a gap between the light blocking patterns 520 of the slit 510 disposed in the translucent region C1 corresponding to the first portion 184, which is the connecting portion 400, is used. It was. In this case, in the translucent region C1 corresponding to the third portion 186, the width of the slit 510 is constant at 1.3 μm, and the light shielding pattern 520 is 1.3 μm, 1.8 μm, closer to the light blocking region A1. It has a width of 2.3 占 퐉 and is arranged four by one. As a result of forming the third portion of the passivation layer 180 using the mask 500, the third portion 186 may be formed in a tapered structure having an inclination angle θ in a range of 5-6 °.

Next, as shown in FIG. 1 and finally, the IZO or ITO film is laminated by sputtering and patterned by a photolithography process using a photoresist pattern to form a plurality of pixel electrodes 190 and a plurality of contact assistants 82. . At this time, in the photolithography process, a photosensitive film is coated on the IZO film or the ITO film and exposed to light to form a photosensitive film pattern, and then the IZO film or the ITO film is etched using the mask as a mask. In this case, when the boundary of the connection part has a steep inclined surface, the photoresist film is formed thicker than other parts at the boundary of the connection part because of the step difference. Will remain. Thus, the remaining photosensitive film leaves the IZO film or ITO film at the boundary of the connection portion. The remaining conductive film causes a short circuit between adjacent signal lines when the driving circuit is connected to the connection portion using the anisotropic conductive film. In the exemplary embodiment of the present invention, the inclined surface S of the connection part 400 is gently formed to prevent the photoresist film from being thickly applied at the boundary of the connection part, thereby preventing the conductive film of ITO or IZO from remaining. The short circuit can be prevented from occurring at the connecting portion, and the contact reliability of the connecting portion can be ensured.

On the other hand, in the photolithography process, since the photosensitive film is formed particularly thick at the corner portion of the boundary of the connection portion, it is preferable that the boundary of the connection portion 400 does not have an edge, and will be described in detail with reference to the drawings.

14A and 14B are plan views illustrating boundary lines of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

As shown in FIGS. 14A and 14B, in the thin film transistor array panel according to the exemplary embodiment of the present invention, the boundary of the connection portion 400 formed by the tapered structure at the connection portion 400 and formed on the inclined surface S has a chamfered shape or is smooth. It can be a fan shape.

In addition, although the embodiment of the present invention has been described above in the manufacturing method for forming the semiconductor layer and the data line by a photolithography process using different masks, the manufacturing method according to the present invention is used to minimize the manufacturing cost. The same applies to the method of manufacturing a thin film transistor array panel for a liquid crystal display device, in which the photo data line is formed by a photolithography process using one photosensitive film pattern. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 15, 16A, and 16B.

FIG. 15 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment, and the thin film transistor array panel illustrated in FIGS. 15A and 16B is along the XVIa-XVIa 'line and the XVIb-XVIb' line, respectively. It is sectional drawing cut out.

As shown in Figs. 15 to 16B, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices shown in Figs. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. On the ohmic contacts 161 and 165 and the gate insulating layer 140, a plurality of data lines 171 including a plurality of source electrodes 153, a plurality of drain electrodes 175, and a plurality of conductive capacitors 177. ) Is formed and a passivation layer 180 is formed thereon. A plurality of contact holes 182, 185, 187, and 181 are formed in the passivation layer 180 and / or the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members are formed on the passivation layer 180. 81 and 82 are formed.

However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the thin film transistor array panel according to the present embodiment is electrically connected to the gate line 121 on the same layer as the gate line 121 instead of having an extension portion on the gate line 121. A plurality of storage electrode lines 131 separated by the plurality of layers are overlapped with the drain electrode 175 to form a storage capacitor. The storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside, and the storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient. In order to maximize the aperture ratio of the pixel, the pixel may be disposed at an edge of the pixel area.

The semiconductor 151 has a planar shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. . In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165. ) Has an exposed portion between them.

In addition, the gate line 121 has a contact portion for connecting to the driving circuit at the end portion 129, and the end portion 129 of the gate line 121, which is a contact portion, is connected to the gate insulating layer 140 and the passivation layer 180. It is exposed through the contact hole 181 formed, and is connected with the contact auxiliary member 81 formed in the upper part of the protective film 180 through the contact hole 181.

Here, in the thin film transistor array panel for a liquid crystal display according to the second exemplary embodiment of the present invention, the structure of the connecting portion is the same as that of FIGS. 3 and 4, and is not shown in the drawings.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the present invention, the thickness of the passivation layer is thinly formed in the connection portion to which the driving circuit of the connection portion is connected, thereby preventing contact failure caused by the step in the connection portion. In addition, by forming the boundary of the connection portion in a tapered structure having a gentle inclination angle, the conductive film can be prevented from remaining, and a short circuit can be prevented from occurring when connecting the drive circuit, thereby ensuring contact reliability of the connection portion.

1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along the line II-II ',

3 is an enlarged plan view illustrating a structure of a connection unit to which an external driving integrated circuit is connected in a thin film transistor array panel according to an exemplary embodiment of the present invention.

4 is a cross-sectional view taken along the line IV-IV 'of the connection part of FIG. 3,

5, 7, 9, and 11 are layout views of the thin film transistor array panel at an intermediate stage of the method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 4 according to an embodiment of the present invention. Are listed,

6, 8, 10, and 12 show the thin film transistor array panels illustrated in FIGS. 5, 7, 7, 9, and 11, respectively, in the VIb-VIb 'line, the VIIIb-VIIIb' line, the Xb-Xb 'line, and the XIIb line. Is a cross section taken along the line XIIb ',

13 is a cross-sectional view showing the structure of the connecting portion in the manufacturing method according to an embodiment of the present invention,

14A and 14B are plan views illustrating boundary lines of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

15 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

16A and 16B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 15 taken along the lines XVIa-XVIa 'and XVIb-XVIb', respectively.

Claims (19)

Multiple signal lines, A thin film transistor connected to the signal line, A protective film formed on the signal line and the thin film transistor, A pixel electrode formed on the passivation layer and connected to the thin film transistor, Each of the signal lines has a contact portion for connecting to the outside, the passivation layer has a thickness thinner than other portions on the contact portion, and the passivation layer has a tapered structure having an inclination angle in a range of 5-10 ° at the thinning portion. . In claim 1, The thin film transistor array panel having a width of the thinning portion of the protective film is in the range of 10-40㎛. In claim 1, An edge of the pixel electrode overlaps the signal line with the passivation layer interposed therebetween. In claim 1, The passivation layer is a thin film transistor array panel made of an organic insulating material. In claim 1, The passivation layer has a contact hole exposing the contact portion. In claim 5, And a contact member formed of the same layer as the pixel electrode and connected to the contact portion through the contact hole. In claim 5, And the contact hole exposes a boundary of the contact portion. In claim 1, The signal line includes a gate line and a data line crossing each other. In claim 8, The thin film transistor includes a gate electrode that is part of the gate line, a source electrode that is part of the data line, a drain electrode connected to the pixel electrode, and a semiconductor disposed between the gate electrode and the source electrode and the drain electrode. In claim 9, And the semiconductor extends along the data line. In claim 10, And the semiconductor except for the source electrode and the drain electrode have the same planar pattern as the data line and the drain electrode. In claim 1, The pixel electrode is a thin film transistor array panel made of IZO or ITO. Forming a gate line having a gate electrode on the substrate, Stacking a gate insulating film on the substrate; Forming a semiconductor layer on the gate insulating layer; Forming a data line and a drain electrode having a source electrode in contact with the semiconductor layer, A first portion covering the semiconductor layer, the first portion having a contact hole exposing a contact portion of the gate line or the data line for connection with an outside, a second portion thicker than the first couple, the first portion and the second portion Forming a protective film comprising a third portion formed of a tapered structure having an inclination angle of 5-10 ° or less between Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 13, The protective film forming step is formed by a photolithography process using a mask, The mask corresponds to the first portion and the third portion, and includes a first region transmitting only a part of the light, a second region corresponding to the contact hole and transmitting most of the light, and corresponding to the third portion. A method of manufacturing a thin film transistor array panel including a third region to be blocked. The method of claim 14, The mask may be a thin film transistor array panel in which a slit or a lattice pattern is formed in the first region. The method of claim 15, And a width or an interval of a slit or a lattice pattern of the first region gradually increases or decreases closer to the third region. The method of claim 16, The width of the slit of the first region corresponding to the first portion is constant, and the width of the light shielding pattern defining the slit of the first region corresponding to the third portion is gradually increased closer to the third region. The manufacturing method of the thin film transistor array panel. In claim 13, The passivation layer is formed of an organic insulating material. In claim 13, The pixel electrode is formed of IZO or ITO.