KR100984352B1 - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

A gate line is formed over the insulating substrate, and a gate insulating film is stacked over the insulating substrate. Subsequently, the semiconductor and the ohmic contact are sequentially stacked, a data line and a drain electrode are formed thereon, then a protective film is laminated and a photoresist pattern is formed thereon. In this case, the photoresist pattern includes a first portion having an uneven pattern and corresponding to the contact portion, and a second portion thicker than the first portion. The photoresist pattern is patterned using an etch mask to form a protective film and a gate insulating film to form a contact hole exposing the drain electrode and a boundary thereof in the contact portion. At this time, a protective film remains on the gate insulating film around the drain electrode boundary line exposed through the contact hole to form an uneven pattern. Next, a pixel electrode connected to the drain electrode is formed through the contact hole.

Unevenness, IZO, Contact Resistance, Slit, Pixel Electrode

Description

Thin film transistor array panel and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL AND METHOD FOR MANUFACTURING THE PANEL}

1 is a thin film transistor array panel for a liquid crystal display according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 1 taken along the line II-II ′.

3 is an enlarged cross-sectional view illustrating a structure of a contact unit in a thin film transistor array panel according to an exemplary embodiment of the present invention.

4, 6, 8, and 12 are layout views of the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 3 according to one embodiment of the present invention. Are listed,

5, 7, 9, and 13 show the thin film transistor array panels shown in FIGS. 4, 6, 8, and 12, respectively, as follows: Vb-Vb 'line, VIIb-VIIb' line, IXb-IXb 'line, and XIIIb. A cross section taken along the line -XIIIb ',

FIG. 10 is a cross-sectional view taken along the line IX-IX 'of FIG. 8 and illustrates the next step of FIG. 9.

11 and 14 are cross-sectional views illustrating the next steps of FIGS. 9 and 13, respectively, in which the structure of the contact portion is enlarged.

15 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

16A and 16B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 15 taken along lines XVIa-XVIa 'and XVIb-XVIb', respectively.

17 is a layout view of a thin film transistor array panel at a first stage of manufacture according to a second embodiment of the present invention;

18A and 18B are cross-sectional views taken along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb' of FIG. 17, respectively.

19A and 19B are cross-sectional views taken along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb' in FIG. 17, respectively, and are cross-sectional views in the next steps of FIGS. 18A and 18B;

20A and 20B are cross-sectional views taken along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb' in FIG. 17, respectively, and are cross-sectional views in the next steps of FIGS. 19A and 19B;

FIG. 21 is a layout view of a thin film transistor array panel in the next step of FIGS. 20A and 20B.

22A and 22B are cross-sectional views taken along the lines XXIIa-XXIIa 'and XXIIb-XXIIb' of FIG. 21, respectively.

FIG. 23 is a layout view of a thin film transistor array panel in the next step of FIGS. 22A and 22B.

24A and 24B are cross-sectional views taken along the lines XXIVa-XXIVa 'and XXIVb-XXIVb', respectively, of FIG. 23.

110 substrate 121 gate line

124: gate electrode 140; Gate insulating film

151, 154: semiconductors 161, 163, 165: ohmic contact members

171: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 190: pixel electrode

81, 82: contact auxiliary member

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

In this case, in order to prevent signal delay, it is common to use a metal material having a low resistance, particularly an aluminum-based metal material such as aluminum (Al) or aluminum alloy (Al alloy). However, since aluminum or aluminum alloys have weak physical or chemical properties, corrosion occurs when they are connected to other conductive materials at the contact portion, thereby degrading display characteristics. In particular, when the pixel electrode is formed using indium tin oxide (ITO) or indium zinc oxide (IZO), which is a transparent conductive material, aluminum or an aluminum alloy may be corroded at the contact portion of ITO or IZO and a signal line of aluminum or an aluminum alloy. The problem arises in that the contact resistance of the contact increases. In order to solve this problem, a technology of forming a signal line by adding a conductive material having a low contact resistance with ITO or IZO has been developed.

In a method of manufacturing a thin film transistor array panel for such a liquid crystal display device using the above technique, when connecting a signal line formed with an insulating layer and a transparent conductive layer to each other, a process of exposing a part of the boundary of the signal line is required to minimize the contact resistance of the contact portion. . However, if the substrate is etched to another insulating layer below the signal line and severely undercuts, the step coverage of the contact portion deteriorates. For this reason, there is a problem in that a profile of the upper layer formed thereafter becomes worse or a disconnection occurs in the contact portion, thereby degrading the reliability of the contact portion. In order to solve this problem, a portion having a middle thickness is provided on the photoresist pattern to prevent another insulating layer under the signal line from being etched and used to form a smooth profile of the contact portion.

In this case, the portion having the intermediate thickness among the photoresist patterns may be prevented from being etched so that the conductive layer or the insulating layer positioned at the lower portion thereof is not initially exposed, and then the portion having the intermediate thickness is used to use the portion left thick as an etching mask. It must be completely removed through the ashing process. However, if the thickness of the portion having an intermediate thickness is thick, even if the ashing process is carried out, the portion having the intermediate thickness is not completely removed and the photoresist film remains at the contact portion, thereby increasing the contact resistance of the contact portion or the thickness of the portion having an intermediate thickness. If thin, the undercut still occurs at the contact, resulting in poor step coverage of the contact.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a thin film transistor array panel and a method of manufacturing the same, which can prevent contact failure at a contact portion while minimizing contact resistance of a contact portion.

In order to solve this problem, in the thin film transistor array panel according to the present invention and a manufacturing process thereof, the photosensitive film of the contact portion is formed in an uneven pattern by adjusting the width and spacing of the slit for controlling the light transmittance in the mask. The insulating film is etched using an etching mask to form an uneven pattern in which the insulating film passes through the boundary of the conductive film at the contact portion.

More specifically, in the method for manufacturing a thin film transistor array panel according to the embodiment of the present invention, first, a gate line is formed on an insulating substrate, a gate insulating film is laminated, and a semiconductor layer is formed. Subsequently, a data line crossing the gate line and a drain electrode separated from the data line are formed, and then a protective film is laminated and the protective film is patterned to form a first contact hole exposing the drain electrode and the gate insulating film around the drain electrode. Next, a pixel electrode connected to the drain electrode is formed on the passivation layer through the first contact hole. At this time, the gate insulating film exposed through the first contact hole in the first contact hole forming step is formed in a concave-convex pattern having a boundary line passing through the boundary line of the drain electrode together with the protective film.

In this manufacturing method, a second or third contact hole exposing the end portion of the data line or the end portion of the gate line may be formed in the first contact hole forming step.

In this case, the forming of the first to third contact holes may be performed by forming a photoresist pattern on the passivation layer, etching the gate insulating layer and the passivation layer using the photoresist pattern as an etch mask, and the photoresist pattern having an uneven pattern and having first and second patterns. It is preferred to include a first portion corresponding to the contact hole, a second portion thicker than the first portion, a third portion thinner than the first portion and corresponding to the third contact hole.                     

In the first to third contact hole forming steps, first, the gate insulating film or the protective film under the third portion is etched using the first and second portions as etching masks, and then an ashing process is performed. Subsequently, the protective film or the gate insulating film under the second portion is etched using the first portion as an etching mask.

It is preferable to leave a part of the second part on top of the protective film in the ashing step.

The gate line or data line is preferably formed of a lower film of chromium or molybdenum or molybdenum alloy and an upper film of aluminum or aluminum alloy, and preferably, the upper conductive film is removed before the pixel electrode forming step.

The pixel electrode may be formed of IZO, and the data line and the semiconductor layer may be patterned together by a photolithography process using a photoresist pattern having a different thickness.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a gate line is formed on an insulating substrate, and a semiconductor is formed on the gate insulating layer covering the gate wiring. A drain electrode is formed on the gate insulating film and is separated from the data line and the data line. The drain electrode covers the data line and the drain electrode, and has a first contact hole exposing at least part of a boundary line of the drain electrode. A partially remaining protective film is also formed on the upper portion of the protective film, and a pixel electrode connected to the drain electrode is formed at least on the first contact hole. At this time, the gate insulating film and the protective film positioned in the first contact hole are formed with an uneven pattern having a boundary line passing through the boundary line of the drain electrode.

The pixel electrode is in contact with the gate insulating film and the drain electrode along the surface of the uneven pattern in the first contact hole.

The gate insulating film and the protective film are preferably made of silicon nitride, and the pixel electrode is preferably made of IZO.

The passivation layer has a second contact hole that exposes the end of the gate line together with the end of the data or the gate insulating film, and is formed of the same layer as the pixel electrode, and the end of the data line or the end of the gate line through the second contact hole. It may further include a contact auxiliary member connected to each.

In the second contact hole, it is preferable that the boundary line of the end portion of the gate line or the end portion of the data line is exposed, and the gate line or data line and the drain electrode are formed as a lower layer of chromium or molybdenum or molybdenum alloy and an upper layer of aluminum or aluminum alloy. It is preferred that the top film is removed from the first and second contact holes.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a portion of a layer, film, region, plate, etc. is said to be "on top" of another part, this includes not only when the other part is "right on" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the structure of a thin film transistor array panel completed through a manufacturing process according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel according to a first exemplary embodiment of the present invention, FIG. 2 is a cross-sectional view of the thin film transistor array panel of FIG. 1 taken along line II-II ′, and FIG. A portion of the contact portion of the cross-sectional view taken along the line II-II 'of the thin film transistor array panel 1 is illustrated in detail.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a part of each gate line 121 forms a plurality of gate electrodes 124. In addition, another portion of each gate line protrudes downward to form a plurality of expansions 127.

The gate line 121 includes two layers having different physical properties, that is, a lower layer 121p and an upper layer 121q thereon. The upper layer 121q is made of a metal having a low resistivity, for example, aluminum-based metal such as aluminum (Al) or aluminum alloy, so as to reduce the delay or voltage drop of the gate signal. In contrast, the lower layer 121p is a material having excellent physical, chemical, and electrical contact properties with other materials, particularly indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum alloys). -Tungsten (MoW) alloy], chromium (Cr) and the like. An example of the combination of the lower layer 121p and the upper layer 121q may be a chromium / aluminum-neodymium (Nd) alloy. In FIG. 1, lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, and lower and upper layers of the expansion unit 127 are denoted by reference numerals 127p and 127q, respectively.

Side surfaces of the lower layer 121p and the upper layer 121q are inclined, respectively, and the inclination angle thereof is about 30 to 80 ° with respect to the surface of the substrate 110.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

On the semiconductor 151, a plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with high concentration of silicide or n-type impurities are formed. It is. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitors are disposed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively. conductor 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to the gate electrode 123. The gate electrode 123, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The storage capacitor conductor 177 overlaps the extension portion 127 of the gate line 121.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are also disposed on the lower films 171p, 173p, 175p, and 177p such as molybdenum (Mo), molybdenum alloy, and chromium (Cr). The upper layer is made of aluminum-based metals 171q, 173q, 175q, and 177q.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has an exposed portion between the source electrode 173 and the drain electrode 175 and is not covered by the data line 171 and the drain electrode 175, and in most places, the linear semiconductor 151 is provided. Although the width of is smaller than the width of the data line 171, as described above, the width becomes larger at the portion that meets the gate line 121 to strengthen the insulation between the gate line 121 and the data line 171.

On the data line 171, the drain electrode 175, the conductive capacitor 177 for the storage capacitor, and the exposed portion of the semiconductor 151, an organic material or plasma chemical vapor deposition having excellent planarization characteristics and photosensitivity. A passivation layer 180 made of a low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F, or the like formed by enhanced chemical vapor deposition (PECVD) is formed.

In an embodiment in which the passivation layer 180 is made of a storage material, the passivation layer 180 may be formed to prevent the organic material of the passivation layer 180 from coming into contact with the portion of the semiconductor 151 exposed between the data line 171 and the drain electrode 175. An insulating film made of silicon nitride or silicon oxide may be added to the lower portion of the silver organic film.                     

The passivation layer 180 includes a plurality of contact holes 185, 187, and 182 that respectively expose the drain electrode 175, the storage capacitor conductor 177, and the end portion 179 of the data line 171. Formed. As described above, the embodiment in which the passivation layer 180 has a contact hole 182 exposing the end portion 179 of the data line 171 connects an external data driving circuit to the data line 171 using an anisotropic conductive layer. For this reason, the data line 171 has a contact portion, and the end portion 179 of the data line 171 may have a width wider than that of the data line 171 as necessary. In the present embodiment, the gate line 121 does not have a contact portion at the end portion. In this structure, the end portion of the gate line 121 is directly connected to the output terminal of the gate driving circuit formed directly on the substrate.

On the other hand, the end portion of the gate line 121 may have a contact portion like the end portion of the data line. In this embodiment, the passivation layer 180 together with the gate insulating layer 140 may expose a plurality of end portions of the gate line 121. Has a contact hole.

The contact holes 185, 187, and 182 expose the drain electrode 175, the conductor 177 for the storage capacitor, and the end portion 179 of the data line 171. In the contact holes 185, 187, and 182, In order to secure contact characteristics with the conductive film of ITO or IZO formed afterwards, it is preferable that the aluminum-based upper films 175q and 177q are not exposed. To this end, the upper layers 175q and 177q are removed from the contact holes 185, 182, and 187 to expose the lower layers 175p and 177p, and the data line 179 is formed of only the lower layer. In this case, the contact holes 185, 187, and 182 have a boundary line between the drain electrode 175, the storage capacitor conductor 177, and the end portion 179 of the data line 171.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 made of IZO or ITO are formed on the passivation layer 180.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the contact holes 185 and 187, respectively, to receive a data voltage from the drain electrode 175, and to connect the conductor. Transfer data voltage to 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied. .

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off, thereby enhancing the voltage holding capability. In order to achieve this, another capacitor connected in parallel with the liquid crystal capacitor is provided, which is called a "storage electrode". The storage capacitor is made by overlapping the pixel electrode 190 and the neighboring gate line 121 (which is referred to as a "previous gate line"), and the like, to increase the capacitance of the storage capacitor, that is, the storage capacitance. In order to increase the overlapped area by providing an extension part 127 extending the gate line 121, a protective film conductor 177 connected to the pixel electrode 190 and overlapping the extension part 127 is provided as a protective film. 180) Place it underneath to bring the distance between the two closer.                     

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 82 are connected to the end portions 179 of the data lines through the contact holes 182, respectively. The contact auxiliary member 82 is not essential to serve to protect and protect adhesiveness between each end portion 179 of the data line 171 and an external device such as a driving integrated circuit, and whether or not to apply them. Is optional. Of course, the end portion of the gate line 121 is also connected to the contact auxiliary member through the contact hole of the protective film like the end portion of the data line.

At this time, the drain electrode 175, the storage capacitor conductor 177, and the gate insulating layer 140 outside the boundary of the data line end portion 179, which are substantially exposed through the contact holes 182, 187, and 187 at the contact portion, remain. The pixel electrode 190 and the contact auxiliary member 82 have a concave-convex structure together with a portion of the passivation layer, and a drain electrode 175, a conductive capacitor 177 for a storage capacitor, and a data line that are formed along the upper surface of the concave-convex structure. Is connected to the portion 179. This will be described in detail with reference to FIG. 3. Here, only the structure in which the drain electrode and the pixel electrode are connected will be described with reference to an example.

As shown in FIG. 3, a portion of the passivation layer 180 remains on the gate insulating layer 140 on the substrate 110 exposed through the contact hole 185 at the contact portion, and the gate insulating layer 140 and the passivation layer 180 are formed. Has an uneven structure. Here, the dotted lines show the shapes of the gate insulating layer 140 and the remaining passivation layer 180 positioned on the side of the drain electrode 175. In this case, the pixel electrodes 190 formed on the passivation layer 180 are stacked along the uneven surface and are connected to the drain electrode 175. The structure of these contacts can be equally applied to the other contacts described above. In the structure of the contact portion, at least a portion of the gate insulating layer 140 positioned under the drain electrode 175 at the boundary of the drain electrode 175 is etched to the lower portion of the drain electrode 175 so that an undercut occurs. ) Is not undercut, and the remaining passivation layer 180 remains. Therefore, even if a portion of the pixel electrode 190 connected to the drain electrode 175 is disconnected at the portion where the undercut has occurred, a portion of the gate insulating layer 140 where the undercut has not occurred and the pixel electrode (the upper portion of the remaining passivation layer 180) 190 is connected to drain electrode 175 while maintaining a gentle profile. Therefore, in the thin film transistor array panel according to the exemplary embodiment of the present invention, contact failure can be prevented at the contact portion while minimizing contact resistance at the contact portion.

According to another embodiment of the present invention, a transparent conductive polymer may be used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistant 82 may be made of a material different from the pixel electrode 190, in particular, IZO or ITO.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 to 3 will be described in detail with reference to FIGS. 4 to 12 and FIGS. 1 to 3.

4, 6, 8, and 12 are layout views of a thin film transistor array panel at an intermediate stage of a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 through 3 according to an embodiment of the present invention. 5, 7, 9, and 13 show the thin film transistor array panels shown in FIGS. 4, 6, 8, and 12, respectively, in the Vb-Vb 'line, the VIIb-VIIb' line, and the IXb- line. FIG. 9 is a cross-sectional view taken along the line IXb 'and XIIIb-XIIIb', FIG. 9 is a cross-sectional view showing the next step of FIG. 8, and FIGS. 11 and 14 are structures of a contact portion in a manufacturing method according to an embodiment of the present invention. It is a cross-sectional view.

First, two layers of a metal film, that is, a lower metal film and an upper metal film, are sequentially stacked on an insulating substrate 110 made of transparent glass, for example, by sputtering. The lower metal film is made of a metal having excellent contact properties with IZO or ITO, for example, molybdenum, molybdenum alloy or chromium, and preferably has a thickness of about 500 kPa. The upper metal film is made of an aluminum-based metal, and preferably has a thickness of about 2,500 Å.

4 and 5, a gate including a plurality of gate electrodes 124 and a plurality of extensions 127 is formed by sequentially patterning an upper metal layer and a lower metal layer in a photolithography process using a photoresist pattern. A line 121 is formed.

The patterning of the top layer 121q, which is an aluminum-based metal, is CH3COOH (8-15%) / HNO3 (5-8%) / H3PO4 (50-60%), an aluminum etchant that can be etched while giving a side slope to all of aluminum. It is possible to proceed with wet etching using / H 2 O (rest), and when the lower layer 121p is molybdenum or molybdenum alloy, it can be etched while giving a side slope under the same etching conditions.

As shown in Figs. 6 and 7, a three-layer film of a gate insulating film 140, intrinsic amorphous silicon, and an impurity amorphous silicon layer is successively laminated, and an impurity amorphous silicon layer and an intrinsic The amorphous silicon layer is photo-etched to form a linear intrinsic semiconductor 151 including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154, respectively. As the material of the gate insulating layer 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa.

Next, two layers of the metal film, that is, the lower metal film and the upper metal film, are sequentially stacked by sputtering. The lower metal film is made of a metal having excellent contact properties with IZO or ITO, for example, molybdenum, molybdenum alloy or chromium, and preferably has a thickness of about 500 kPa. The upper metal film is made of an aluminum-based metal, and preferably has a thickness of about 2,500 Å.

8 and 9, a plurality of data lines 171, a plurality of drain electrodes 175 each including a plurality of source electrodes 173 by patterning the upper metal film and the lower metal film in turn. A plurality of conductors 177 for the storage capacitor are formed.

Subsequently, the photosensitive layer on the data line 171 and the drain electrode 175 is removed or left untouched, and is exposed without being covered by the data line 171, the drain electrode 175, and the storage capacitor conductor 177. By removing the portion of the impurity semiconductor 164, the plurality of linear ohmic contacts 161 and the plurality of island type ohmic contacts 165 each including a plurality of protrusions 163 are completed, while the intrinsic semiconductor 151 thereunder. ) To expose the part.                     

In this case, when the exposed impurity semiconductor 164 is removed using the data line 171 and the drain electrode 175 as an etching mask, the molybdenum series constituting the data line 171 and the drain electrode 175 is removed. In order to prevent the conductive film from being damaged, the impurity semiconductor 164 is etched using CF ₄ + HCl gas.

Subsequently, in order to stabilize the surface of the portion of the intrinsic semiconductor 151, oxygen plasma is preferably followed.

Next, a protective film 180 is formed by stacking an inorganic insulating film such as silicon nitride or an organic insulating film having a low dielectric constant, and applying a photoresist film thereon by a spin coating method thereon, and then through the mask 500. After irradiating light to the photoresist film, the photoresist film is developed to form photoresist patterns 52 and 54 as shown in FIG. 10.

At this time, the thickness of the developed photosensitive film patterns 52 and 54 varies depending on the position. In FIG. 10, the photosensitive film is formed of first to third portions whose thickness becomes smaller. The first part located in the area A1 (hereinafter referred to as "rest area") and the second part located in area C1 (hereinafter referred to as "contact area") are denoted by reference numerals 52 and 54, respectively. Here, in the third part, the photosensitive film is almost completely removed and is not shown in the drawings of this embodiment. The third portion is a position for removing the passivation layer 180 and the gate insulating layer 140 together to expose the end portion of the gate line 121 in the embodiment in which the gate line 121 has a contact portion at an end portion thereof. If the gate insulating layer 140 and the passivation layer 180 formed of the same layer as the line 121 are to be removed, the third portion may be formed. The ratio of the thicknesses of the first portion 52 and the second portion 54 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 54 is 1/2 of the thickness of the first portion 52. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less.

As described above, there may be various methods of varying the thickness of the photoresist film according to the position, and the transparent mask and the light blocking area as well as the translucent area may be provided in the exposure mask. Yes. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness.

Substantially, as shown in FIG. 11, the photosensitive film 54 having a thin thickness located in the contact region is formed into a concave-convex structure, which forms a slit 510 or a slit of the mask 500 located in the contact region C1. The photosensitive film may be exposed by adjusting the width and interval of the light shielding pattern 520 to be defined.

The method of forming the second portion of the photoresist film with the concave-convex structure at the contact portion is performed even when developing the photoresist film 54 having the intermediate thickness on the upper portion of the end portion 179 of the holding capacitor conductor 177 and the data line 171. The same can be applied.

Subsequently, the photoresist patterns 52 and 54 are used as etch masks to etch the passivation layer 180 and the gate insulating layer 140, which are lower layers thereof. In this case, initially, the gate insulating layer 140 and the protective layer 180 under the third portion from which the photoresist layer is removed are removed, but at least the gate insulating layer 140 must remain in the second region C1. To this end, a portion 54 having an intermediate thickness of the photoresist pattern is formed, and when the gate insulating layer 140 and the protective layer 180 corresponding to the third portion are initially removed, the drain electrode 175 and the storage capacitor are contacted. The passivation layer 180 and the gate insulating layer 140 are not exposed around the boundary line between the conductor 177 and the end portion 179 of the data line. As a result, when the protective layer 180 and the gate insulating layer 140 are removed from the third portion, the gate insulating layer 140 is not exposed at the contact portion, so that the drain electrode 175 is disposed at the contact portion when the protective layer 180 is etched during the subsequent etching process. It is possible to prevent the gate insulating layer 140 disposed below the etched portion from being etched to prevent the undercut from occurring in the contact portion. In this case, a portion of the photoresist of the second region C1 may also be etched.

Next, as shown in FIGS. 12 and 13, the portion 54 having an intermediate thickness is removed by an ashing process, and then the passivation layer 180 is formed by using the photoresist pattern 52 of the remaining first region A1 as an etching mask. Etching is performed to form contact holes 182, 185, and 187. Next, the upper layer 177q exposed through the contact holes 182, 185, and 187 in the end portion 179 of the data line 171, the drain electrode 175, and the storage capacitor conductor 177 through aluminum front etching. 175q, 171q)). In this embodiment, an ashing process is performed by forming the photoresist pattern 54 of the second region C1 to have an uneven structure, so that the photoresist is formed on the drain electrode 175 and the end portion 179 of the data line 171. Although all are removed, a part of the photosensitive film of an uneven | corrugated pattern remains in a contact part. Accordingly, when the passivation layer 180 and the gate insulating layer 140 are etched using the photoresist pattern 52 as an etching mask, the passivation layer 180 may be formed on the gate insulating layer 140 exposed from the contact holes 182, 185, and 187. A part remains, and the gate insulating layer 140 forms an uneven pattern together with the passivation layer 180 remaining in the contact holes 182, 185, and 187. At this time, the boundary line of the uneven pattern crosses the boundary line of the conductive film such as the end portion 179 of the data line, the conductor 177 for the storage capacitor, and the drain electrode 175. The uneven pattern may include the passivation layer 180, but may not be the same, so that the boundary line of the uneven pattern may overlap the boundary line of the conductive layer.

At this time, unlike the present embodiment, the portion 54 having the intermediate thickness is not formed in the uneven pattern, but the portion 54 having the intermediate thickness may be formed at a predetermined thickness, but the photoresist film 54 of the contact region C1 may be formed. It may be thick or thin. In the case where the photoresist film 54 is thick, even if the ashing process is performed, the portion 54 having an intermediate thickness is not completely removed in the ashing process so that the photoresist film remains at the contact portion, which is located above the drain electrode 175 at the contact portion. Since the passivation layer 180 is not completely removed, the contact resistance between the drain electrode 175 and the pixel electrode 190 increases. In addition, when the thickness of the portion 54 having the intermediate thickness is thin, the gate insulating layer 140 under the drain electrode 175 is etched in the subsequent etching process, resulting in undercut, resulting in poor step coverage of the contact portion. As a result, the pixel electrode 190 may be disconnected due to the step of the undercut connected to the drain electrode 175.

At this time, the photoresist film positioned on the upper portion of the drain electrode 175 made of metal remains thinner than other portions, which is reflected light generated by the drain electrode 175 during exposure, and thus the photoresist film overlaps the drain electrode 175. This is because the irradiation amount of light increases more than other parts. For this reason, even when the photoresist film is formed in the uneven pattern in the contact region C1, the upper portion of the conductive film such as the end portion 179 of the data line, the conductive capacitor 177 for the storage capacitor, and the drain electrode 175 can be completely removed in the ashing process. When the contact holes 182, 185, and 187 are formed, the protective film 180 remains on the conductive film such as the end portion 179 of the data line, the conductive capacitor 177 for the storage capacitor, and the drain electrode 175. Can be prevented.

Next, as shown in FIGS. 1 to 3, an ITO or IZO film is stacked and patterned using a mask to form a plurality of pixel electrodes 190 and a plurality of contact assistants 82. At this time, the sputtering temperature of IZO or ITO is preferably 250 ° C or less in order to minimize contact resistance.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, some gate insulating layers 140 positioned below the drain electrode 175 at the boundary of the drain electrode 175 at the contact portion are etched to the lower portion of the drain electrode 175. Even when an undercut occurs, at least a portion of the gate insulating layer 140 has a portion that is not undercut. Therefore, even if a portion of the pixel electrode 190 connected to the drain electrode 175 is disconnected at the portion where the undercut has occurred, a portion of the gate insulating layer 140 where the undercut has not occurred and the pixel electrode (the upper portion of the remaining passivation layer 180) 190 is connected to drain electrode 175 while maintaining a gentle profile. Therefore, in the thin film transistor array panel according to the exemplary embodiment of the present invention, contact failure can be prevented at the contact portion while minimizing contact resistance at the contact portion. In addition, the contact portion is sufficiently in contact with the lower layer 701 having a low contact resistance with the IZO or ITO film to minimize the contact resistance of the contact portion.

The structure of the thin film transistor array panel according to the exemplary embodiment of the present invention includes a conductive film made of aluminum or an aluminum alloy in which the gate line 121 and the data line 171 have low resistance, and at the same time, the contact portion, in particular, the data line and the pixel electrode 190. Contact resistance can be minimized and can be applied to a large screen high-definition liquid crystal display device. In addition, when the gate driving integrated circuit or the data driving integrated circuit is mounted to connect the gate line 121 and the data line 171, the profile of the contact portion may be gentle to ensure reliability of the contact portion.

As described above, the structure of the contact portion may be applied to a thin film transistor array panel manufactured using five masks, but the same may be applied to a thin film transistor array panel for liquid crystal display devices manufactured using four masks. . In a manufacturing method using a four-sheet mask, different layers are patterned into one photoresist pattern using a photoresist pattern including a portion having an intermediate thickness in order to reduce manufacturing costs. This will be described in detail with reference to the drawings.

First, a unit pixel structure of a thin film transistor array panel for a liquid crystal display according to a second exemplary embodiment of the present invention will be described in detail with reference to FIGS. 15, 16A, and 16B.

FIG. 15 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment, and the thin film transistor array panel illustrated in FIGS. 15A and 16B is along the XVIa-XVIa 'line and the XVIb-XVIb' line, respectively. It is sectional drawing cut out.

As shown in FIGS. 15 to 16B, the layer structure of the thin film transistor array panel for a liquid crystal display device according to the present exemplary embodiment is generally the same as the layer structure of the thin film transistor array panel for liquid crystal display devices illustrated in FIGS. 1 to 3. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. On the ohmic contacts 161 and 165 and the gate insulating layer 140, a plurality of data lines 171 including a plurality of source electrodes 153, a plurality of drain electrodes 175, and a plurality of conductive capacitors 177. ) Is formed and a passivation layer 180 is formed thereon. A plurality of contact holes 182, 185, 187, and 181 are formed in the passivation layer 180 and / or the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members are formed on the passivation layer 180. 81 and 82 are formed.

However, unlike the thin film transistor array panel shown in FIGS. 1 to 3, the thin film transistor array panel according to the present embodiment is electrically connected to the gate line 121 on the same layer as the gate line 121 instead of having an extension portion on the gate line 121. A plurality of storage electrode lines 131 separated by the plurality of layers are overlapped with the drain electrode 175 to form a storage capacitor. The storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside, and the storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient. In order to maximize the aperture ratio of the pixel, the pixel may be disposed at an edge of the pixel area.

The semiconductor 151 has a planar shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. . In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165. ) Has an exposed portion between them.

In addition, the gate line 121 has a contact portion for connecting to the driving circuit at the end portion 129, and the end portion 129 of the gate line 121, which is a contact portion, is connected to the gate insulating layer 140 and the passivation layer 180. It is exposed through the contact hole 181 formed, and is connected with the contact auxiliary member 81 formed in the upper part of the protective film 180 through the contact hole 181.

Of course, in the thin film transistor array panel for the liquid crystal display according to the second embodiment of the present invention, the end portion 179 and the drain electrode 175 of the data line 171 exposed through the contact holes 181, 182, and 185 at the contact portion of the liquid crystal display according to the second exemplary embodiment of the present invention. The gate insulating layer 140 or the remaining passivation layer 180 around the boundary line of the () is formed of an uneven pattern, and the boundary line of the uneven pattern crosses the boundary of the end portion 179 of the data line 171 and the drain electrode 175. . In addition, the contact auxiliary members 81 and 82 and the pixel electrode 190 are stacked along the uneven pattern so that the end portion 179 of the data line 171, the end portion 129 of the gate line 121, and the drain electrode ( 175).

Next, a method of manufacturing a thin film transistor array panel for a liquid crystal display device having the structure of FIGS. 15 to 16B according to an embodiment of the present invention will be described in detail with reference to FIGS. 17 to 24B and 15 to 16B. .

FIG. 17 is a layout view of a thin film transistor array panel at a first stage of manufacture according to a second embodiment of the present invention, and FIGS. 18A and 18B are cut along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb', respectively, in FIG. 17. 19A and 19B are cross-sectional views taken along the lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb' in FIG. 17, respectively, and are cross-sectional views in the next steps of FIGS. 18A and 18B, and FIGS. 20A and 20B are respectively FIGS. 17 is a cross-sectional view taken along lines XVIIIa-XVIIIa 'and XVIIIb-XVIIIb', which are cross-sectional views of the next steps of FIGS. 19A and 19B, and FIG. 21 of the thin film transistor array panel of the next steps of FIGS. 20A and 20B. 22A and 22B are cross-sectional views taken along the lines XXIIa-XXIIa 'and XXIIb-XXIIb' in FIG. 21, respectively, and FIG. 23 is a layout view of the thin film transistor array panel in the next steps of FIGS. 22A and 22B. 24A and 24B are respectively shown in FIG. 2 3 is a cross-sectional view taken along the lines XXIVa-XXIVa 'and XXIVb-XXIVb'.

First, as shown in FIGS. 17, 18A, and 18B, the upper metal layer and the lower metal layer are stacked on the insulating substrate 110 as in the first embodiment, and patterned by a photolithography process to form a plurality of gate lines 124. A plurality of gate lines 121 and a plurality of sustain electrode lines 131 each of which is formed are formed. Here, reference numerals 131p and 131q may be a lower layer and an upper layer of the storage electrode line 131, and the storage electrode line 131 may have a storage electrode extending to a wide width.

As shown in FIGS. 19A and 19B, the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are each about 1,500 kPa to about 5,000 kPa and about 500 kPa using chemical vapor deposition. Continuous deposition to a thickness of from about 2,000 kPa to about 300 kPa. Subsequently, the lower film 170p and the upper film 170q are successively stacked by a method such as sputtering to form a conductor layer 170, and then a photosensitive film is applied thereon to a thickness of 1 μm to 2 μm, and then, The photosensitive film is irradiated with light through a photomask (not shown), and then developed to form photosensitive film patterns 62 and 64.

At this time, the thickness of the developed photoresist film varies depending on the position, and the photoresist film is composed of first to third portions whose thickness becomes smaller. The first part located in the area A2 (hereinafter referred to as the "wiring area") and the second part located in the area C2 (hereinafter referred to as the "channel area") are denoted by reference numerals 62 and 64, respectively, and the area B2. The reference numeral 3 is not given to the third part located in the " (hereinafter referred to as " other region ") because the third part has a thickness of 0, so that the conductive layer 170 below is exposed. The ratio of the thicknesses of the first portion 62 and the second portion 64 varies depending on the process conditions in the subsequent process, but the thickness of the second portion 64 is 1/2 of the thickness of the first portion 62. It is preferable to set it as the following, for example, it is good that it is 4,000 Pa or less.

Therefore, a plurality of data lines 171 and a plurality of drain electrodes 175 each including a plurality of source electrodes 173 as shown in FIGS. 21, 22A, and 22B are formed through a series of etching steps, and a plurality of protrusions are formed. A plurality of linear ohmic contacts 161 each including 163, a plurality of island-like ohmic contacts 165, and a plurality of linear semiconductors 151 including a plurality of protrusions 154 are formed.                     

For convenience of description, portions of the conductor layer 170, the impurity amorphous silicon layer 160, and the intrinsic amorphous silicon layer 150 positioned in the wiring region A2 are referred to as first portions, and the conductor layer located in the channel region C2. A portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 is referred to as a second portion, and the conductor layer 170 located in the other region B2, the impurity amorphous silicon layer 160, and intrinsic A part of the amorphous silicon layer 150 is called a third part.

One example of the order of forming such a structure is as follows.

(1) removing the third portion of the conductor layer 170, the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region B2,

(2) removing the second portion 64 of the photosensitive film located in the channel region C2,

(3) removing the second portion of the conductor layer 170 and the impurity amorphous silicon layer 160 located in the channel region C2, and

(4) Removal of the first portion 62 of the photosensitive film located in the wiring area A2.

Another example of this order is as follows.

(1) removing the third portion of conductor layer 170 located in other region B2,

(2) removing the second portion 64 of the photosensitive film located in the channel region C2,

(3) removing the third portions of the impurity amorphous silicon layer 160 and the amorphous silicon layer 150 located in the other region B2,

(4) removing the second portion of conductor layer 170 located in channel region C2,

(5) removing the first portion 62 of the photosensitive film located in the wiring region A2, and

(6) Removal of the second portion of the impurity amorphous silicon layer 160 located in the channel region C2.                     

This section describes the first example.

First, as illustrated in FIGS. 20A and 20B, the upper layer 170q and the lower layer 170p of the conductor layer 170 exposed to the other region B2 are removed by wet or dry etching to remove the impurities in the lower portion. The third portion of the silicon layer 160 is exposed. The aluminum-based conductive film mainly proceeds by wet etching, and the molybdenum-based conductive film may be selectively wet and dry etched, and the double layer of the upper layer 170q and the lower layer 170p may be patterned by one wet etching condition. It may be.

Reference numeral 174 denotes a conductor in which the data line 171 and the drain electrode 175 are still attached, and reference numerals 174p and 174q denote upper and lower layers of the conductor. When dry etching is used, the upper portion of the photoresist films 62 and 64 may be cut out to a certain thickness.

Subsequently, the third portion of the impurity amorphous silicon layer 160 and the lower intrinsic amorphous silicon layer 150 positioned in the other region B2 is removed, and the second photoresist film 64 of the channel region C2 is removed. To expose the second portion of the conductor 174 below. Removal of the second portion 64 of the photoresist film is performed simultaneously with or separately from removal of the third portion of the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150. Residue of the second portion 64 remaining in the channel region C2 is removed by ashing.

In this step, the linear intrinsic semiconductor 151 is completed. Reference numeral 164 denotes a linear impurity amorphous silicon layer 160 in which the linear ohmic contact 161 and the island-like ohmic contact 165 are still attached to each other, which is referred to as a (linear) impurity semiconductor in the future.

In this case, when the lower layer 170p of the conductor layer 170 is patterned by dry etching, the impurity amorphous silicon layer 160 and the intrinsic amorphous silicon layer 150 are continuously dry-etched to simplify the manufacturing process. In this case, the same etching chamber may or may not be performed by an in-situ method of performing dry etching on three layers 170p, 160, and 150 in succession.

Next, as illustrated in FIGS. 21, 22A and 22B, the second portion of the conductor 174 and the linear impurity semiconductor 164 positioned in the channel region C2 is etched and removed. In addition, the remaining photoresist first portion 62 is also removed.

In this case, as shown in FIG. 22B, a portion of the linear intrinsic semiconductor 151 located in the channel region C2 may be removed to reduce the thickness, and the first portion 62 of the photoresist layer may have a small thickness. Etched to thickness.

In this way, each of the conductors 174 is completed while being separated into one data line 171 and a plurality of drain electrodes 175, and each of the impurity semiconductors 164 is formed of one linear ohmic contact 161 and a plurality of electrodes. Completed by dividing into the island resistive contact member 165.

Next, as shown in FIGS. 23, 24A, and 24B, as in the first embodiment, a protective film 180 is formed by stacking silicon nitride or silicon oxide on the substrate 110, and then the gate insulating layer 140. And a plurality of contact holes 181, 185, and 182. In this case, the photoresist pattern includes a third portion having almost no thickness. In an embodiment in which the photoresist film includes the third portion, the protective film 180 or the gate insulating layer 140 under the third portion is first etched using the photoresist pattern as an etch mask before the ashing process, and then the ashing process is performed. In the same manner as in the first embodiment, the contact holes 182, 185, and 181 are completed.

Finally, as shown in FIGS. 15 to 16B, a IZO or ITO layer having a thickness of 500 μs to 1,500 μs is deposited by a sputtering method and etched to photograph the plurality of pixel electrodes 190 and the plurality of contact assistants 81. 82). In the case of using the IZO layer, the etching is preferably wet etching using an etching solution for chromium such as (HNO3 / (NH4) 2Ce (NO3) 6 / H2O), and since the etching solution does not corrode aluminum, ), The aluminum conductive film may be prevented from corroding in the drain electrode 175 and the gate line 121.

In this embodiment, the data line 171, the drain electrode 175, the ohmic contacts 161 and 165, and the semiconductor 151 are formed in one photo process together with the effect according to the first embodiment. The process can be simplified.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, in the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, when the contact portion is formed, the photoresist pattern having a medium thickness is formed in the uneven pattern, and the insulating film around the conductive film is formed in the uneven pattern passing through the boundary of the conductive film. The contact resistance of the contact portion can be minimized with uniform and reproducibility, and the reliability of the contact portion can be improved by preventing disconnection at the contact portion.

Claims (17)

A gate line formed over the insulating substrate, A gate insulating film covering the gate line, A semiconductor formed on the gate insulating film, A data line formed on the gate insulating layer and a drain electrode separated from the data line; A protective film covering the data line and the drain electrode and having a first contact hole exposing a boundary line of the drain electrode; A pixel electrode connected to the drain electrode through the first contact hole and formed on the passivation layer; Including, The passivation layer remains on the gate insulating layer exposed through the first contact hole, and the gate insulating layer and the passivation layer exposed through the first contact hole together form a concave-convex pattern having a boundary line passing through a boundary line of the drain electrode. Thin film transistor array panel. In claim 1, The pixel electrode is in contact with the gate insulating layer, the drain electrode, and the passivation layer along a surface of the uneven pattern at the first contact hole. In claim 1, The thin film transistor array panel of which the gate insulating film and the protective film are made of silicon nitride. In claim 1, The pixel electrode is a thin film transistor array panel made of IZO. In claim 1, The passivation layer has a second contact hole exposing an end portion of the gate line together with an end portion of the data line or the gate insulating layer. And a contact auxiliary member formed on the same layer as the pixel electrode and connected to an end portion of the data line or an end portion of the gate line through the second contact hole. In claim 5, The thin film transistor array panel of which a boundary line of an end portion of the gate line or an end portion of the data line is exposed in the second contact hole. In claim 6, And the gate line, the data line and the drain electrode are formed of a lower layer of chromium, molybdenum or molybdenum alloy, and an upper layer of aluminum or aluminum alloy. In claim 7, And the upper layer is removed from the first and second contact holes. Forming a gate line on the insulating substrate, Stacking a gate insulating film on the gate line; Forming a semiconductor layer on the gate insulating film, Forming a data line crossing the gate line and a drain electrode separated from the data line; Stacking a passivation layer on the data line and the drain electrode; Patterning the passivation layer to form a first contact hole exposing the drain electrode and the gate insulating layer around the drain electrode; Forming a pixel electrode connected to the drain electrode through the first contact hole on the passivation layer, The thin film transistor is formed in the first contact hole forming step by forming the gate insulating film on the gate insulating film exposed through the first contact hole to form the gate insulating film in a concave-convex pattern having a boundary line passing the boundary line of the drain electrode together with the protective film. The manufacturing method of a display panel. The method of claim 9, And forming a second or third contact hole exposing an end portion of the data line or an end portion of the gate line in the first contact hole forming step. In claim 10, The forming of the first to third contact holes may be performed by forming a photoresist pattern on the passivation layer, etching the gate insulating layer and the passivation layer using the photoresist pattern as an etching mask, and the photoresist pattern has an uneven pattern. Fabrication of a thin film transistor array panel including a first portion corresponding to first and second contact holes, a second portion thicker than the first portion, and a third portion thinner than the first portion and corresponding to the third contact hole. Way. In claim 11, The first to third contact hole forming step, Etching the gate insulating film or the protective film under the third portion using the first and second portions as an etching mask, Removing the second portion of the photoresist pattern by an ashing process; Etching the passivation layer or gate insulating layer under the second portion using the first portion as an etching mask; Method of manufacturing a thin film transistor array panel comprising a. In claim 12,  And manufacturing the second portion above the passivation layer exposed through the first to third contact holes in the ashing process. The method of claim 9, The gate line or the data line is formed of a lower layer of chromium or molybdenum or molybdenum alloy and an upper layer of aluminum or aluminum alloy. The method of claim 14, And removing the upper conductive layer before the pixel electrode forming step. The method of claim 9, The pixel electrode is formed of IZO. The method of claim 9, And the data line and the semiconductor layer are formed by patterning together the photolithography process using a photoresist pattern having a different thickness.

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