KR20060004718A - Thin film transistor array panel and manufacturing method thereof - Google Patents

Abstract

A gate line is formed on the substrate, a gate insulating film and a semiconductor layer are sequentially stacked on the gate line, and a lower conductive film and an upper conductive film are deposited on the semiconductor layer. Subsequently, the upper conductive layer, the lower conductive layer and the semiconductor layer are photo etched, and then a protective layer is deposited, and the protective layer is photo etched to expose the first and second portions of the upper conductive layer. Subsequently, the first and second portions of the upper conductive layer are removed to expose the first and second portions of the lower conductive layer, and then the pixel electrode covering the first portion of the lower conductive layer and the auxiliary source electrode exposing a portion of the second portion are exposed. A portion of the semiconductor layer is exposed by removing the second portion of the lower conductive film between the auxiliary source electrode and the auxiliary drain electrode while forming the auxiliary drain electrode. Oxygen slamming is then performed to form a channel passivation layer on the exposed portion of the semiconductor layer.

Plasma, Channel Shielding, Semiconductor, IZO, ITO

Description

Thin film transistor array panel and manufacturing method thereof

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor substrate illustrated in FIG. 1 taken along lines IIa-IIa 'and IIb-IIb',

3, 5, 7, and 10 are layout views of the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1, 2A, and 2B according to an embodiment of the present invention. The drawings are listed in order,

4A and 4B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively.

6A and 6B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 5 taken along lines VIa-VIa 'and VIb-VIb', respectively.

8A and 8B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively.

9A and 9B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 7 taken along the lines VIIIa-VIIIa 'and VIIIb-VIIIb', respectively, and are views of the next steps of FIGS. 8A and 8B.

11A and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along lines XIa-XIa 'and XIb-XIb', respectively.

12 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 13 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 12 taken along the line XII-XII ′.

14, 16, 18, and 20 are layout views of the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 12 and 13 according to an embodiment of the present invention. The drawings listed,

FIG. 15 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 14 taken along the line XV-XV ′,

FIG. 17 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 16 taken along the line XVI-XVI ′.

FIG. 19 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 18 taken along the line XIX-XIX ′,

FIG. 21 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 20 taken along the line XXI-XXI ′.

22 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment of the present invention.                 

23A and 23B are cross-sectional views of the thin film transistor substrate illustrated in FIG. 22 taken along lines XXIIIa-XXIIIa 'and XXIIIb-XXIIIb',

24, 26, 28, and 30 are layout views of the thin film transistor array panel at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 22, 23A, and 23B according to an embodiment of the present invention. The drawings are listed in order,

25A and 25B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 24 taken along lines XXVa-XXVa 'and XXVb-XXVb', respectively.

27A and 27B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 28 taken along lines XXVIIa-XXVIIa 'and XXVIIb-XXVIIb', respectively.

29A and 29B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 28 taken along lines XXIXa-XXIXa 'and XXIXb-XXIXb', respectively.

31A and 31B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 30 taken along lines XXXIa-XXXIa 'and XXXIb-XXXIb', respectively.

<Description of the symbols for the main parts of the drawings>

110: substrate 121, 129: gate line

124: gate electrode 140; Gate insulating film

151, 154: semiconductors 161, 163, 165: ohmic contact members

171, 179: data line 173: source electrode

175: drain electrode 180: protective film

181, 182, 185: contact hole 189: opening                 

190: pixel electrode 81, 82: contact auxiliary member

80: channel shield

The present invention relates to a thin film transistor array panel and a method of manufacturing the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal element for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode are provided. Install on the display panel.

Such a liquid crystal display panel has a layered structure in which a plurality of conductive layers and an insulating layer are stacked. The gate line, the data line, and the pixel electrode are made of different conductive layers (hereinafter, referred to as respective gate conductors, data conductors, and pixel conductors) and separated into insulating layers, which are generally arranged in order from the bottom.

A thin film transistor array panel having such a layered structure is manufactured through a plurality of thin film deposition and photolithography processes, and how many stable elements are formed through a small number of photolithography processes is an important factor in determining a manufacturing cost.

The technical problem of the present invention is to provide a thin film transistor array panel and a method of manufacturing the same which can reduce manufacturing cost through a small number of photographic processes.

In order to achieve the above object, in the present invention, the conductive film is etched using the protective film or the pixel electrode as a mask to complete the data line and the drain electrode having the source electrode, and the upper portion of the exposed semiconductor layer is formed as a channel protective film using oxygen plasma. .

More specifically, in the method of manufacturing a thin film transistor array panel according to an exemplary embodiment of the present invention, a gate line is formed on a substrate, a gate insulating film and a semiconductor layer are sequentially stacked on the gate line, and a conductive film is deposited on the semiconductor layer. Subsequently, the conductive film and the semiconductor layer are photo-etched, the protective film is deposited, and then the photo-etched is exposed to expose the first and second portions of the conductive film, thereby forming a pixel electrode covering the first portion of the conductive film. Subsequently, the second portion of the conductive film is removed to complete the data line and the drain electrode made of the conductive film, and oxygen plasma is performed to form a portion of the semiconductor layer under the second portion as a channel protective film.

In the passivation photolithography step, the third portion of the conductive layer may be exposed, and in the pixel electrode forming step, the contact auxiliary member may be formed. It is preferable to form a contact auxiliary member for covering a portion of the gate line.

The gate line may include a lower layer and an upper layer, and the gate insulating layer may be etched together to expose a portion of the upper layer of the gate line, and the exposed gate line upper layer may be removed to expose a portion of the lower gate line layer. Do.

The pixel electrode forming step and the data line and drain electrode finishing steps may be performed in the same etching process. The conductive film may be formed of chromium and the pixel electrode may be formed of IZO.

The gate line and the conductive film may be formed of aluminum or molybdenum, and may be formed of a double or triple film made of a first conductive film containing aluminum or a second conductive film containing molybdenum, and the pixel electrode may be formed of ITO. It is preferable to form.

The semiconductor layer includes an intrinsic semiconductor film and an impurity semiconductor film, and after the conductive film is removed, an exposed portion of the impurity semiconductor film is formed as a channel protective film.

In this case, the conductive layer may include a lower conductive layer and an upper conductive layer, and the first and second portions of the lower conductive layer may be removed by removing the first and second portions of the upper conductive layer in the first and second partial exposure steps of the conductive layer. The auxiliary source electrode and the auxiliary drain electrode covering the second portion are formed in the pixel electrode forming step. In this case, the upper conductive layer is preferably formed of chromium, and the pixel electrode, the auxiliary source electrode, and the auxiliary drain electrode are preferably formed of IZO.

The forming of the pixel electrode, the auxiliary source electrode and the auxiliary drain electrode, and the partially exposing the semiconductor layer may be performed together, and may be performed under the same etching conditions.

In the passivation photolithography step, the first portion of the conductive layer and the gate insulating layer adjacent thereto may be exposed together.

In the thin film transistor array panel according to the exemplary embodiment of the present invention, a gate line including a gate electrode is formed on an insulating substrate, and a gate insulating layer covering the gate line is formed. A semiconductor layer and an ohmic contact are sequentially formed on the gate insulating film. A data line and a drain electrode having a source electrode are formed thereon, and a channel protective film is formed over the semiconductor layer between the source electrode and the drain electrode. A passivation layer having a first contact hole exposing the drain electrode and an opening exposing a channel passivation layer between the source electrode and the drain electrode is formed on the data line and the drain electrode, and a passivation layer is formed on the passivation layer to contact the drain electrode through the first contact hole. The pixel electrode is formed. At this time, the boundary line of the passivation layer in the opening coincides with the boundary line of the source electrode and the drain electrode.

It is preferable that the boundary of the channel protective film in the opening coincides with the boundary of the ohmic contact member.                     

The gate line includes a lower layer and an upper layer, and further includes a contact auxiliary member covering a portion of the lower layer, wherein the lower layer of the gate line is made of Cr, and the upper layer is made of a conductive layer containing Al.

The data line and the drain electrode include a conductive film of chromium, wherein the pixel electrode is preferably made of IZO.

The gate line, the data line, and the drain electrode may include a first conductive film including aluminum and a second conductive film including molybdenum, wherein the pixel electrode is preferably made of ITO.

The data line and the drain electrode include a lower conductive layer and an upper conductive layer, and the boundary lines between the lower conductive layer and the upper conductive layer exposing the semiconductor may not coincide with each other. An auxiliary source electrode and an auxiliary drain electrode covering the electrode may be formed. The lower conductive film boundary lines of the source electrode and the drain electrode exposing the semiconductor layer preferably correspond to the boundary lines of the auxiliary source electrode and the auxiliary drain electrode facing each other.

The first contact hole may expose a portion of the conductive layer under the drain electrode and the adjacent gate insulating layer.

Then, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.                     

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1, 2A, and 2B.

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B illustrate the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively. One cross section.

A plurality of gate lines 121 are formed on the insulating substrate 110 to transfer gate signals. The gate line 121 mainly extends in the horizontal direction, and a portion of each gate line 121 protrudes upward to form a plurality of gate electrodes 124.

The gate line 121 includes two layers having different physical properties, that is, a lower layer and an upper layer thereon. The upper layer is made of a metal having a low resistivity, such as aluminum (Al) or an aluminum alloy, so as to reduce the delay or voltage drop of the gate signal. In contrast, the underlayer is a material having excellent physical, chemical and electrical contact properties with other materials, in particular indium tin oxide (ITO) or indium zinc oxide (IZO), such as molybdenum (Mo) and molybdenum alloys (eg, molybdenum-tungsten (MoW). ) Alloy], and chromium (Cr). Preferred examples of the combination of the lower layer and the upper layer include two layers etched under different etching conditions such as Cr / Al, Cr / Al-Nd alloy, and the like. In FIGS. 2A and 2B, the lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, respectively. The lower and upper layers of the end portion 129 of the gate line 121 for contact with other portions are respectively represented. Reference numerals 129p and 129q are denoted, and a portion of the upper layer 129q of the end portion 129 is removed to expose the lower layer 129p.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of extensions 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

A channel passivation layer 80 made of silicon oxide is formed on the semiconductor 151 protrusion 154 between the protrusion 163 and the island contact member 165. In this case, the channel passivation layer 80 may be formed of the same layer as the ohmic contacts 161 and 165 and may have a thickness extending to the upper portion of the semiconductor 151. The channel passivation layer 80 protects the semiconductor 151 between the protrusion 163, which is a channel portion of the thin film transistor, and the island contact member 165 from being exposed to the outside, thereby preventing deterioration of the characteristics of the thin film transistor.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined, and the inclination angle is 30 to 80 degrees.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165, respectively.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. A plurality of branches extending from both data lines 171 to both sides of the drain electrode 175 form a source electrode 173. The pair of source electrode 173 and the drain electrode 175 are separated from each other with respect to the channel passivation layer 80, and their boundary lines coincide with the boundary lines of the channel passivation layer 80. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. The protrusion 154 is formed below the channel passivation layer 80 between the electrode 173 and the drain electrode 175.                     

The data line 171 and the drain electrode 175 also include the lower conductors 171p and 175p and the upper conductors 171q and 175q disposed thereon. At this time, the lower conductors 173p and 175p are exposed out of the upper conductors 173q and 175q in the source electrode 173 and the drain electrode 175, and the boundary lines of the lower conductors 173p and 175 are thin film transistor channels. Define the width and spacing of the. As in the case of the gate line 121, a preferable example of the combination of the lower conductors 171p and 175p and the upper conductors 171q and 175q may be formed under different etching conditions such as Cr / Al and Cr / Al-Nd alloys. Two layers to be etched. In FIGS. 2A and 2B, the lower and upper layers of the source electrode 173 are denoted by reference numerals 173p and 173q, respectively. The lower and upper layers of the end portion 179 of the data 171 for contacting with other portions are shown, respectively. Reference numerals 179p and 179q indicate that a portion of the upper layer 179q of the end portion 179 is removed to expose the lower layer 179p.

The lower layers 171p and 175p and the upper layers 171q and 175q of the data line 171 and the drain electrode 175 are also inclined at an angle of about 30 to 80 °, similarly to the gate line 121.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 in the lower portion thereof, the data line 171 and the drain electrode 175 in the upper portion thereof, and serve to lower the contact resistance therebetween. The semiconductor 151 has a planar shape substantially the same as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 below the semiconductor 151 except for the protrusion 154 where the thin film transistor is located.

On the data line 171 and the drain electrode 175, a-Si: C formed by plasma enhanced chemical vapor deposition (PECVD), an organic material having excellent planarization characteristics, photosensitivity, and plasma deposition. A passivation layer 180 made of a low dielectric constant insulating material such as: O, a-Si: O: F, or silicon nitride, which is an inorganic material, is formed.

The passivation layer 180 includes a plurality of contact holes 182 exposing the end portion 179 of the data line 171, the drain electrode 175, and the gate insulating layer 140 adjacent to the drain electrode 175. 185 and a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 together with the gate insulating layer 140. The passivation layer 180 also has an opening 189 exposing the channel passivation layer 80 over the protrusion 154 of the semiconductor 151. At this time, a portion of the lower conductors 173p and 175p is exposed through the opening 189 between the source electrode 173 and the drain electrode 175.

The contact holes 181 and 182 expose only the lower films 129p, 179p and 175p of the gate line 121, the drain electrode 175 and the end portions 129 and 179 of the data line 171, and the boundary thereof is located at the top thereof. Coincides with the boundaries of the films 129q, 179q, and 175q. The contact hole 185 exposes the lower layer 175p of the drain electrode and the adjacent gate insulating layer 140.

A plurality of pixel electrodes 190, a plurality of auxiliary source electrodes 193 and an auxiliary drain electrode 195, and a plurality of contact assistants 81 and 82 are formed on the passivation layer 180. And they are made of a transparent conductive material of IZO. In this case, since the contact hole 185 connecting the drain electrode 175 and the pixel electrode 190 is formed to the adjacent gate insulating layer 140, the upper layer 175q of the drain electrode is undercut by overetching. Can be prevented. Therefore, the contact area between the pixel electrode 190 formed on the gate insulating layer 140 and the lower layer 175p of the drain electrode is large, so that contact failure can be prevented from occurring.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive a data voltage from the drain electrode 175. The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules between the two electrodes by generating an electric field together with a common electrode (not shown) of another display panel (not shown) to which the common voltage is applied. Let's do it.

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with it, which is called a storage capacitor. The storage capacitor is made by overlapping the pixel electrode 190 with another gate line 121 adjacent thereto (referred to as a prior gate line) or a storage electrode formed separately. The storage electrode is made of the same layer as the gate line 121 and is separated from the gate line 121 to receive a voltage such as a common voltage. In order to increase the capacitance of the storage capacitor, that is, the capacitance, the area of the overlapped portion is increased or the conductor connected to the pixel electrode 190 and overlapped with the front gate line or the storage electrode under the protective film 180 is disposed between the two. You can get close.

The contact auxiliary members 81 and 82 are connected to the end portion 129 of the gate line and the end portion 179 of the data line through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device, and do not necessarily serve to protect them. Their application is optional.

The boundary lines of the auxiliary source electrode 193 and the auxiliary drain electrode 195 facing each other are located below and the lower conductors 173p and 175p of the source electrode 173 and the drain electrode 175 defining the channel of the thin film transistor. 273p and 175p completely exposed through the opening 189. That is, the boundary between the opening 189 passing through the source electrode 173 and the drain electrode 175 is completely covered by the auxiliary source electrode 193 and the auxiliary drain electrode 195.

According to another embodiment of the present invention, a transparent conductive polymer, ITO, or the like is used as the material of the pixel electrode 190, and in the case of a reflective liquid crystal display, an opaque reflective metal may be used. In this case, the contact assistants 81 and 82 may be made of ITO or IZO.

Then, referring to FIGS. 3 to 11B and FIGS. 1 to 2A and 2B for a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 1, 2A and 2B according to an embodiment of the present invention. This will be described in detail.

First, as illustrated in FIGS. 3, 4A, and 4B, a plurality of gate lines 121 including a plurality of gate electrodes 124 are formed on an insulating substrate 110 such as transparent glass by a photolithography process. . The gate line 121 is formed of a double layer of the lower layers 124p and 129p and the upper layers 124q and 129q. The lower layers 124p and 129p are about 500 Cr thick Cr and the upper layers 124q and 129q. Al-Nd having a thickness of about 1,000 kPa to 3,000 kPa, preferably about 2,500 kPa.

As shown in FIGS. 5, 6A, and 6B, the gate insulating layer 140, the intrinsic amorphous silicon, and the impurity amorphous silicon layer are chemical vapor deposition (CVD). Then, the lower metal film and the upper metal film are sequentially stacked by sputtering, and then four layers of the upper and lower metal film, the impurity amorphous silicon layer, and the intrinsic amorphous silicon layer are photo-etched to obtain a plurality of upper and lower conductors (174q). , 174p), and a plurality of linear intrinsic semiconductors 151 each including a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154.

As the material of the gate insulating layer 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa. The thicknesses of the intrinsic semiconductor 151 and the impurity semiconductor 164 are preferably about 500 mW to 1,500 mW and about 300 mW to 600 mW, respectively. The lower conductor 174p is made of Cr having a thickness of about 500 kV, and the upper conductor 174q is made of Al or Al-Nd having a thickness of about 1,000 mW to 3,000 mW, preferably about 2,500 mW. As a target material of the upper conductor 174q, an Al-Nd alloy containing aluminum or 2 atomic% of Nd is suitable, and sputtering temperature is preferably about 150 ° C.

Next, as shown in FIGS. 7, 8A, and 8B, a protective film 180 having a thickness of 3,000 Å or more is stacked, a photoresist film 40 is formed thereon, and then dry-etched together with the gate insulating layer 140. A plurality of contact holes 181, 182, and 185 and a plurality of openings 189 are formed. The contact hole 181 exposes the upper layer 129q of the end portion 129 of the gate line 121, and the contact holes 182 and 185 and the opening 189 are a part of the upper conductor 174q, that is, FIG. 1. 2A and 2B, a portion of an end portion 179 of the data line 171, a portion of the drain electrode 175 and an adjacent gate insulating layer 140, and a source electrode 173 and a drain electrode ( A portion of 175 and the area between them 173 and 175 are revealed respectively. At this time, by forming the contact hole 185 and the opening 189 by patterning the passivation layer 180 of the corresponding region using slit exposure, the gate insulating layer 140 exposed in the contact hole 185 is overetched to form a lower conductor ( Undercutting to the bottom of 174p) can be prevented.

That is, the contact hole 181 completely exposes and develops the passivation layer 180 and the photoresist layer 40 on the gate insulating layer 140 of the corresponding portion, and the passivation layer 180 and the gate insulating layer of the portion where the contact hole 181 is to be formed. 140 is formed by first etching. In this case, the contact hole 185 and the opening 189 are slit-exposed and developed on the photoresist film 40 on the passivation layer 180 of the corresponding site, leaving the photoresist film in a thin thickness, whereby the contact hole 185 and the opening 189 are formed. The passivation layer 180 may not be etched. The protective film 180 of the portion where the contact hole 185 and the opening 189 are to be formed is exposed by removing the photosensitive film having a thin thickness through an etch back process, and a second etching is performed to form a contact hole ( The contact hole 185 and the opening 189 are formed by only removing the passivation layer 180 of the portion where the opening 185 and the opening 189 are to be formed. Therefore, when the passivation layer 180 and the gate insulating layer 140 are etched by the first etching so that the upper layer 129q of the end portion 129 of the gate line 121 is exposed, the contact hole 185 and the opening 189 are etched. ) Is not etched so that the gate insulating layer 140 under the passivation layer 180 of the contact hole 185 and the opening 189 is not overetched. It is possible to prevent the gate insulating layer 140 from being cut under the conductor 174p. In this case, even in the contact hole 182 exposing the end portion 179 of the data line 171, the boundary line of the lower conductor 171p may be completely exposed, such as the contact hole 185 exposing the drain electrode 175. have.

9A and 9B, the exposed portions of the upper layer 121q and the upper conductor 174q of the gate line 121 are removed while the photosensitive layer 40 is left or removed as it is, and the lower layer 121p is removed. While exposing the lower conductor 174p, the upper layers 171q and 175q of the data line 171 and the drain electrode 175 are completed. In this case, the etching conditions of the upper layer 121q and the upper conductor 174q of the gate line 121 may be set such that the lower layer 121p and the lower conductor 174p are not etched. In this case, the upper conductor 174q to be etched may be over-etched under the passivation layer 180 to cause an undercut.

Next, as illustrated in FIGS. 10, 11A, and 11B, 400 Å to 500 Å thick IZO films are stacked by sputtering and photo-etched to form a plurality of pixel electrodes 190 and a plurality of contact assistants 81, 82. ). In this case, a plurality of auxiliary source electrodes 193 and auxiliary drain electrodes 195 for defining the channel of the thin film transistor to separate the lower conductors 174p are also formed, and the lower conductors 174p exposed between them. Is etched to separate the lower conductors 171p and 175p to complete the data line 171 and the drain electrode 175. Here, since the IZO layer is patterned with a chromium etchant used to etch chromium, the lower conductors 171p and 175p may be etched under the same etching conditions while the IZO layer is etched. When the material of the pixel electrode 190, the auxiliary source electrode 193, the auxiliary drain electrode 195, and the contact auxiliary members 81 and 82 is IZO, the target is indium x-metal oxide (IDIXO) manufactured by Idemitsu, Japan. ), And include In2O3 and ZnO, and the content of zinc in the total amount of indium and zinc is preferably in the range of about 15-20 atomic%. In addition, it is preferable that the sputtering temperature of IZO is 250 ° C. or less in order to minimize contact resistance. IZO can be etched with a weak acid such as oxalic acid.

The contact auxiliary members 81 and 82 and the pixel electrode 190 are disposed on the lower layer 129p and the drain electrode 175 of the end portion 129 of the gate line 121 exposed through the contact holes 181, 182, and 185. ) And a portion of the lower conductor 174p and the gate insulating layer 140 of the end portion 179 of the data line 171.

1 and 2A and 2B, the impurity semiconductor 164 exposed between the source electrode 173 and the drain electrode 175 is formed as a channel passivation layer 80 by performing an oxygen plasma process. The ohmic contacts 161 and 165 are completed.

As described above, in the exemplary embodiment of the present invention, the lower conductor 174p exposed while patterning the auxiliary source electrode 193 and the auxiliary drain electrode 195 is etched to complete the source electrode 173 and the drain electrode 175, Subsequently, the impurity semiconductor 164 is etched to expose the protrusion 154 of the semiconductor. As a result, the thin film transistor channel between the source electrode 173 and the drain electrode 175 may be uniformly formed on the entire surface of the substrate, and the width and the gap of the channel may be uniformly controlled.                     

In addition, by forming the channel passivation layer 80 by only an oxygen plasma process without adding a separate photographic process, the manufacturing process may be simplified.

In the manufacturing method according to the exemplary embodiment of the present invention, the thin film transistor array panel may be completed using four masks, thereby simplifying the manufacturing process. That is, when the data line 171 is formed of a double film including an aluminum conductive film, two masks are required. In this embodiment, the data line of the double film can be completed using only one mask, thereby simplifying the manufacturing process. can do.

Meanwhile, the manufacturing process may be simplified by forming the data line as a conductive film that can be patterned under the same etching conditions as the pixel electrode, and this will be described in detail with reference to the accompanying drawings.

12 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 13 is a cross-sectional view of the thin film transistor array panel of FIG. 12 taken along the line XIII-XIII ′, respectively.

As shown in Figs. 12 and 13, most laminated structures are the same as Figs. That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 including a plurality of source electrodes 153 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the passivation layer 180 is formed thereon. Is formed. A plurality of contact holes 182, 185, and 187 are formed in the passivation layer 180 and / or in the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact assistants are formed on the passivation layer 180. 82) is formed.

However, unlike FIGS. 1 and 2B, the data line 171 and the drain electrode 175 are formed of a single layer of chromium, and the gate line 121 does not have a contact portion at an end thereof, so the passivation layer 180 is formed of a gate insulating film ( It does not have a contact hole that exposes the end of the gate line 121 with the 140. In this embodiment, the gate driving circuit is directly formed on the substrate 110 with the same layer as the stacked structure, and an end portion of the gate line is connected to the output terminal of the gate driving circuit.

A plurality of pixel electrodes 190 and a plurality of contact assistants 82 are formed on the passivation layer 180, which are made of IZO.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 12 and 13 according to an embodiment of the present invention will be described in detail with reference to FIGS. 14 to 21, 12, and 13.

First, as shown in FIGS. 14 and 15, a photolithography process is performed on a plurality of gate lines 121 including a plurality of gate electrodes 124 on an insulating substrate 110 such as transparent glass as in the previous embodiment. To form. In this case, when the gate driving circuit is directly formed on the substrate 110, a part of the gate driving circuit of the same layer as the gate line 121 is also formed.

As shown in Figs. 16 and 17, the gate insulating film 140, the intrinsic amorphous silicon layer, and the impurity amorphous silicon layer (extrinsic amorphous silicon) may be formed by chemical vapor deposition (CVD). Unlike the exemplary embodiment, a single layer of chromium (Cr) is stacked by sputtering, and then four layers of a conductive film, an impurity amorphous silicon layer, and an intrinsic amorphous silicon layer are photo-etched to obtain a plurality of conductors 174 and a plurality of linear impurities. A plurality of linear intrinsic semiconductors 151 each including a semiconductor 164 and a plurality of protrusions 154 are formed.

Next, as shown in FIGS. 18 and 19, a protective film 180 having a thickness of 3,000 kPa or more is stacked, a photosensitive film 40 is formed thereon, and then dry-etched together with the gate insulating layer 140 to contact the plurality of contacts. Holes 182 and 185 and a plurality of openings 189 are formed.

Next, as shown in FIG. 20 and FIG. 21, the IZO film having a thickness of 400 kHz to 500 kHz is stacked by sputtering and photoetched in the same manner as in the previous embodiment to contact the plurality of pixel electrodes 190 with the plurality of data. The auxiliary member 82 is formed. In this case, the contact auxiliary member 82 and the pixel electrode 190 contact the drain electrode 175 and the end portion 179 of the data line 171 exposed through the contact holes 182 and 185, and the periphery thereof. A portion of the gate insulating layer 140 is covered. However, the portion of the lower conductor 174 exposed to the opening 189 is exposed as it is, without being covered. The etchant for patterning the IZO film is used as the etchant for patterning the chromium film. As a result, the exposed portion of the conductor 174 is removed together when the IZO film is etched to expose the impurity semiconductor 164 while completing the data line 171 and the drain electrode 175.

12 and 13, the exposed portion of the impurity semiconductor 164 between the source electrode 173 and the drain electrode 175 is subjected to oxygen plasma to form a channel passivation layer 80 and to form ohmic contact. Complete the members 161 and 165.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the photolithography process using four masks may be completed, thereby simplifying the manufacturing process, thereby minimizing the manufacturing cost. In particular, when the pixel electrode 190 is patterned, the conductors in the upper portion of the channel portion are etched under the same etching conditions to complete the data line 171 and the drain electrode 175, thereby simplifying the manufacturing process and minimizing the manufacturing cost. have.

In the above embodiment, the pixel electrode is formed of an IZO film, but may be formed of an ITO film. In this embodiment, the data line is preferably made of a conductive film made of aluminum, molybdenum, or an alloy thereof. It will be described in detail with reference to.

FIG. 22 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment, and FIGS. 23A and 23B are cut along the lines XXIIIa-XXIIIa 'and XXIIIb-XXIIIb', respectively, of FIG. 22. It is sectional drawing.

As shown in Figs. 22 to 23B, the layered structure and the arrangement structure of the thin film transistor array panel for the liquid crystal display device according to the present embodiment are generally the same as the layered structure of the thin film transistor array panel for the liquid crystal display device shown in Figs. . That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 including a plurality of source electrodes 153 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the passivation layer 180 is formed thereon. Is formed. A plurality of contact holes 182, 185, and 181 are formed on the passivation layer 180 and / or on the gate insulating layer 140, and a plurality of pixel electrodes 190 and a plurality of contact auxiliary members (eg, on the passivation layer 180). 81 and 82 are formed.

However, the gate line 121 includes two layers having different physical properties, that is, a lower layer and an upper layer thereon. The gate line 121 has an end portion 129 for contacting an external driving circuit and the like. The lower layer and the upper layer of the end portion 129 are denoted by reference numerals 129p and 129q, respectively. In this case, the lower layers 124p and 129p of the gate line 121 are made of aluminum or an aluminum alloy, and the upper layers 124q and 129q are made of molybdenum or molybdenum alloy.

The data line 171 and the drain electrode 175 are formed of the lower layers 171p and 175p, the upper layers 171r and 175r disposed thereon, and the intermediate layers 171q and 171q positioned therebetween. The lower layers 171p and 175p and the upper layers 171r and 175r are made of a conductive material having excellent contact properties, such as molybdenum, molybdenum alloy, or chromium, and the intermediate layers 171q and 175q are made of a conductive material having low resistance. Preferred examples include three layers which are etched under the same etching conditions as Mo or Mo alloy / Al / Mo or Mo alloy, Mo or Mo alloy / Al alloy / Mo or Mo alloy.

The lower layers 171p and 175p, the intermediate layers 171q and 175q, and the upper layers 171r and 175r of the data line 171 and the drain electrode 175, as well as the gate line 121, have sides of about 30-80 °. Each is inclined at an angle of.

The passivation layer 180 is provided with a plurality of contact holes 181 exposing the end portion 129 of the gate line 121 together with the gate insulating layer 140. The contact hole 181 exposes the boundary of the end portion 129 of the gate line 121. The contact holes 185 and 182 also define the boundary line of the drain electrode 175 and the end portion 179 of the data line 171. It may be revealed.

The gate contact auxiliary member 81 is connected to the end portion 129 of the gate line through the contact hole 181.

In this case, the pixel electrode 190 and the contact auxiliary members 81 and 82 are made of an indium tin oxide (ITO) film, unlike the previous embodiment.

Then, referring to FIGS. 24 to 32b and FIGS. 22, 23a, and 23b for a method of manufacturing the thin film transistor array panel for the liquid crystal display device shown in FIGS. 22, 23a, and 23b according to an embodiment of the present invention. This will be described in detail.

First, as shown in FIGS. 24, 25A, and 25B, a lower layer including aluminum and an upper layer including molybdenum are sequentially stacked on an insulating substrate 110 such as transparent glass, and then patterned to form a plurality of gates. A plurality of gate lines 121 including the electrode 124 and the end portion 129 are formed. In this case, the lower layer including aluminum and the upper layer including molybdenum are patterned with the same etchant using an aluminum etchant for etching aluminum, and are formed in a tapered structure.

As shown in FIGS. 26, 27A and 27B, the gate insulating layer 140, the intrinsic amorphous silicon, and the impurity amorphous silicon layer are chemical vapor deposition (CVD). The lower metal film, the intermediate metal film, and the upper metal film are sequentially stacked by sputtering, and then four layers of the upper, middle and lower metal films, an impurity amorphous silicon layer, and an intrinsic amorphous silicon layer are photographed and etched. And a plurality of linear intrinsic semiconductors 151 each comprising a middle portion, a lower conductor 174r, 174q, and 174p, a plurality of linear impurity semiconductors 164 and a plurality of protrusions 154, respectively.

The lower and upper conductors 174p and 174r are made of molybdenum or molybdenum alloy about 500 kW thick, and the intermediate conductor 174q is made of aluminum or aluminum alloy about 1,000 kPa to 3,000 kPa, preferably about 2,500 kPa thick. As a target material of the intermediate conductor 174q, an Al-Nd alloy containing aluminum or 2 atomic% of Nd is suitable, and sputtering temperature is preferably about 150 ° C.

Next, as shown in FIGS. 28, 29A, and 29B, a protective film 180 having a thickness of 3,000 Å or more is stacked, a photoresist film 40 is formed thereon, and then dry-etched together with the gate insulating film 140. A plurality of contact holes 181, 182, and 185 and a plurality of openings 189 are formed. The contact hole 181 exposes the upper layer 129q of the end portion 129 of the gate line 121, and the contact holes 182 and 185 and the opening 189 are a part of the upper conductor 174r,

Next, as shown in FIGS. 30, 31A, and 31B, 400 to 500 Å thick ITO films are stacked by photolithography and photo-etched to form the plurality of pixel electrodes 190 and the plurality of contact auxiliary members 81 and 82. To form. In this case, the contact auxiliary members 81 and 82 and the pixel electrode 190 are formed of the upper layer 129q and the conductor of the end portion 129 of the gate line 121 exposed through the contact holes 181, 182, and 185. Although the portion 174 is covered, the portion of the conductor 174 exposed through the opening 189 is not covered but is exposed. In addition, since the conductive film including aluminum or molybdenum is etched with respect to the etchant for etching the ITO film, as shown in FIGS. 33A and 33B, the exposed portion of the conductor 174 is removed by full etching to form an impurity semiconductor ( The lower layers 171p and 171q of the data line 171 and the drain electrode 175 are completed while exposing 164.

 Then, as in the previous embodiment, as shown in FIGS. 22 to 23B, oxygen plasma is performed to form an exposed portion of the impurity semiconductor 164 as the channel passivation layer 80 and the ohmic contacts 161 and 165. To complete.

Even in this embodiment, when the pixel electrode 190 and the contact members 81 and 82 are formed, the conductor 174 is patterned to complete the data line 171 and the drain electrode 175 to simplify the manufacturing process and thereby. Manufacturing costs can be minimized. In addition, in the present embodiment, since the conductive film including aluminum is not exposed in the contact holes 181, 182, and 185, the entire surface of the aluminum may be omitted, thereby simplifying the manufacturing process.

In the method of manufacturing the thin film transistor array panel according to the present invention, the source electrode and the drain electrode are separated by using the passivation layer, the pixel electrode, and the contact auxiliary member, thereby reducing the number of photographic processes, simplifying the process, and lowering the manufacturing cost and increasing the yield.

In addition, by forming a channel passivation layer using only an oxygen plasma process without adding a separate photolithography process, the manufacturing process may be simplified to minimize manufacturing costs.

In addition, the width of the channel and the width of the channel of the thin film transistor may be controlled and formed by separating the source electrode and the drain electrode using the auxiliary electrode and exposing a portion of the semiconductor where the channel of the thin film transistor is formed.

In addition, by widening the contact hole where the drain electrode and the pixel electrode are connected to the portion where the gate insulating film is formed, the upper layer of the drain electrode is undercut to prevent the defective contact with the pixel electrode, and the drain electrode and the pixel electrode are connected. The slit exposure of the passivation film of the corresponding portion to form a contact hole may be prevented from etching the gate insulating film of the corresponding portion.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (32)

Forming a gate line on the substrate, Sequentially depositing a gate insulating film and a semiconductor layer on the gate line; Depositing a conductive film on the semiconductor layer; Photo etching the conductive layer and the semiconductor layer; Depositing a protective film, Photo-etching the passivation layer to expose the first and second portions of the conductive layer; Forming a pixel electrode covering the first portion of the conductive film, Removing a second portion of the conductive film to complete a data line and a drain electrode formed of the conductive film, and Performing an oxygen plasma to form a channel passivation layer on a portion of the semiconductor layer under the second portion Method of manufacturing a thin film transistor array panel comprising a. In claim 1, A method of manufacturing a thin film transistor array panel to expose a third portion of the conductive layer in the protective film photolithography step. In claim 2, And forming a contact auxiliary member covering the third portion in the pixel electrode forming step. In claim 1, A method of manufacturing a thin film transistor array panel to expose a portion of the gate line in the passivation layer photo etching step. In claim 4, And forming a contact auxiliary member covering a portion of the gate line in the pixel electrode forming step. In claim 1, The gate line includes a lower layer and an upper layer. In claim 6, And etching the gate insulating film together in the passivation photolithography step to expose a portion of the upper layer of the gate line. In claim 7, And removing a portion of the gate line lower layer to expose a portion of the gate line lower layer together. In claim 1, And forming the pixel electrode and completing the data line and the drain electrode in the same etching process. In claim 9, And the conductive film is formed of chromium. In claim 10, The pixel electrode is formed of IZO. In claim 1, And the gate line and the conductive film include aluminum or molybdenum. In claim 12, And the gate line and the conductive film are formed of a double film or a triple film made of a first conductive film containing aluminum or a second conductive film containing molybdenum. In claim 12, The pixel electrode is formed of ITO. In claim 1, The semiconductor layer includes an intrinsic semiconductor film and an impurity semiconductor film, And removing the conductive layer to form an exposed portion of the impurity semiconductor layer as the channel passivation layer. In claim 1, The conductive layer includes a lower conductive layer and an upper conductive layer, In the step of exposing the first and second portions of the conductive layer, the first and second portions of the upper conductive layer are removed to expose the first and second portions of the lower conductive layer. And forming an auxiliary source electrode and an auxiliary drain electrode covering the second portion in the pixel electrode forming step. The method of claim 16, And the upper conductive layer is formed of chromium, and the pixel electrode, the auxiliary source electrode, and the auxiliary drain electrode are formed of IZO. The method of claim 17, And forming the pixel electrode, the auxiliary source electrode, the auxiliary drain electrode, and partially exposing the semiconductor layer. The method of claim 18, And forming the pixel electrode, the auxiliary source electrode, the auxiliary drain electrode, and partially exposing the semiconductor layer under the same etching conditions. In claim 1, And a first portion of the conductive layer and a gate insulating layer adjacent thereto are exposed together in the passivation photolithography step. Board, A gate line formed on the substrate and including a gate electrode; A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, An ohmic contact formed on the semiconductor layer, A data line and a drain electrode formed on the ohmic contact and having a source electrode; A channel passivation layer formed on the semiconductor layer between the source electrode and the drain electrode A passivation layer formed on the data line and the drain electrode, the passivation layer having a first contact hole exposing the drain electrode and an opening exposing the channel passivation layer between the source electrode and the drain electrode; A pixel electrode formed on the passivation layer and in contact with the drain electrode through the first contact hole; The boundary line of the passivation layer in the opening coincides with the boundary line of the source electrode and the drain electrode. The method of claim 21, The boundary of the channel passivation layer in the opening coincides with the boundary of the ohmic contact. The method of claim 21, And a contact auxiliary member including the gate line lower layer and the upper layer and covering a portion of the lower layer. The method of claim 23, The lower layer of the gate line is made of Cr, and the upper layer of the gate line is a thin film transistor array panel made of a conductive film containing Al. The method of claim 24, The data line and the drain electrode may include a conductive film of chromium. The method of claim 25, The pixel electrode is a thin film transistor array panel made of IZO. The method of claim 21, The gate line, the data line, and the drain electrode include a first conductive layer including aluminum and a second conductive layer including molybdenum. The method of claim 27, The pixel electrode is made of ITO. The method of claim 21, The data line and the drain electrode include a lower conductive layer and an upper conductive layer, and the boundary lines between the lower conductive layer and the upper conductive layer exposing the semiconductor do not coincide with each other. The method of claim 29, And an auxiliary source electrode and an auxiliary drain electrode formed on the same layer as the pixel electrode and covering the source electrode and the drain electrode which are part of the data line in the opening. The method of claim 30, And the lower conductive layer boundary lines of the source electrode and the drain electrode exposing the semiconductor layer coincide with the boundary lines of the auxiliary source electrode and the auxiliary drain electrode facing each other. The method of claim 21, The first contact hole exposes a portion of the lower conductive layer under the drain electrode and an adjacent gate insulating layer.

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