KR20060063250A - Manufacturing method of thin film transistor array panel - Google Patents

Abstract

The present invention relates to a method of manufacturing a thin film transistor array panel, the method comprising: forming a gate line including a gate electrode on a substrate, forming a gate insulating film on the gate line, forming a semiconductor layer on the gate insulating film, and Forming a resistive contact member over the semiconductor layer, forming a photoresist film over the resistive contact member, removing a first portion of the photosensitive film, and forming a conductive film over the second portion of the photosensitive film and the exposed resistive contact member Removing the second portion of the photoresist layer to form a data line and a drain electrode; depositing a protective film on the data line and the drain electrode to selectively etch the pixel electrode; and forming a pixel electrode connected to the drain electrode. Forming a step. At this time, the photosensitive film is negative, and in this case, the conductive film has a triple film. After removing the first portion of the photoresist film, a conductive film is formed on the second portion and the other portion of the photoresist film to form data lines and drain electrodes, so that there is a risk of unstable signal transmission or disconnection caused by poor profiles due to different etching conditions. To prevent.

Thin film transistor display panel, slit, mask, undercut, photoresist, negative, lift-off

Description

Manufacturing method of thin film transistor array panel {MANUFACTURING METHOD OF THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively.

3, 10, and 12 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process.

4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively.

5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along the lines IVa-IVa 'and IVb-IVb', respectively, and are views of the next steps of FIGS. 4A and 4B.

Figures 6a and 6b show the next steps in Figures 5a and 5b, respectively.

Figures 7a and 7b show the next steps in Figures 6a and 6b, respectively.

8A and 8B show the next steps in FIGS. 7A and 7B, respectively.

Figures 9a and 9b show the next steps in Figures 8a and 8b respectively.                 

11A and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along the lines XIa-XIa 'and XIb-XIb', respectively.

13A and 13B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 12 taken along the lines XIIIa-XIIIa 'and XIIIb-XIIIb', respectively, and are views of the next steps of FIGS. 11A and 11B.

The present invention relates to a method of manufacturing a thin film transistor array panel.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which a field generating electrode is formed and a liquid crystal layer interposed therebetween. It is a display device which controls the transmittance | permeability of the light which passes through a liquid crystal layer by rearranging.

Among the liquid crystal display devices, a field generating electrode is provided in each of two display panels. Among them, a liquid crystal display device having a structure in which a plurality of pixel electrodes are arranged in a matrix form on one display panel and one common electrode covering the entire display panel on the other display panel is mainstream. The display of an image in this liquid crystal display device is performed by applying a separate voltage to each pixel electrode. To this end, a thin film transistor, which is a three-terminal device for switching a voltage applied to a pixel electrode, is connected to each pixel electrode, and a gate line for transmitting a signal for controlling the thin film transistor and a data line for transmitting a voltage to be applied to the pixel electrode. Install on the display panel.

In such a liquid crystal display, in order to prevent signal delay, the gate line or the data line transferring the image signal, the control signal, or the like generally uses a low resistivity material such as aluminum (Al) or aluminum alloy (Al alloy). At this time, since aluminum has a weak physical or chemical property, it is preferable to form another gate having a high contact property and forming a gate line and a data line as a double layer or triple layer together with aluminum or an aluminum alloy. The conductive film containing molybdenum in the metal is advantageously used because it can be patterned under one etching condition with a conductive film containing aluminum.

However, when the gate line and the data line are formed as the double layer or the triple layer in this way, the degree of etching between the layers is different due to the difference in the etching speed between the layers, and the undercut occurs, thereby deteriorating the profile of the cross section. . As a result, disconnection or poor connection of the signal line may reduce the reliability of the operation, and all the etching conditions for each layer need to be taken into account, resulting in process problems such as reduced process margins.

The technical problem to be achieved by the present invention is to improve the profile of the signal line.

Another technical object of the present invention is to achieve good signal transmission.

According to an aspect of the present invention, a method of manufacturing a thin film transistor array panel includes: forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate line, and forming the gate insulating layer Forming a semiconductor layer on the semiconductor layer, forming a resistive contact member on the semiconductor layer, forming a first photosensitive film on the resistive contact member, removing a first portion of the first photosensitive film, and forming the first photosensitive film Forming a conductive film over a second portion of the substrate and the exposed ohmic contact; removing a second portion of the first photosensitive film to form a data line and a drain electrode; depositing a passivation layer on the data line and the drain electrode Selectively etching, and forming a pixel electrode connected to the drain electrode And a step of.

Preferably, the first photosensitive film is negative, and the first photosensitive film may be formed using a photomask having a light blocking area and a transmission area.

The conductive layer may be formed of an upper layer including molybdenum, an intermediate layer including aluminum, and a lower layer including molybdenum, and the gate line may be formed of a lower layer made of aluminum or an aluminum alloy and an upper layer including molybdenum. can do.

Selectively etching the passivation layer may expose a portion of the data line and a portion of the drain electrode.

In the selective etching of the passivation layer, the gate insulating layer may be etched together to expose a portion of the gate line.

The passivation layer and the gate insulating layer have a contact hole exposing an end portion of the gate line and an end portion of the data line, and are connected to an end portion of the gate line and an end portion of the data line through the contact hole in the pixel electrode forming step. It is preferable to form the contact assistant member.

The forming of the ohmic contact may include depositing a gate insulating film, an intrinsic amorphous silicon layer, and an impurity amorphous silicon layer on the gate line, and forming a second photoresist film having a different thickness depending on positions on the impurity amorphous silicon layer; And selectively etching the impurity amorphous silicon layer and the intrinsic amorphous silicon layer using the second photoresist film as a mask to form the ohmic contact member.

The second photoresist layer may be formed using an optical mask having a light blocking region, a transflective region, and a transmissive region.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity, and like reference numerals designate like parts throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Hereinafter, a thin film transistor array panel and a method of manufacturing the same according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, a thin film transistor array panel according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 2B.

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIGS. 2A and 2B are cross-sectional views of the thin film transistor array panel of FIG. 1 taken along lines IIa-IIa 'and IIb-IIb', respectively. One example.

As shown in FIGS. 1 and 2B, a plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate line 121 mainly extends in the horizontal direction and transmits a gate signal, and has a wide end portion for connection with another layer or an external device. A portion of each gate line 121 protrudes downward to form a plurality of gate electrodes 124.

The storage electrode line 131 extends mainly in the horizontal direction and receives a predetermined voltage such as a common voltage applied to a common electrode (not shown) of another display panel (not shown). It includes an extension 137 that extends up and down in width.

The gate line 121 and the storage electrode line 131 include two layers having different physical properties, that is, the lower layers 121p and 131p and the upper layers 121q and 131q thereon. The lower layers 121p and 131q are made of a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum alloy so as to reduce signal delay or voltage drop. Has a thickness of. In contrast, the top films 121q and 131q are materials which have excellent physical, chemical and electrical contact properties with other materials, especially indium zinc oxide (IZO) or indium tin oxide (ITO), such as molybdenum (Mo) and molybdenum alloys. : Molybdenum-tungsten (MoW) alloy], chromium (Cr), etc., and has a thickness in the range of 100-1,000Å. Examples of the combination of the lower layers 121p and 131q and the upper layers 121q and 131q include pure aluminum or aluminum-neodymium (Nd) alloy / molybdenum, and the positions may be interchanged. In FIG. 2, lower and upper layers of the gate electrode 124 are denoted by reference numerals 124p and 124q, respectively.

Side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is in the range of about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. have. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island contact members 165 are paired and positioned on the protrusions 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is 30-80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165.

The data line 171 transferring the data voltage mainly extends in the vertical direction to cross the gate line 121 and has a wide end portion for connection with another layer or an external device. A plurality of branches extending from the data line 171 toward the drain electrode 175 forms a source electrode 173. Each drain electrode 175 has one end portion 177 that is wider and the other end portion that is linear for connection with another layer, and each source electrode 173 has the other end of the drain electrode 175. It is curved to partially surround the end. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor together with the protrusion 154 of the semiconductor 151, and a channel of the thin film transistor is a source electrode 173 and a drain electrode. It is formed in the protrusion 154 between the (175).

The data line 171 and the drain electrode 175 may include, for example, an upper layer made of a material having excellent physical, chemical, and electrical properties with IZO or ITO, such as titanium, tantalum, chromium, molybdenum (Mo), or an alloy thereof. In order to reduce the delay or voltage drop of the data signal, diffusion of a low resistivity metal, for example, an interlayer film made of an aluminum-based metal such as aluminum (Al) or an aluminum alloy and an aluminum-based metal into the resistive contact member And a bottom film made of a metal to prevent such as titanium, tantalum, chromium, molybdenum or an alloy thereof or the like.

In the embodiment of the present invention, the upper and lower films 171p, 171r, 175p, and 175r are formed of molybdenum, and the intermediate films 171q and 175q are formed of aluminum.

 In FIG. 2, the lower layer, the intermediate layer, and the upper layer of the source electrode 173 are denoted by reference numerals 173p, 173q, and 173r, respectively.

Sides of the data line 171 and the drain electrode 175 are also inclined, and the inclination angle is in the range of about 30-80 ° with respect to the horizontal plane.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance.

The linear semiconductor 151 has substantially the same shape as the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165 thereunder. However, it has a portion exposed between the source electrode 173 and the drain electrode 175, not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 made of an inorganic material such as silicon nitride is formed on the gate line 121, the data line 171, the entire exposed portion of the semiconductor 154, and the drain electrode 175. However, the passivation layer 180 is an organic material having excellent planarization characteristics and photosensitivity, but a-Si: C: O and a-Si: O formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material having a dielectric constant of about 4.0 or less, such as: F, and may have a double film structure of a lower inorganic film and an upper organic film.

The passivation layer 180 may include a plurality of contact holes 181, 182, and 187 exposing an end portion of the gate line 121, an end portion of the data line 171, and a portion 177 of the drain electrode 175, respectively. Has)

A plurality of pixel electrodes 190 made of a transparent conductor or a reflective metal such as IZO, ITO or a-ITO (amorphous ITO) is formed on the passivation layer 180, and contact holes 181 and 182 are formed in the contact holes 181 and 182. A plurality of contact assistants 81 and 82 are formed.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 exposed through the opening 187 to receive a data voltage from the drain electrode 175.

The pixel electrode 190 applied with the data voltage generates an electric field together with a common electrode (not shown) of another display panel (not shown) to which a common voltage is applied, thereby generating liquid crystal molecules of the liquid crystal layer between the two electrodes. Rearrange them.                     

In addition, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain an applied voltage even after the thin film transistor is turned off. There is another capacitor connected in parallel with it, which is called a storage capacitor. 1 to 2B, the storage capacitor is formed by overlapping the pixel electrode 190 and the storage electrode line 131 and overlapping the drain electrode 175 and the storage electrode line 131 connected to the pixel electrode 190. . The extended portion 137 is provided in the storage electrode line 131, so that the overlapped area is large, and there is no protective layer 180 between the pixel electrode 190 and the storage electrode line 131, and only the gate insulating layer 140 exists. The distance between the capacitors is short, so the capacitance of the holding capacitor is large.

In this case, a part 177 of the drain electrode 175 connected to the pixel electrode 190 overlaps the storage electrode line 131 with the gate insulating layer 140 interposed therebetween.

The contact auxiliary members 81 and 82 are connected to the ends of the gate lines 121 and the ends of the data lines 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement the adhesion between the end portion of the gate line 121 and the end portion of the data line 171 and the external device, and do not necessarily serve to protect them. Whether is optional.

Next, a method of manufacturing the thin film transistor array panel illustrated in FIGS. 1 to 2B according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 3 to 11B and FIGS. 1 to 2B.                     

3, 10, and 12 are layout views at an intermediate stage of the method for manufacturing the thin film transistor array panel shown in FIGS. 1 to 2B according to one embodiment of the present invention, respectively, and are arranged in the order of the process. 4A and 4B are cross-sectional views of the thin film transistor array panel of FIG. 3 taken along lines IVa-IVa 'and IVb-IVb', respectively. 5A and 5B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 3 taken along the lines IVa-IVa 'and IVb-IVb', respectively, and are views of the next steps of FIGS. 4A and 4B. 6A and 6B are views in the next steps of FIGS. 5A and 5B, respectively, and FIGS. 7A and 7B are views in the next steps of FIGS. 6A and 6B, respectively, and FIGS. 8A and 8B are respectively FIGS. 7A and 7B. 9A and 9B are views in the next step, respectively. FIGS. 8A and 8B respectively. 11A and 11B are cross-sectional views of the thin film transistor array panel illustrated in FIG. 10 taken along lines XIa-XIa 'and XIb-XIb', respectively, and FIGS. 13A and 13B are thin film transistors illustrated in FIG. 12, respectively. 11A and 11B illustrate cross-sectional views of the display panel taken along lines XIIIa-XIIIa 'and XIIIb-XIIIb'.

First, as shown in FIGS. 3 to 4B, two layers of metal films, that is, a lower metal film of aluminum or an Al-Nd alloy and an upper metal film of molybdenum, are formed on an insulating substrate 110 made of transparent glass. The gate line 121 and the storage electrode line including the plurality of gate electrodes 124 by sequentially stacking the sputtering layer and patterning the upper metal layer and the lower metal layer in a photolithography process using a photoresist pattern (not shown). 131 is formed. Here, the lower metal film preferably has a thickness of about 1,000-3,000 mm 3, and the upper metal film preferably has a thickness of about 500-1,000 mm 3.

The patterning of the top films 121q, 124p and 131q and the bottom films 121p, 124q and 131p is a CH ₃ COOH (acetic acid) / HNO ₃ (nitric acid), an aluminum etchant that can be etched while laterally inclining both aluminum and molybdenum. It is preferred to proceed by wet etching with) / H ₃ PO ₄ (phosphate) / H ₂ O.

In this case, a process of hard baking the photoresist pattern before the wet etching may be omitted, and the wet etching may be a spray mode in which the etching is performed by spraying the etchant.

Next, as shown in FIGS. 5A and 6B, three-layer films of the gate insulating layer 140, the intrinsic amorphous silicon layer 150, and the impurity amorphous silicon layer 160 are sequentially stacked by chemical vapor deposition (CVD), and the like. The photosensitive film 70 is apply | coated on it.

Thereafter, the photosensitive film 70 is irradiated with light through a photomask (not shown) and then developed. The thickness of the developed photosensitive film 70 varies depending on the position. In FIGS. 5A and 5B, the photosensitive film 70 is formed of first to third portions whose thickness becomes smaller. The first part located in the area A (hereinafter referred to as the wiring area) and the second part located in the area B (hereinafter referred to as the channel area) are indicated by reference numerals 72 and 74, respectively. Reference numerals are not given to the third portion located in the region, because the third portion has a thickness of 0, thereby revealing the impurity amorphous silicon layer 170 below. The ratio of the thicknesses of the first portion 72 and the second portion 74 is different depending on the process conditions in the subsequent process, but the thickness of the second portion 74 is 1/2 of the thickness of the first portion 72. It is preferable to set it as follows.

As such, there may be various methods of varying the thickness of the photoresist film according to the position. The transmissive area as well as the light transmitting area and the light blocking area may be provided in the exposure mask. For example. The semi-transmissive region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist film with a conventional mask having only a transmissive area and a light shielding area, and then reflowing so that the photoresist film flows into an area where no photoresist film remains.

Given the appropriate process conditions, the underlying layers may be selectively etched due to the difference in thickness of the photoresist films 72 and 74. Accordingly, a plurality of linear ohmic contacts 161 and a plurality of island resistive contact members 165 each including a plurality of protrusions 163 as shown in FIGS. 6A and 6B through a series of etching steps, and a plurality of A plurality of linear semiconductors 151 including the protrusions 154 are formed.

As the material of the gate insulating film 140, silicon nitride is preferable, and the lamination temperature is preferably 250 to 500 占 폚 and a thickness of about 2,000 to 5,000 Pa.                     

Subsequently, the photoresist layer 40 is coated on the linear and island resistive contact members 161 and 165 and the exposed gate insulating layer 140, and the photomask 50 is aligned thereon. In this case, the photosensitive film 40 is a negative type in which a portion not exposed to light is removed.

The photomask 50 is composed of a transparent substrate 51 and an opaque light shielding layer 52 thereon, the light-transmitting region C having a width of the light shielding layer 52 not less than a predetermined width and a light shielding layer having a predetermined width or more ( 52) with the light shielding area A.

The transmissive region C faces the region surrounded by the gate line 121 and the data line 171 and the end portion of the gate line 121, and the other portion faces the light blocking region A. FIG.

In FIG. 7A and FIG. 7B, the hatched portion is a portion facing the light blocking region A and is not exposed to light, and the remaining portion is a portion that is exposed to light facing the transmission region C.

When the photosensitive film 40 is irradiated with light through the photomask 50 and developed, the photosensitive film portion 41 exposed to the light remains as shown in FIGS. 8A and 8B. As described above, since the photosensitive film 40 is negative, the side surface of the photosensitive film part 41 penetrates inward by exposure, and has a reverse taper shape.

9A and 9B, a conductive film is stacked on the substrate 110 by a sputtering method to form a data line conductive film 700. In this case, the conductive layer 700 may be formed of a triple layer including aluminum, and for example, triple layers of molybdenum (Mo), aluminum (Al), and molybdenum (Mo) (701-703, 701'-703 '). To form.

As such, when molybdenum (Mo) and aluminum (Al) are included, there is an advantage in that patterning is possible in one etching condition.

At this time, the conductive film 700 is composed of a first portion 710 ′ positioned on the photosensitive film portion 41 and a second portion 710 positioned elsewhere, and the side surface of the photosensitive film portion 41 has an inverse taper shape. The first step 710 ′ and the second part 710 of the conductive film 700 are separated from each other at least in part due to the step between the photoresist part 41 and the other parts, thereby forming a gap. The side of 41 is at least partially exposed.

Subsequently, when the substrate 110 is immersed in the photoresist solvent, the solvent penetrates into the photoresist part 41 through the exposed side surface of the remaining photoresist part 41, thereby removing the photoresist part 41. At this time, since the first portion 710 ′ of the conductive film 700 positioned on the remaining photosensitive film portion 41 also falls off together with the photosensitive film portion 41 in a lift-off manner, the conductive film ( Only the triple layers 701, 702, and 703 of the second portion 710 of the 700 remain, and these 701, 702, and 703 are the lower layers 171p and 175p, the intermediate layers 171q and 175q, and the upper layer ( The data line 171 and the drain electrode 175 are formed in correspondence with 171r and 175r (see FIGS. 10 to 11B).

Next, as shown in FIGS. 13A and 13B, the planarization characteristic is excellent and photosensitivity is provided to cover the gate insulating layer 140 and the data line 171 and the drain electrode 175 exposed on the substrate 110. Branched organic material, low dielectric constant insulating material such as a-Si: C: O, a-Si: O: F formed by plasma enhanced chemical vapor deposition (PECVD), or silicon nitride as an inorganic material. A passivation layer 180 is formed.                     

Then, the passivation layer 180 is etched using the photolithography process, and then the passivation layer 180 of the corresponding portion and the gate insulating layer 140 below are sequentially etched to form an end portion of the gate line 121, an end portion of the data line 171, and a drain. A plurality of contact holes 181, 182, and 187 exposing portions of the electrode 175 are formed, respectively.

When the protective film is formed of an organic material having photosensitivity, the contact hole may be formed only by a photographic process.

Lastly, as shown in FIGS. 1 and 2B, IZO and ITO a-ITO films are stacked on the substrate 110 by sputtering, and a plurality of pixel electrodes 190 and the contact assistants 82 are formed by a photolithography process. . In the case of IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu Co., Ltd. can be used as a target, and includes In ₂ O ₃ and ZnO, and zinc occupies about 15 indium and zinc. It is preferably in the range of -20 atomic%. In addition, the sputtering temperature of IZO is preferably 250 ° C. or lower to minimize contact resistance with other conductors.

In the exemplary embodiment of the present invention, the data line 171 and the drain electrode 175 are formed in a lift-off manner after forming the negative photosensitive film, but the gate line 121 as well as the data line 171 and the drain electrode 175 are formed. ) And sustain electrode line 131 can also be formed in the same manner.

As described above, in the present exemplary embodiment, the data line 171 and the drain electrode 175, the ohmic contact members 161 and 165 and the semiconductor 151 formed thereunder are formed in one photo process, and the pixel electrode 190 and A separate photographic process for forming the contact auxiliary member 82 is omitted to simplify the overall process.

In addition, since the side of the photosensitive film portion 41 has a reverse taper shape by using the negative photosensitive film 40, the transparent conductive film located on the photosensitive film portion 41 and the transparent conductive film located on other portions are disconnected and undercut. The lift-off process for the first portion 91 of the transparent conductive film is easily performed without a separate etching process.

As such, in the present embodiment, since the data line 171 and the drain electrode 175 are formed by the negative photosensitive film and the lift-off process, there is no problem such as undercut caused by different etching processes. In addition, since the wiring is formed without an etching process, the selection range for the wiring is widened, so that the wiring can be formed even with a metal having a high non-etching tendency such as lead (Pt), nickel (Ni), or the like.

As described above, according to the present invention, since the data line and the drain electrode are formed by the lift-off process, a poor profile such as an undercut due to different etching conditions is eliminated. As a result, disconnection of the signal line is reduced and stable signal transmission is achieved. In addition, since the wiring is formed without an etching process, the selection range of the selection type is widened. Thus, the wiring can be formed even from a metal having a large non-etching tendency such as lead (Pt), nickel (Ni), or the like.

Furthermore, since the negative photosensitive film having the side of the reverse taper shape is used, a separate process for undercut is not necessary under the photosensitive film, thereby reducing manufacturing time and manufacturing cost.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (10)

Forming a gate line including a gate electrode on the substrate, Forming a gate insulating film on the gate line; Forming a semiconductor layer on the gate insulating film, Forming an ohmic contact on the semiconductor layer, Forming a first photoresist film on the ohmic contact member; Removing a first portion of the first photoresist film, Forming a conductive film on the second portion of the first photosensitive film and the exposed ohmic contact; Removing a second portion of the first photosensitive film to form a data line and a drain electrode; Selectively etching a protective film on the data line and the drain electrode, and Forming a pixel electrode connected to the drain electrode Method of manufacturing a thin film transistor array panel comprising a. In claim 1, The first photosensitive film is a method of manufacturing a thin film transistor array panel of the negative type. In claim 2, The first photoresist film is formed using a photomask having a light blocking region and a transmission region. In claim 2, And the conductive film is formed of an upper film containing molybdenum, an intermediate film containing aluminum, and a lower film containing molybdenum. In claim 2, The gate line may be formed of a lower layer made of aluminum or an aluminum alloy and an upper layer including molybdenum. In claim 1, Selectively etching the passivation layer exposes a portion of the data line and a portion of the drain electrode. In claim 1, The selectively etching the passivation layer may include etching the gate insulating layer together to expose a portion of the gate line. In claim 1, The passivation layer and the gate insulating layer have contact holes exposing an end portion of the gate line and an end portion of the data line, And forming a contact auxiliary member connected to an end portion of the gate line and an end portion of the data line through the contact hole in the pixel electrode forming step. In claim 1 Forming the ohmic contact member, Sequentially depositing a gate insulating film, an intrinsic amorphous silicon layer, and an impurity amorphous silicon layer on the gate line; Forming a second photosensitive film having a different thickness depending on a position on the impurity amorphous silicon layer, and Selectively etching the impurity amorphous silicon layer and the intrinsic amorphous silicon layer using the second photoresist film as a mask to form the ohmic contact member Containing Method of manufacturing a thin film transistor array panel. In claim 9, And the second photosensitive film is formed using an optical mask having a light blocking region, a transflective region, and a transmissive region.

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