KR20050023162A - Method for fabricating a crystalline thin film transistor including a metal offset region - Google Patents

Abstract

PURPOSE: A method of manufacturing a crystalline TFT(Thin Film Transistor) is provided to acquire easily a metal offset region without an additional photoresist mask, to prevent damage of an active layer and to improve a crystalline state of the active layer by implanting a predetermined metal for MILC(Metal Induced Lateral Crystallization) into the active layer using a gate forming mask in an existing state of a gate insulating layer. CONSTITUTION: An amorphous silicon active layer, a gate insulating layer(22) and a gate metal film are sequentially formed on an insulating substrate. A gate electrode(25) is formed by patterning selectively the gate metal film using a mask. At this time, the gate electrode is recessed under the mask. A predetermined metal for MILC is implanted into the active layer by using the mask, so that a metal implanted region is offset from a channel region of the active layer as much as the recessed length of the gate electrode. An ion-implantation is then performed on the active layer. The active layer is crystallized by using a heat treatment.

Description

A method of manufacturing a crystalline thin film transistor including a metal offset region {METHOD FOR FABRICATING A CRYSTALLINE THIN FILM TRANSISTOR INCLUDING A METAL OFFSET REGION}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to thin film transistors (TFTs) used in display devices, such as liquid crystal displays (LCDs) and organic electroluminescent displays (OELDs). The present invention relates to a method of manufacturing a thin film transistor in which an active layer forming a channel is formed of crystalline silicone.

Thin film transistors used in display devices such as LCD and OELD are usually deposited with silicon on a transparent substrate such as glass or quartz, forming a gate insulating layer and a gate electrode, injecting dopants into a source and a drain, and then annealing them. It is composed by forming an active layer after activation. The active layer constituting the source, drain and channel of the thin film transistor is usually formed by depositing a silicon layer on a transparent substrate such as glass using a chemical vapor deposition (CVD) method. However, the silicon layer deposited directly on the substrate by a method such as CVD has a low electron mobility as an amorphous silicon film. As display devices using thin film transistors require fast operation speeds and are miniaturized, the integration degree of the driving IC is increased and the aperture ratio of the pixel area is reduced. Therefore, the driving circuit is formed simultaneously with the pixel TFT by increasing the electron mobility of the silicon film, It is necessary to increase the pixel aperture ratio. For this purpose, a technique is used in which an amorphous silicon layer is heat-treated to crystallize into a crystalline silicon layer having a crystalline structure having high electron mobility.

Various methods have been proposed to crystallize an amorphous silicon layer of a thin film transistor into a crystalline silicon layer. Solid phase crystallization (SPC) is a method of annealing an amorphous silicon layer over several hours to several tens of hours at a temperature of 600 ° C. or less, which is a deformation temperature of glass, which is a material forming a substrate. Since the SPC method requires a long time for heat treatment, the productivity is low, and when the area of the substrate is large, there is a problem that deformation of the substrate may occur because a long heat treatment process is required even at a temperature of 600 ° C. or less. Excimer Laser Crystallization (ELC) is a method in which an excimer laser is injected into a silicon layer to instantaneously crystallize the silicon layer by generating a locally high temperature for a very short time. The ELC method has a technical difficulty in precisely controlling the scanning of the laser light, and since only one substrate can be processed at a time, there is a problem that productivity is lowered than when batch processing of several substrates at the same time in the blast furnace.

In order to overcome the disadvantages of the conventional silicon layer crystallization method, a method of contacting metals such as nickel, gold, and aluminum with amorphous silicon or injecting these metals into silicon is used, which is amorphous even at a low temperature of about 200 ° C. This is to take advantage of the phenomenon that the phase change is induced to silicon crystalline silicon. This phenomenon is called metal induced crystallization (MIC). When a thin film transistor is manufactured using the MIC phenomenon, metal remains in the crystalline silicon constituting the active layer of the thin film transistor, and thus, especially in the channel portion of the thin film transistor. The problem of current leakage occurs.

Recently, metal induced side crystallization (Metal Induced Lateral Crystallization) does not directly induce a phase change of silicon, but the silicide generated by the reaction between metal and silicon continues to propagate to the side as the MIC. A method of crystallizing a silicon layer using a MILC phenomenon has been proposed (see SW Lee & SK Joo, IEEE Electron Device Letter, 17 (4), p. 160, (1996)). Nickel, palladium, cobalt, etc. are known as the metals causing the MILC phenomenon. When the silicon layer is crystallized using the MILC phenomenon, the silicide interface including the metal moves sideways as the phase change of the silicon layer propagates. Therefore, in the silicon layer crystallized using the MILC phenomenon, there is almost no metal component used to induce crystallization, which does not affect the current leakage and other operating characteristics of the transistor activation layer. In addition, in the case of using the MILC phenomenon, it is possible to induce crystallization of silicon at a relatively low temperature of 300 ° C to 600 ° C, and there is an advantage of simultaneously crystallizing a plurality of substrates without damaging the substrate by using a furnace.

1A to 1D are cross-sectional views showing prior art processes for manufacturing a TFT including a crystal chamber silicon active layer using MIC and MILC phenomena. As shown in FIG. 1A, an amorphous silicon layer is deposited on an insulating substrate 10 on which a buffer layer (not shown) is formed, and an active layer 11 is formed by patterning amorphous silicon by photolithography. The gate insulating layer 12 and the gate electrode 13 are formed on the active layer 10 using conventional methods.

As shown in FIG. 1B, the entire insulating substrate 10 is doped with a dopant using the gate electrode 13 as a mask to form the source region 11S, the channel region 11C, and the drain region 11D in the active layer 11. do. Then, as shown in FIG. 1C, the photoresist 14 is formed to cover the gate electrode 12, the source region 11S and the drain region 11D around the gate electrode, and the substrate 10 and the photoresist ( A metal layer 15 is deposited over the entire surface of 14). The metal layer 15 is formed by depositing nickel, palladium, cobalt, or the like to a thickness of 1-10,000 kPa, preferably 10-200 kPa, using a method such as sputtering, heat evaporation, or PECVD.

As shown in FIG. 1D, the photoresist 14 is removed and the entire substrate is annealed at a temperature of 300 ° C. to 700 ° C. so that the source and drain regions 16 immediately below the remaining metal layer 15 are crystallized by MIC. The portion of the source and drain regions where the metal layer 15 is not covered and the channel region 17 under the gate electrode are crystallized by a MILC phenomenon induced from the remaining metal layer 15.

The reason why the photoresist 14 is formed to cover the source and drain regions on both sides of the gate electrode 13 in the prior art shown in FIGS. 1A to 1D is the channel region 11C, the source region 11S, and the channel region. When the metal layer 15 is deposited to the interface between 11C and the drain region 11D, metal components introduced by the MIC phenomenon remain in these interfaces and the channel region 11C, so that current leakage in the channel region 11C may occur. This is because a problem of deteriorating operation characteristics occurs. Therefore, patterning the photoresist wider than the gate electrode to form a metal offset region around the channel region 11C without applying a metal component is essential to the characteristics of the crystalline thin film transistor manufactured by MILC. The metal offset region is usually formed with a width of 0.01 to 5 μm, which is the minimum distance necessary to prevent penetration of the channel region of the metal component, and thus the time required for MILC crystallization of the channel region 11C and the metal offset region to which the metal is not applied. Minimize.

However, the prior art shown in Figs. 1A to 1D has the following problems.

(1) A separate photoresist pattern is used to form metal offset regions around the channel, which increases the number of process steps.

(2) In the conventional process, the MILC induction metal was directly deposited on the surface of the amorphous silicon active layer using a method such as sputtering. To do this, a portion of the gate insulating layer must be removed to expose the silicon layer. The etching of the gate insulating layer not only complicates the process but also may cause a problem that the gate insulating layer is incompletely removed or excessively etched and the active layer is damaged when the etching process is not accurately controlled.

(3) In the conventional metal deposition process, it is difficult to precisely control the amount of metal deposited on the surface of the active layer, so that an excessive amount of metal is deposited on the active layer. Thus only a portion of the deposited metal layer reacts with silicon to induce MILC and most of the metal remains in the metal state. Thus, the remaining metal layer may cause current leakage of the thin film transistor, and there is a problem of greatly reducing the light transmittance of the LCD and OELD screens using the thin film transistor. To prevent this problem, the MILC metal must be removed after the heat treatment process, and other components such as gate electrodes are easily damaged during this process.

(4) In the conventional process, since it is difficult to uniformly control the thickness on which the MILC metal is deposited, there is a problem that the uniformity of the off current characteristic of the TFT becomes unstable depending on the thickness of the deposited metal.

One object of the present invention is to provide a method of forming a metal offset region around a channel region without using a separate photoresist mask in order to solve the above technical problem of the conventional thin film transistor manufacturing method using MILC. .

It is another object of the present invention to provide a method for manufacturing a crystalline thin film transistor using MILC without removing the gate insulating layer. In addition, an object of the present invention is to provide a method for manufacturing a crystalline thin film transistor which can finely control the amount of MILC-derived metal applied to the active layer and does not need to remove the MILC-derived metal after crystallization of the active layer.

A method of manufacturing a thin film transistor according to the present invention includes providing a transparent substrate, forming an amorphous silicon active layer on the substrate, laminating a gate insulating layer and a gate metal layer on the substrate and the silicon active layer, using a mask Patterning a gate metal layer to form a gate electrode, implanting a MILC-derived metal into the active layer using a mask, implanting impurities into the active layer, and heat treating the substrate to crystallize the active layer; By etching the metal layer, a gate electrode is formed in a structure that is undercut inwardly with respect to the mask, and the gate insulating layer is not removed by etching the gate metal layer, and a MILC induction metal is a channel of the active layer under the gate electrode. Offset by a distance from the area It is characterized.

According to another aspect of the present invention, a method of manufacturing a CMOS thin film transistor includes providing a transparent substrate, forming a first active layer and a second active layer of amorphous silicon on the substrate, a gate insulating layer and a gate on the substrate and the silicon active layer Stacking a metal layer, patterning a stacked gate metal layer on each gate active layer using a mask to form a gate electrode, implanting MILC induction metal into the first and second active layers using a mask, and Forming a photoresist on an active layer and injecting impurities of a first conductivity type into a second active layer, forming a photoresist on a second active layer, removing a photoresist on a first active layer, and then removing impurities of a second conductivity type Implanting, and heat treating the substrate to crystallize the first and second active layers, wherein the gate electrode is gated. The metal layer is etched to form an undercut structure inwardly with respect to the mask, and the gate insulating layer is not removed by etching the gate metal layer, and the MILC inducing metal is offset by a predetermined distance from the channel region of the active layer under the gate electrode. It is characterized in that the injection.

Hereinafter, with reference to the accompanying drawings will be described specific embodiments of the present invention.

(First embodiment)

2A to 2J are diagrams illustrating a process of manufacturing a TFT using a MILC phenomenon in accordance with one embodiment of the present invention.

2A is a cross-sectional view of a state in which an amorphous silicon island 21 constituting an active layer of a thin film transistor is formed on a transparent substrate 20 and a gate insulating layer 22 and a gate metal layer 23 are sequentially formed thereon. Substrate 20 is comprised of an insulating material, such as Corning 1737 glass, quartz or silicon oxide, or oxidized silicon wafer. Optionally, a buffer layer (not shown) may be formed on the substrate 20 to prevent diffusion of contaminants from the substrate 20 into the silicon layer 21. The buffer layer may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof using PECVD (Plasma-Enhanced Chemical Vapor Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), or APCVD (Atmosphere). It is formed by deposition to a thickness of 300 to 10,000 Pa, preferably 500 to 3,000 Pa at a temperature of 600 ° C. or lower by using a deposition method such as Pressure Chemical Vapor Deposition) or ECR CVD (Electron Cyclotron Resonance CVD). The amorphous silicon layer 21 is formed by depositing silicon to 100 to 3,000 microns, preferably 500 to 1,000 microns thick using PECVD, LPCVD or sputtering.

The gate insulating layer 22 and the gate metal layer 23 are formed on the silicon island 21. The gate insulating layer 22 may be formed using a deposition method such as PECVD, LPCVD, APCVD, or ECR CVD to form silicon oxide (SiO ₂ ), silicon nitride (SiNx), silicon oxynitride (SiOxNy), or a composite layer thereof in a range of 300 to 3,000 Å. It is preferably formed by deposition to a thickness of 500 to 1,000 mm 3. A conductive material such as a metal material or doped polysilicon on the gate insulating layer 22 may be sputtered, evaporated, PECVD, LPCVD, APCVD, ECR CVD, or the like by using 1,000 to 8,000 Å preferably 2,000. The gate metal layer is deposited to a thickness of 4,000 kHz.

FIG. 2B shows a state in which a photoresist film 24 is formed by depositing and exposing a photoresist film to form a gate electrode on the gate metal layer. 2C shows a state in which the gate electrode 25 is formed by etching the gate metal layer using the photoresist mask 24. The gate electrode is typically patterned by wet etching using an acidic etching solution such as ferric chloride, 1HNO ₃ / 5HCl, 150CH ₃ COOH / 50HNO ₃ / 3HCl, and the gate insulating layer 22 is not removed during the etching process. Only the gate metal layer is selectively etched to form a gate electrode. At this time, the gate metal layer is excessively etched to form an undercut structure under the photoresist mask 24 so that the photoresist pattern extends from the outside of the sidewall of the gate electrode by a predetermined distance "a".

2D shows a process for injecting nickel into an amorphous silicon island using a photoresist mask. Nickel ions are implanted at a concentration of 1E17 to 1E22 / cm ³ at an energy of 10 to 200 KeV using a conventional ion implantation method. In this case, since the width of the photoresist mask 24 is wider than that of the gate electrode 25, a metal offset region in which nickel is not implanted is formed around the channel region under the gate electrode. Accordingly, the present invention has the advantage that a metal offset region can be formed without using an additional mask other than the photoresist mask for patterning the gate electrode. Also, since the mask used for nickel implantation is a mask used to form the gate metal, it is always aligned with the position of the gate electrode, so that the metal offset region can always be formed at the correct position.

According to the present invention, when nickel is injected at an energy of 10 to 200 KeV, nickel ions may pass through the gate insulating layer, and nickel may be injected into the amorphous silicon without removing a part of the gate insulating layer. In addition, 1E17 to 1E22 / cm ³ on the silicon thin film without depositing a large amount of metal layer on the surface of the amorphous silicon with nickel. It was confirmed that even ion implantation at a degree of concentration could sufficiently induce crystallization by MILC of amorphous silicon. Nickel ion etching or gettering process for removing nickel after crystallization of active layer does not occur when the nickel ion is injected into the active layer and the substrate at the concentration applied in the present invention. You do not have to use it. Although nickel has been described as an example of injecting nickel into amorphous silicon as a metal for inducing a MILC phenomenon, a metal such as cobalt (Co), palladium (Pd), titanium (Ti), or the like may be used.

2E shows a process of forming a source region 21S and a drain region 21D by doping impurities into the active layer 21 using a photoresist mask. In manufacturing N-MOS TFTs, dopants such as PH ₃ , P, and As are ion-doped or ion implanted using an energy of 10 to 200 KeV (preferably 30 to 100 KeV) at 1E11 to 1E22 / cm ³ (good). For example, when doping with a dose of 1E15 to 1E21 / cm ³ ) and manufacturing a P-MOS TFT, dopants such as B ₂ H ₆ , B, and BH ₃ may be charged with energy of 1E11 to 1E22 / cm ^{3 at} an energy of 11 to 200 KeV. Doping is carried out with a dose of (preferably 1E14 to 1E21 / cm ³ ). When the impurity doping is completed, the photoresist is removed as shown in FIG. 2F. Although the impurity implantation process of FIG. 2E is described as being performed in this embodiment after nickel implantation, it should be understood that nickel may be implanted after impurity implantation.

Thereafter, as shown in FIG. 2G, low concentration doping is performed to form a low concentration doped region (LDD) region around the channel region. In the case of manufacturing the N-MOS TFT, dopants such as PH ₃ , P, and As are doped with a dose of 1E11-1E20 / cm ³ using an ion shower doping method, an ion implantation method, or other ion implantation method, and P- when manufacturing the MOS TFT is executed by doping a dopant such as _{B 2 H 6, B, BH} 3 in a dose of 1E11-1E20 / cm ^3. In this case, when forming an offset junction region in which impurities are not implanted instead of the LDD region around the channel region, the low concentration doping process may be omitted and the process may directly proceed to the crystallization heat treatment process. As described with reference to FIG. 2E in the doping process of FIG. 2G, when a high concentration of impurities are injected, a conventional thin film transistor having no LDD region or offset junction region may be manufactured.

Thereafter, as shown in FIG. 2H, the heat treatment is performed to crystallize the active layer 21 by MILC and to activate the dopant injected into the source region 21S and the drain region 21D of the active layer 21. This process uses a high-speed annealing (RTA) method which heats for a short time within a few minutes at a temperature of about 700 to 800 Pa using a tungsten-halogen or xenon arc heating lamp, or an ELC method which heats for a very short time using an excimer laser. , A method of using a furnace and the like can be used. In an embodiment of the present invention, the active layer is crystallized using MILC which can crystallize amorphous silicon into crystalline silicon at a temperature of 300 to 700 ° C. lower than RTA. Crystallization of the active layer is preferably carried out in a furnace at a temperature of 300 to 700 ° C. for 0.1 to 50 hours, preferably 0.5 to 20 hours. In the heat treatment process, the silicon of the nickel-implanted portion is crystallized by MIC, and the other portion is crystallized by MILC propagated from the nickel-implanted portion.

After that, according to the conventional method, as shown in FIG. 2I, an interlayer insulating film 26 is formed on the substrate, the active layer, and the gate electrode, and a contact hole 27 is formed in the contact insulating layer so that a part of the source region, the drain region, and the gate are exposed. Form. Subsequently, a thin film transistor is formed by forming a contact electrode and a pixel electrode electrically connecting the source region and the drain region to the outside through the contact hole as shown in FIG. 2J.

(2nd Example)

Hereinafter, an embodiment of fabricating a thin film transistor having no LDD region or an offset junction region formed around the channel region by applying the principles of the present invention will be described. Processes not described separately in this embodiment are to be understood that the same process and process conditions as those applied in the first embodiment are applied.

3A shows a state in which an amorphous silicon island 31, a gate insulating layer 32, a gate metal layer 33 and a photoresist mask 34 are formed on the transparent substrate 30 in the same manner as in the previous embodiment. Subsequently, as shown in FIG. 3B, the gate metal layer is patterned by wet etching to form the gate electrode 35. In this case, as described above, the gate electrode has an undercut structure with respect to the photoresist mask, so that the photoresist mask 34 extends outward by a predetermined distance "a" from the gate electrode.

Next, nickel is implanted into the silicon island using a photoresist as a mask to form a metal offset region around the channel region as shown in FIG. 3C. 3D, the photoresist is removed and ion implantation is performed using an N-type or P-type dopant to form a source region 31S and a drain region 31D in the active layer. In this case, since the gate electrode is used as an impurity doping mask, the LDD region or the offset junction region is not formed around the channel region in direct contact with the region in which the impurity is implanted. While the present embodiment cannot form the LDD region or the offset junction region, the process is simple compared with the process of the first embodiment. Since the pixel transistors of LCD and OELD require low off-current characteristics, it is necessary to form the LDD region, but the driving transistors need not strictly limit the off current. Therefore, this embodiment can be applied to the manufacture of drive region transistors of LCD or OELD.

Thereafter, the thin film transistor is completed in the manner described with reference to FIGS. 2H through 2J.

(Third Embodiment)

Hereinafter, an embodiment of manufacturing a thin film transistor using a gate electrode as a mask instead of a photoresist will be described. Processes not described separately in this embodiment are to be understood that the same process and process conditions as those applied in the first embodiment apply.

4A shows that the silicon active layer 41 and the gate insulating layer 42 are formed on the transparent substrate 40, and the first metal layer 43A and the second metal layer 43B are stacked, and then the photoresist mask 44 is formed. It shows a structure. The first metal layer 43A and the second metal layer 43B are formed of metal having different etching rates with respect to the etchant. A photoresist mask for patterning the gate electrode is formed on the second metal layer.

4B shows a state in which the first metal layer 43A and the second metal layer 43B are etched using the photoresist mask. The first metal layer 43A and the second metal layer 43B are preferably patterned by wet etching using an acidic etching solution. Selecting a metal material such that the first metal layer and the second metal layer have different etching rates with respect to the etchant may allow the first metal layer to be etched faster than the second metal layer to have an undercut structure. In some cases, the second metal layer may be first patterned by anisotropic etching and wet anisotropic etching may be performed on the first metal layer to form a structure as shown in FIG. 4B.

Thereafter, as shown in FIG. 4C, the process of removing the photoresist and ion implanting nickel into the silicon active layer 41 using the second metal layer 43B as a mask is shown. After nickel injection, impurities are implanted into the active layer as shown in FIG. 4D. As described above, the nickel implantation and impurity implantation processes may be reversed. Since the second metal layer is wider than the first metal layer, nickel and impurities are not injected around the channel region of the active layer to form a metal offset region and a lightly doped region.

Thereafter, as shown in FIG. 4E, when the second metal layer is removed and low concentration doping is performed, an LDD region can be formed around the channel region. When the high concentration doping is performed, a thin film transistor having no LDD region is manufactured. In the case where the offset junction region is formed around the channel region, crystallization heat treatment is immediately performed after the impurity is implanted as in FIG. 4C and the process of FIG. 4E is omitted. When the process of Fig. 4E is completed, the thin film transistor is completed by the same process as described with reference to Figs. 2H to 2J of the first embodiment.

(Example 4)

Hereinafter, an embodiment of manufacturing a CMOS TFT by applying the present invention will be described.

In this embodiment, as shown in FIG. 5A, a pair of amorphous silicon active layers 51A and 51B are formed on the transparent substrate 50, and the gate insulating layer 52 and the gate metal layer 53 are formed thereon, and then the left and right transistors are formed. Photoresist masks 54A and 54B are formed at positions where gate electrodes are to be formed in the region, respectively. As shown in FIG. 5B, the gate metal layers 53 are patterned by an acidic etching solution to form gate electrodes 53A and 53B. At this time, the gate metal layers are excessively etched with respect to the photoresist mask to form a structure that is undercut by a certain distance “a”. do.

After patterning the gate electrode, nickel is implanted into the left and right silicon active layers (FIG. 5C) and the photoresist is removed (FIG. 5D). Thereafter, as shown in Fig. 5E, impurities are implanted into the other transistor while the one transistor is covered with the photoresist. 5E shows an embodiment in which a high concentration of P-type impurities are injected into the right transistor while the left transistor is covered with a photoresist to form a P-type TFT on the right side. Thereafter, as shown in FIG. 5F, the N-type impurity is implanted while the right transistor is covered with the photoresist and the left photoresist is removed. Then, the substrate is heat-treated in a state where the photoresist is removed as shown in FIG. 5G to simultaneously crystallize the left and right silicon active layers by MILC. Thereafter, the CMOS thin film transistor is completed by using the same conventional process as in the previous embodiment.

According to this embodiment, crystalline CMOS TFTs in which metal offset regions are formed in both the P-MOS and the N-MOS and the LDD region or the offset junction is not formed can be manufactured using the smallest number of processes. This type of CMOS TFT can be suitably used for driving transistors that require better on-current characteristics and faster operating speed than pixel transistors with low off-current tolerance in LCDs and OELDs.

(Example 5)

Hereinafter, another embodiment of manufacturing a CMOS TFT by applying the present invention will be described.

Referring to FIG. 6A, two amorphous silicon islands 61A and 61B for fabricating a CMOS TFT are formed on a substrate 60, and a gate insulating layer 62 and a gate metal layer 63 are formed thereon. A photoresist is formed on the gate metal layer. The photoresist 64A on the left side of the drawing is patterned in the form of a mask for etching the gate electrode of the left transistor. On the other hand, the photoresist 64B on the right side of the figure is formed to cover all of the right transistor regions. When the gate metal layer is etched by wet etching using an acidic etchant, the gate metal layer under the left photoresist 64A is etched as shown in FIG. 6B to form the gate electrode 63A. At this time, the gate metal layer is excessively etched to form an undercut structure having a distance "a" into the photoresist mask. On the right side, the gate metal layer is protected by the photoresist 64B so that no etching occurs.

Thereafter, nickel and impurities are implanted into the left silicon active layer using a photoresist as a mask as shown in FIG. 6C. At this time, since the width of the photoresist mast is larger than the width of the gate electrode, that is, the channel region, metal offset regions and undoped regions are formed around the channel region. In this embodiment, an N-type impurity such as P is implanted into the active layer on the left side to fabricate a CMOS TFT in which a P-type TFT is formed on the right side of the N-type TFT. The order of the process of injecting nickel and impurities may be reversed. When the nickel and impurity implantation is completed, the photoresist is removed from the entire substrate as shown in FIG. 6D and lightly doped. The photoresist can be easily removed by the lift-off method or by an etchant such as a hydrogen fluoride solution or carbon fluoride. When low concentration doping is performed after the photoresist removal, a low concentration doping region is formed around the channel region of the active layer of the left transistor. If the low concentration doping process is omitted, the left transistor forms an offset junction. Since the active layer on the right side is covered by the gate metal layer, impurities are not injected.

Thereafter, as shown in Fig. 6E, the entire left transistor is covered with the photoresist 64C and the photoresist mask 64D is patterned on the gate metal layer on the right active layer. As shown in FIG. 6F, the gate metal layer is etched in the undercut structure using a photoresist mask to form the gate electrode 63B. Then, nickel is implanted into the active layer using a photoresist mask. In this case, since the width of the photoresist is wider than the panned gate electrode, a metal offset region is formed around the channel region of the right transistor active layer.

After nickel injection, the photoresist is processed by ashing as shown in FIG. 6G to adjust the width of the photoresist to be similar to the width of the gate electrode, and to inject P-type impurities in high concentration so that the source region and A drain region is formed. In addition, when the P-type impurities are injected at a high concentration before or after the nickel injection in the state as shown in FIG. 6F, and the P-type impurities are injected at a low concentration in the process of FIG. have.

Thereafter, as shown in FIG. 6H, when the photoresist is removed and heat treatment is performed, crystallization is performed by nickel injected into the active layers of the left and right thin film transistors. After that, an crystalline CMOS thin film transistor is completed by forming an interlayer insulating film, contact hole, contact electrode, pixel electrode, or the like by a conventional process.

Although the content of the present invention has been described by way of examples, the embodiments of the present invention are merely illustrative of the present invention and should not be construed as limiting the scope of the present invention. Those skilled in the art to which the present invention pertains may modify or alter the present invention in various forms within the principles and scope described in the claims herein.

The present invention uses a method of ion implantation without depositing a metal such as nickel in MILC-induced silicon active layer, it is possible to metal injection without removing the gate insulating layer. Therefore, the problem of damage to the silicon active layer when the gate insulating layer is removed can be prevented. In addition, the present invention can form a metal offset region around the channel region without using a separate mask in addition to the photoresist mask used to form the gate electrode, and separately from the MILC induction metal layer because the metal layer does not remain after crystallization of the active layer There is an advantage that does not need to be removed. In addition, the method of the present invention can more uniformly control the concentration of the metal in the active layer than the conventional deposition process can maintain a more uniform operating characteristics of the thin film transistor to be manufactured.

1A-1D illustrate prior art fabrication of crystalline silicon thin film transistors using the MILC phenomenon.

2A to 2J are sectional views showing a process of manufacturing a crystalline silicon thin film transistor according to the first embodiment of the present invention.

3A to 3D are cross-sectional views illustrating a process of manufacturing a crystalline silicon thin film transistor according to the second embodiment of the present invention.

4A to 4E are cross-sectional views illustrating a process of manufacturing a crystalline silicon thin film transistor according to a third embodiment of the present invention.

5A through 5G are cross-sectional views illustrating a process of manufacturing a crystalline silicon thin film transistor according to a fourth embodiment of the present invention.

6A to 6H are cross-sectional views showing a process of manufacturing a crystalline silicon thin film transistor according to the fifth embodiment of the present invention.

Claims (10)

Providing an insulating substrate; Forming an amorphous silicon active layer on the substrate; Stacking a gate insulating layer and a gate metal layer on the substrate and the silicon active layer; Patterning the gate metal layer using a mask to form a gate electrode; Injecting a MILC inducing metal into the active layer using the mask; Injecting impurities into the active layer; And In the method of manufacturing a crystalline silicon thin film transistor comprising the step of heat-treating the substrate to crystallize the active layer, The gate electrode is formed to have a structure in which the gate metal layer is etched and undercut inwardly with respect to the mask, and the gate insulating layer is not removed by etching the gate metal layer, and the MILC induction metal is formed in the gate electrode. The crystalline silicon thin film transistor manufacturing method, characterized in that the implant is offset by a predetermined distance from the channel region of the lower active layer. The method of claim 1, wherein the implanting of the impurity comprises performing high concentration doping without removing the mask and low concentration doping with removing the mask to form a low concentration doping region around the channel region. A crystalline silicon thin film transistor manufacturing method. The method of claim 1, wherein the gate metal layer is formed of two different metal layers, and the MILC inducing metal and the impurities are injected into the active layer using a patterned metal layer having a wide pattern among the gate metal layers. Method for manufacturing crystalline silicon thin film transistor. A method according to any one of claims 1 to 3, wherein the mask is formed using a photoresist. 4. The method of any one of claims 1 to 3, wherein the gate metal layer is wet etched using an acidic etchant. 4. The crystalline material of claim 1, wherein the MILC derived metal comprises one of nickel, cobalt, palladium and titanium and is injected into the active layer at a concentration of 1E17 to 1E22 / cm ³ . Silicon thin film transistor manufacturing method. Providing an insulating substrate; Forming a first active layer and a second active layer of amorphous silicon on the substrate; Stacking a gate insulating layer and a gate metal layer on the substrate and the silicon active layer; Patterning a gate metal layer deposited on each of the gate active layers using a mask to form a gate electrode; Implanting a MILC inducing metal into the first and second active layers using the mask; Forming a photoresist on the first active layer and implanting impurities of a first conductivity type into the second active layer; Forming a photoresist on the second active layer, removing the photoresist on the first active layer, and then implanting impurities of a second conductivity type; And In the method of manufacturing a crystalline silicon CMOS thin film transistor comprising the step of heat-treating the substrate to crystallize the first and second active layer, The gate electrode is formed to have a structure in which the gate metal layer is etched and undercut inwardly with respect to the mask, and the gate insulating layer is not removed by etching the gate metal layer, and the MILC induction metal is formed in the gate electrode. A method of manufacturing a crystalline silicon CMOS thin film transistor, characterized in that the implant is offset by a predetermined distance from the channel region of the lower active layer. 8. The photovoltaic display device of claim 7, wherein after the gate electrode patterning, the MILC-induced metal implantation, and the impurity implantation are completed for the second active layer while the entire first active layer is covered with the photoresist, the photoresist is entirely covered with the photoresist. Using a resist mask to pattern a gate metal layer on the first active layer, implant a MILC inducing metal, ash the photoresist mask, and implant impurities into the first active layer Thin film transistor manufacturing method. Insulating substrate; A crystalline silicon active layer formed on the insulating substrate; A gate insulating layer formed to cover the entire silicon active layer; And A gate electrode formed on the gate insulating layer, The silicon active layer is crystallized by injecting a MILC induction metal into amorphous silicon through the gate insulating layer and heat treatment, the crystalline silicon thin film transistor, characterized in that the MILC induction metal is injected a predetermined distance away from the channel region of the silicon active layer . 10. The crystalline material of claim 9, wherein the MILC induction metal is implanted spaced apart from the channel region of the active layer using a mask used to form the gate electrode or a gate electrode patterned by the mask as a mask. Silicon thin film transistor.