KR20050003047A - Capacitor in ferroelcetric random access memory and method for fabricating the same - Google Patents

Abstract

PURPOSE: A capacitor of a ferroelectric memory device and a manufacturing method thereof are provided to improve contact resistance between a storage node contact and a lower electrode by forming a conductive oxide layer on the storage node contact. CONSTITUTION: An interlayer dielectric(34) is formed on a semiconductor substrate having a junction region(33). A storage node contact is formed to connect the junction region through the interlayer dielectric, wherein the storage node contact has the stack structure of a recessed plug(35a), an oxide barrier layer(36a) and a conductive oxide layer(37) as a diffusion barrier in a storage node contact hole. A lower electrode(38) is formed on the storage node contact. A ferroelectric film(40) and an upper electrode(41) are sequentially formed on the lower electrode.

Description

Capacitor for ferroelectric memory device and manufacturing method thereof {CAPACITOR IN FERROELCETRIC RANDOM ACCESS MEMORY AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly to a method of manufacturing a ferroelectric memory device.

In general, by using a ferroelectric thin film in a ferroelectric capacitor in a semiconductor memory device, the development of a device capable of using a large-capacity memory while overcoming the limitation of refresh required in a DRAM (Dynamic Random Access Memory) device is in progress. come. A ferroelectric random access memory device (hereinafter referred to as 'FeRAM') device using the ferroelectric thin film is a nonvolatile memory device, which has an advantage of storing stored information even when power is cut off. In addition, the operating speed is comparable to DRAM, and is becoming the next generation memory device.

Recently, a merged top electrode plateline (MTP) structure is applied to fabricate a high density ferroelectric memory device.

1 is a device cross-sectional view showing a ferroelectric memory device according to the prior art.

Referring to FIG. 1, an isolation layer 12 defining an active region is formed on a semiconductor substrate 11, and a gate oxide layer 13 and a gate electrode 14 are stacked on a selected surface of the semiconductor substrate 11. Source / drain 15a and 15b of the transistor are formed in the semiconductor substrate 11 on both sides of the gate electrode 14.

A first interlayer insulating film ILD 16 is formed on the semiconductor substrate 11, and a bit line contact 17 penetrating through the first interlayer insulating film 16 and contacting one source / drain 15a is formed. The bit line 18, which is connected to the bit line contact 17, is formed on the first interlayer insulating layer 16.

Then, a second interlayer insulating film 19 is formed on the first interlayer insulating film 16 including the bit line 18, and the second interlayer insulating film 19 and the first interlayer insulating film 16 are simultaneously etched to form the other source. The storage node contact is buried in the storage node contact hole where the drain 15b is exposed. Here, the storage node contact is a film laminated in the order of the polysilicon plug 20, the titanium silicide 21, and the titanium nitride 22. Here, the titanium nitride 22 is a diffusion barrier film that prevents the mutual diffusion between the polysilicon plug 20 and the lower electrode 23.

The lower electrode 23 of the ferroelectric capacitor connected to the storage node contact is formed on the second interlayer insulating layer 19, and the ferroelectric layer 24 covering the entire semiconductor substrate 11 on the lower electrode 23 is formed. Is formed, and the upper electrode 25 is formed on the ferroelectric film 24. Here, the lower electrode 23 is isolated from the neighboring lower electrode by the third interlayer insulating film 26.

In the prior art as shown in FIG. 1, only the lower electrode 23 is patterned in advance in order to minimize the area of the capacitor. Then, the third interlayer insulating layer 26 is deposited and planarized, and the ferroelectric layer 24 and the upper electrode 25 are formed. Is deposited successively, and the ferroelectric capacitor is formed by a series of methods for patterning the upper electrode 25 and the ferroelectric film 24.

In the above conventional technique, after depositing the ferroelectric layer 24 to improve the electrical characteristics of the ferroelectric layer 24, and then depositing the upper electrode 25, the contact hole etching for connecting the upper electrode 25 to the circuit electrically After that, a high temperature heat treatment step is performed. At this time, the heat treatment process is heat treated with nitrogen, argon or oxygen atmosphere using a furnace (Rapid) or Rapid Thermal Process (RTP) at a temperature of 500 ℃ to 800 ℃.

However, in the prior art, in particular, when a subsequent heat treatment process is performed in an oxygen atmosphere, the interfacial characteristics between the storage node contact and the lower electrode are degraded due to the diffusion of oxygen, so that the titanium nitride 22, which is the uppermost layer of the storage node contact, becomes Easily oxidized, there is a problem that the contact resistance increases. This has a fatal effect on the operation of the device, and in order to avoid this, the heat treatment or heat treatment of the oxygen atmosphere is performed in an inert gas atmosphere where the heat treatment effect is inferior, but at a low temperature instead of a sufficient temperature. There is a problem in that the deteriorated electrical characteristics of the process cannot be fully recovered.

The present invention has been made to solve the above problems of the prior art, and a capacitor and a method of manufacturing the ferroelectric memory device that can prevent the top layer of the storage node contact in contact with the lower electrode during the subsequent heat treatment process. The purpose is to provide.

1 is a device cross-sectional view showing a ferroelectric memory device according to the prior art;

2 is a cross-sectional view showing a capacitor of a ferroelectric memory device according to an embodiment of the present invention;

3A to 3E are cross-sectional views illustrating a method of manufacturing a capacitor of a ferroelectric memory device according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 device isolation film

33: junction region 34: first interlayer insulating film

35a: plug 36a: oxide barrier film

37 diffusion barrier film 38 lower electrode

39: second interlayer insulating film 40: ferroelectric film

41: upper electrode

The capacitor of the ferroelectric memory device of the present invention for achieving the above object is a storage node contact connected to the semiconductor substrate through the semiconductor substrate, the interlayer insulating film formed on the semiconductor substrate, the interlayer insulating film and at least the top layer is a conductive oxide film, A lower electrode on the interlayer insulating layer connected to the storage node contact, and a ferroelectric layer and an upper electrode stacked on the lower electrode, wherein the storage node contact is a polysilicon film or a tungsten ten film plug; A layered film laminated in the order of the oxide barrier film on the plug and the conductive oxide film, wherein the conductive oxide film is a ruthenium oxide film or an iridium oxide film, and the oxide barrier film is a ruthenium film or an iridium film.

The method of manufacturing a capacitor of the ferroelectric memory device of the present invention includes forming an interlayer dielectric layer on the semiconductor substrate, forming a storage node contact hole to expose a portion of the semiconductor substrate by etching the interlayer dielectric layer, and the storage node. Filling a storage node contact in which at least a top layer is a conductive oxide film in a contact hole, forming a lower electrode connected to the storage node contact on the interlayer insulating layer, and sequentially forming a ferroelectric layer and an upper electrode on the lower electrode The filling of the storage node contact may include forming a plug partially filling the storage node contact hole, and forming an oxide barrier layer having a thickness partially filling the storage node contact hole. And the oxide barrier film And forming the conductive oxide film having a thickness completely filling the storage node contact hole in a portion, wherein the plug and the oxide barrier film are formed through a blanket etch back, and the conductive oxide film is a blanket etch back. It is characterized by forming through chemical mechanical polishing.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2 is a cross-sectional view illustrating a capacitor structure of a ferroelectric memory device according to an embodiment of the present invention.

As shown in FIG. 2, the junction region 33 is formed in the semiconductor substrate 31 in which the active region is defined by the device isolation layer 32, and the first interlayer insulating layer 34 is formed on the semiconductor substrate 31. The storage node contact is formed in the storage node contact hole that passes through the first interlayer insulating layer 34. Here, the storage node contacts are stacked in the order of the plug 35a, the oxide barrier film 36a, and the diffusion barrier film 37. Detailed description will be described later.

In addition, a lower electrode 38 connected to the storage node contact is formed on the first interlayer insulating layer 34, and the lower electrode 38 is formed so as to surround the second interlayer insulating layer 39. ) And the ferroelectric film 40 and the upper electrode 41 are sequentially formed on the second interlayer insulating film 39.

In Fig. 2, the plug 35a constituting the storage node contact is polysilicon or tungsten, the oxide barrier film 36a is ruthenium or iridium, and the diffusion barrier film 37 is a conductive oxide film of a ruthenium oxide film or an iridium oxide film. That is, the oxide barrier film 36a inserted between the plug 35a made of a material that is easily oxidized and the diffusion barrier film 37 made of the conductive oxide film is made of a metal component (ruthenium or iridium) of the diffusion barrier film 37. .

As described above, the diffusion barrier layer 37 of the present invention is a conductive oxide layer, unlike the prior art in which the diffusion barrier layer 37 for preventing mutual diffusion between the plug 35a and the lower electrode 38 is titanium nitride (TiN). When the conductive oxide film is used as the diffusion barrier film 37, the diffusion barrier film 37 is prevented from being oxidized even when oxygen diffuses during the subsequent heat treatment process. That is, the path | route which the oxygen which the diffusion barrier film 37 diffuses diffuses into the plug 35a is interrupted | blocked. In addition, in order to prevent the plug 35a from being oxidized when the diffusion barrier film 37 is formed, the conductive barrier film 37 is conductive to the diffusion barrier film 37 by using a metal component constituting the diffusion barrier film 37 as the oxide barrier film 36a. When the oxide film is formed, the plug 35a is prevented from being oxidized.

3A to 3E are cross-sectional views illustrating a method of manufacturing a capacitor of a ferroelectric memory device according to an embodiment of the present invention.

As shown in FIG. 3A, an isolation region 32 is formed on the semiconductor substrate 31 to form an isolation region, thereby defining an active region, and a junction such as a source / drain of a transistor in the active region of the semiconductor substrate 31. The region 33 is formed.

Next, after depositing and planarizing the first interlayer dielectric layer 34 on the semiconductor substrate 31, the first interlayer dielectric layer 34 is etched with a contact mask (not shown) to expose the junction region 33. Node contact holes (not shown) are formed. Here, the first interlayer insulating film 34 has a multilayer structure as an interlayer insulating film after being formed up to a bit line as in the prior art of FIG.

Next, the first conductive layer 36 is deposited on the first interlayer insulating layer 34 until the storage node contact hole (not shown) is filled, and then the first interlayer insulating layer 34 is exposed until the surface of the first interlayer insulating layer 34 is exposed. The conductive film 35 is chemically polished and planarized. At this time, the first conductive film 35 is a polysilicon film or a tungsten film.

As shown in FIG. 3B, the first conductive film 35 having the chemical mechanical polishing process completed is blanket etched back. In this case, the blanket etch back process is performed so as to be turned off by a predetermined depth below the surface of the first interlayer insulating film 34, that is, until it is recessed. Herein, the recess depth is determined in consideration of a subsequent process and the like, and is preferably about 500 Pa to 1500 Pa.

Through the above-described series of chemical mechanical polishing and bling-cat etch back processes, a plug 35a partially filling the storage node contact hole is formed. That is, the plug 35a is a polysilicon plug or a tungsten plug.

Next, the second conductive film 36 is deposited on the first interlayer insulating film 34 until the top of the recessed plug 35a structure is filled. In this case, the second conductive layer 36 is ruthenium (Ru) or iridium (Ir).

As shown in FIG. 3C, the second conductive film 36 is blanket etched back to leave the second conductive film 36a only on the recessed plug 35a. At this time, the blanket conductive back is also formed so that the second conductive layer 36a has a recessed shape which is turned off below the surface of the first interlayer insulating layer 34, and thus the storage is still performed after the blanket conductive back of the second conductive layer 36 is formed. The node contact hole is not completely filled.

The second conductive film 36a recessed by the above series of blanket etch backs serves as an oxide barrier film to prevent the subsequent conductive oxide film from directly contacting the plug 35a to oxidize the interface. Hereinafter, the recessed second conductive film 36a is abbreviated as 'oxidation barrier film 36a'.

As shown in FIG. 3D, the conductive oxide film 37 is deposited on the first interlayer insulating film 34 until the upper portion of the oxide barrier film 36a is filled. In this case, the conductive oxide film 37 is an iridium oxide film (IrO ₂ ) or a ruthenium oxide film (RuO ₂ ).

Subsequently, the conductive oxide film 37 is etched back into the blanket. At this time, the blanket etch back does not recess differently from the recessed oxide barrier film 36a or the plug 35a until it reaches the same height as the surface of the first interlayer insulating film 34.

The conductive oxide film 37 filling the top of the storage node contact hole by the series of blanket etch backs as described above serves as a diffusion barrier film that prevents interdiffusion between the plug 35a and the lower electrode of the subsequent ferroelectric capacitor. Hereinafter, the conductive oxide film 37 is abbreviated as 'diffusion barrier film 37'.

As shown in FIG. 3E, after depositing the third conductive film to be the lower electrode on the diffusion barrier layer 37 and the first interlayer insulating layer 34, the lower electrode 38 is formed through a mask and an etching process. .

In this case, the lower electrode 38 is deposited by using a deposition method selected from chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and plasma atomic layer deposition (PEALD), and platinum (Pt). ), Iridium (Ir), ruthenium (Ru), rhenium (Re) and rhodium (Rh) is selected from one or use a composite structure thereof. For example, the lower electrode 38 may be Pt / IrO ₂ / Ir stacked in the order of iridium (Ir), iridium oxide (IrO ₂ ), and platinum (Pt), or ruthenium (Ru) and ruthenium oxide (RuO ₂ ). And Pt / RuO ₂ / Ru laminated in the order of platinum (Pt).

Next, the second interlayer insulating film 39 is deposited on the entire surface including the lower electrode 38, and then chemically polished and planarized until the surface of the lower electrode 38 is exposed. Accordingly, the lower electrode 38 has a form surrounded by the second interlayer insulating layer 39 while being separated from each other by the second interlayer insulating layer 39.

Next, the ferroelectric film 40 and the upper electrode 41 are sequentially formed on the lower electrode 38 and the second interlayer insulating film 39. At this time, the ferroelectric film is formed in the entire cell region, and the ferroelectric film is patterned only without patterning the upper electrode.

Here, the ferroelectric film 40 is deposited using a deposition method selected from chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic deposition (MOD), and spin coating (Spin coating), the conventional SBT , One selected from PZT and BLT, or one selected from SBT, PZT, SBTN, and BLT in which impurities are added or compositionally changed. After the ferroelectric film 40 is formed, heat treatment for crystallizing the ferroelectric film 40 is performed by a known technique, and the ferroelectric film 40 is formed on the structure in which the lower electrode 38 is embedded. 41) Flattening prior to formation can facilitate a flat structure with subsequent processing. Meanwhile, the upper electrode 41 may select and use a material applied as the lower electrode 38.

According to the embodiment described above, the storage node contact of the present invention has a structure in which the plug 35a, the oxide barrier film 36a, and the diffusion barrier film 37 are stacked in the order of the plug 35a and the lower electrode 38. The diffusion barrier film 37 which prevents interdiffusion between the two layers is a conductive oxide film such as an iridium oxide film or a ruthenium oxide film.

The oxide barrier film 36a inserted between the plug 35a and the diffusion barrier film 37 is made of a metal component (ruthenium or iridium) of the conductive oxide film constituting the diffusion barrier film 37. This is to prevent oxidation of the plug 35a by forming the conductive oxide film as the barrier film 37.

As a result, the present invention forms a diffusion barrier film, which is the uppermost layer of the storage node contact, located under the lower electrode to form a conductive oxide film so as to sufficiently increase the heat treatment temperature in an oxygen atmosphere for crystallization of ferroelectric film and recovery of electrical characteristics after subsequent processing. In addition, an increase in contact resistance due to oxidation at the interface between the storage node contact and the lower electrode is suppressed.

In the above embodiment, the diffusion barrier layer 37 is formed through a blanket etch back. Alternatively, the diffusion barrier layer 37 may be formed by chemical mechanical polishing.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention can stably secure the contact resistance of the lower electrode during the manufacturing process of the high density ferroelectric memory device, thereby improving the manufacturing yield and characteristics of the device.

Claims (11)

Semiconductor substrates; An interlayer insulating film formed on the semiconductor substrate; A storage node contact penetrating through the interlayer insulating film and connected to the semiconductor substrate, and at least a top layer being a conductive oxide film; A lower electrode on the interlayer insulating layer connected to the storage node contact; And Ferroelectric film and upper electrode stacked on the lower electrode Capacitor of ferroelectric memory device comprising a. The method of claim 1, The storage node contact, The capacitor of the ferroelectric memory device, characterized in that the laminated film laminated in the order of the plug in contact with the semiconductor substrate, the oxide barrier film on the plug and the conductive oxide film. The method of claim 2, The conductive oxide film is a metal oxide film containing a metal component, the oxide barrier film is a capacitor of a ferroelectric memory device, characterized in that the metal film made of a metal component of the metal oxide film. The method of claim 3, And the metal oxide film is a ruthenium oxide film or an iridium oxide film, and the metal film is a ruthenium film or an iridium film. The method of claim 2, The plug is a capacitor of a ferroelectric memory device, characterized in that the polysilicon film or tungsten film. Forming an interlayer insulating film on the semiconductor substrate; Etching the interlayer insulating layer to form a storage node contact hole exposing a portion of the semiconductor substrate; Filling a storage node contact in the storage node contact hole, wherein at least a top layer is a conductive oxide film; Forming a lower electrode connected to the storage node contact on the interlayer insulating layer; And Sequentially forming a ferroelectric film and an upper electrode on the lower electrode Capacitor manufacturing method of the ferroelectric memory device comprising a. The method of claim 6, Filling the storage node contact, Forming a plug partially filling the storage node contact hole; Forming an oxide barrier film having a thickness partially filling the storage node contact hole on the plug; And Forming the conductive oxide layer having a thickness filling the storage node contact hole completely on the oxide barrier layer; Capacitor manufacturing method of a ferroelectric memory device comprising a. The method of claim 7, wherein And the plug and the oxide barrier film are formed through a blanket etch back. The method of claim 7, wherein The conductive oxide film is a capacitor manufacturing method of the ferroelectric memory device, characterized in that formed through the blanket etch back or chemical mechanical polishing. The method according to claim 7, The conductive oxide film is a metal oxide film containing a metal component, the oxide barrier film is a capacitor manufacturing method of a ferroelectric memory device, characterized in that the metal film made of a metal component of the metal oxide film. The method of claim 10, And the metal oxide film is a ruthenium oxide film or an iridium oxide film, and the metal film is a ruthenium film or an iridium film.