KR20050002785A - An area-efficient charge pump circuit for system-on-glass - Google Patents

Abstract

PURPOSE: A small area charge pump circuit for a system on glass(SoG) is provided to reduce the area of the system on glass by reducing the area occupied by the charge pump circuit without increasing a frequency restricted in a polysilicon thin film transistor or the area of a filtering capacitor. CONSTITUTION: According to a ripple reduction circuit of a charge pump circuit for a system on glass(SoG), an input port(330) inputs a boosting voltage. An output port(340) outputs a pumped voltage. N clock ports((320-1) - (320-n)) input a pair of a clock signal and an inverted clock signal. N-pumping circuits((310-1) - (310-n)) are connected to the input port and the output port in parallel, and are connected to n clock ports one to one. And The N-pumping circuits are driven by the clock signal and the inverted clock signal of the clock port, and generate an output voltage by pumping the boosting voltage.

Description

An area-efficient charge pump circuit for system-on-glass

TECHNICAL FIELD The present invention relates to semiconductor circuits, and more particularly, to a ripple reduction circuit and a charge pump circuit of a charge pump for system-on-glass.

As the advanced digital information communication era enters, new technologies are required to realize lightweight, thin and integrated electronic information systems. In order to satisfy these demands, a lot of researches are being actively conducted as a system-on-glass technology that integrates all component functions on a single substrate. System on glass is the integration of various kinds of functional elements and circuits such as voice, display, information processing, storage space, input / output, communication circuits, etc. on a glass substrate.

A representative example of system on glass technology is a TFT-LCD (thin film transistor liguid crystal display). In general, when TFT-LCD is implemented using a-Si (amorphous silicon) thin film transistor, the resolution and response speed are too low and power consumption is high due to the limitation of the electrical and optical properties of the amorphous thin film. Thus, since the driving circuit is externally mounted and connected by a tape automated bonding (TAB) method, there is a problem that the volume and price of the entire TFT-LCD are increased. However, the poly-Si thin film transistor integrates the driving circuit on the panel, that is, the glass, thus eliminating the need for the connection line between the panel and the driver IC. Thus, the defect rate and reliability of the TFT-LCD can be greatly improved. The use of silicon thin film transistors is increasing.

As the resolution increases and the panel increases due to the use of the polycrystalline silicon thin film transistor, power consumption of peripheral circuits for driving the panel increases. In other words, the power to be supplied by the DC-DC conversion circuit is increased, which causes a large output ripple voltage. There are two ways to reduce this ripple voltage: increasing the charge pump circuit's frequency or increasing the filtering capacitor. However, due to the limitation of the operating frequency according to the mobility of the polycrystalline silicon thin film transistor, it is inevitable to increase the filtering capacitor. At this time, as the size of the capacitor increases, the area occupied by the chip also increases, and the increase of the filtering capacitor causes a problem of increasing the cost and limiting the area of other peripheral circuits.

Accordingly, in order to solve the above problems, it is an object of the present invention to reduce the area occupied by the charge pump circuit in the panel without increasing the frequency limited in the polycrystalline silicon thin film transistor or increasing the area of the filtering capacitor. The goal is to reduce the total area of the glass.

Another object of the present invention is to reduce the magnitude of the ripple voltage and to stably supply the output voltage to the system by using a charge pump circuit to which multi-phase clocking is applied.

Another object of the present invention is to enable a charge pump circuit to which multi-phase clocking is applied to a large screen and a high resolution polycrystalline silicon thin film transistor.

1 is a structural diagram showing a Dickson charge pump circuit according to the prior art,

2 is a structural diagram showing a cross coupled charge pump circuit according to the prior art;

3 is a structural diagram showing a ripple reduction circuit of a charge pump applying multi-phase clocking to a cross coupling structure according to the present invention;

4 is a structural diagram showing a ripple reduction circuit of a charge pump applying 4-phase clocking to a cross coupling structure according to an embodiment of the present invention;

5 is a structural diagram showing a ripple reduction circuit of a charge pump applying 6-phase clocking to a cross coupling structure according to another embodiment of the present invention;

6 is a structural diagram showing a boosted portion of a charge pump circuit applying multi-phase clocking to a cross coupling structure according to the present invention;

7 is a graph illustrating a ripple voltage with time for each of the charge pump circuit according to the prior art and the ripple reduction circuit of the charge pump according to the preferred embodiment of the present invention;

8 is a graph illustrating a ripple voltage according to the size of a filtering capacitor for each charge pump circuit according to the related art and a ripple reduction circuit of the charge pump according to the preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

210: pumping circuit

220: clock stage

310-1, 310-2, 310-n: pumping circuit

320-1, 320-2, 320-n: Clock stage

610-1, 610-2, 610-m: boost circuit

620-1, 620-2, 620-m: Step-up clock stage

211, 311-1, 311-2, 311-n, 611-1, 611-2, 611-m: Basic pump

212, 312-1, 312-2, 312-n, 612-1, 612-2, 612-m: inverting pump

230: basic input stage 240: boost output stage

330: input terminal 340: output terminal

410, 510, 600: ripple reduction circuit

In order to achieve the above objects, according to an aspect of the present invention, an input terminal for inputting a boosted voltage, an output terminal for outputting a pumped voltage, n (n> 1) clock stages for inputting a pair of a clock signal and an inverted clock signal Here, the inverted clock signal is a clock signal in which the clock signal is inverted, and the pair of n clock signals and the inverted clock signal input to each clock stage are sequentially (180 / n) degrees. Shifted by-and connected in parallel to the input terminal and the output terminal, and connected one to one to each of the n clock terminals, each driven by a pair of the clock signal and the inverted clock signal of the clock terminal connected one to one; And n pumping circuits for generating the output voltage by pumping the boosted voltages.

Preferably, the pumping circuit includes a basic N-type transistor and an inverted N-type transistor having a drain connected to the input terminal, a basic P-type transistor and an inverted P-type transistor having a drain connected to the output terminal, and one end of the basic N-type transistor. A basic pumping capacitor connected to a source and a source of the basic P-type transistor, the other end of which is connected to a clock terminal for inputting the clock signal, and one end of which is connected to a source of the inverted N-type transistor and a source of the inverted P-type transistor, and the other end of the And an inverting pumping capacitor connected to a clock terminal for inputting the inverted clock signal, wherein the gate of the basic N-type transistor and the gate of the basic P-type transistor are connected to a source of the inverted N-type transistor and a source of the inverted P-type transistor. Connected to the gate of the inverted N-type transistor and the Before the gate of the P-type transistor is connected to the source of the source and the primary P-type transistors of the basic N-type transistor it may be characterized in that the cross-linking.

Preferably, the N-type transistor may be an N-type thin film transistor (NTFT) and the P-type transistor may be a P-type thin film transistor (PTFT), and the boost voltage may be a charge pump circuit having a Dickson structure or a charge pump having a cross coupling structure. The input voltage may be boosted by any one of the circuits.

Preferably, m (m> 1) step-up clock stages for inputting a pair of a base input terminal for inputting a base voltage, a boost output terminal for outputting the boosted voltage, a boosted clock signal and an inverted boosted clock signal, wherein the reverse boosted stage The clock signal is a clock signal in which the boosted clock signal is inverted, and the pair of m boosted clock signals and the reversed boosted clock signal input to each boosted clock stage are sequentially shifted by (180 / m) degrees. And one-to-one sequentially connected to each of the m boosting clock stages, each of which is driven by a pair of the boosting clock signal and the reverse boosting clock signal of the boosting clock stage connected one-to-one, and boosts an input voltage. M boost circuits for generating a boosted output voltage, wherein a boost circuit of the foremost stage is connected to the basic input terminal to receive the basic voltage, and each of the m boost circuits; Is connected in series so that the output voltage of the boost circuit of the previous stage is the input voltage of the boost circuit of the rear stage, and the boost voltage may be an output voltage generated by the boost circuit of the last stage.

Advantageously, said boosting circuit comprises: a basic N-type transistor having a drain connected to an output voltage at the front end of said boost circuit and an inverted N-type transistor, wherein the output voltage at the front end of said boost circuit is said basic voltage; A basic P-type transistor having a drain connected to an input voltage of the rear end of the boost circuit and an inverted P-type transistor, wherein an input voltage of the rear end of the boost circuit of the last stage is the boosted voltage; A basic pumping capacitor connected to a source of a transistor and a source of the basic P-type transistor, the other end of which is connected to a boosting clock stage for inputting the boosted clock signal, and one end of which is connected to a source of the inverted N-type transistor and a source of the inverted P-type transistor; The other end of the inverted pumping capacitor connected to a boosted clock stage for inputting the reverse boosted clock signal; The gate of the basic N-type transistor and the gate of the basic P-type transistor are connected to the source of the inverted N-type transistor and the source of the inverted P-type transistor, and the gate of the inverted N-type transistor and the inverted P-type transistor. The gate of may be connected to the source of the basic N-type transistor and the source of the basic P-type transistor is cross-coupled.

Preferably, the N-type transistor may be an N-type thin film transistor (NTFT) and the P-type transistor may be a P-type thin film transistor (PTFT).

In order to achieve the above objects, according to another aspect of the present invention, an input terminal for inputting a boosted voltage, an output terminal for outputting a pumped voltage, n (n> 1) clock stages for inputting a pair of a clock signal and an inverted clock signal Here, the inverted clock signal is a clock signal in which the clock signal is inverted, and a pair of n clock signals and the inverted clock signal input to each clock stage are sequentially (180 / n) degrees. Shifted-, connected in parallel to the input terminal and the output terminal, connected one to one to each of the n clock terminals, each driven by a pair of the clock signal and the inverted clock signal of the clock terminal connected one to one, N pumping circuits for generating an output voltage by pumping the boosted voltage, a basic input terminal for inputting a basic voltage, a boosted output terminal for outputting the boosted voltage, a boosted clock signal and an inverted boosted clock M (m> 1) step-up clock stages for inputting a pair of arcs, wherein the inverting step-up clock signal is a clock signal in which the step-up clock signal is inverted and m step-up clock signals and inversions input to the respective step-up clock stages. The pair of boosting clock signals are sequentially shifted by (180 / m) degrees-and the boosting clock signals of the boosting clock stage connected one-to-one sequentially to each of the m boosting clock stages. And m boost circuits driven by the pair of inverted boost clock signals, respectively, and boosting an input voltage to generate a boosted output voltage, wherein a boost circuit of the foremost stage is connected to the basic input terminal and is connected to the basic input terminal. A voltage is input, and each of the m boost circuits is connected in series so that the output voltage of the boost circuit of the previous stage becomes the input voltage of the boost circuit of the rear stage, and the boost voltage is the boost circuit of the last stage. In that the output voltage generated document provides a charge pump circuit according to claim.

Other objects, specific advantages and novel features of the present invention will become more apparent from the following detailed description and the preferred embodiments associated with the accompanying drawings. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a structural diagram showing a Dickson charge pump circuit according to the prior art. As the most typical charge pump circuit, the pumping efficiency is limited by the threshold voltage drop of the N-type transistor. The ripple voltage appearing at the output is proportional to the clock period since the filtering capacitor is only charged when the clock signal CLK1 is high for every clock period. If all parasitic capacitors are ignored, the output ripple voltage is expressed as the following equation.

(One)

2 is a structural diagram showing a cross-coupled charge pump circuit according to the prior art. The use of cross-coupled charge pump circuits reduces the efficiency degradation of Dickson charge pump circuits due to drop in threshold voltage.

2B is a circuit diagram for explaining the principle of the cross coupling structure.

In general, the pumping circuit 210, the clock terminal 220, the input terminal 230, and the output terminal 240 are configured. The pumping circuit 210 is an inverting pump consisting of a basic pump 211 consisting of N21, an N-type transistor, P21, a P-type transistor, and a pumping capacitor C21, and an N22 transistor, N22, a P-type transistor P22, and a pumping capacitor C22. 212. The clock stage 220 includes a clock signal CLK21 connected to the pumping capacitor C21 of the basic pump 211 and an inverted clock signal CLK22 connected to the pumping capacitor C22 of the inversion pump 212. The input voltage Vin of the input terminal 230 is connected to the N-type transistors N21 and N22 of the basic pump and the inverting pump, and the output voltage Vout of the output terminal 240 is the basic pump 211 and the inverting pump 212. It is connected to P21 and P22 which are P type transistors. The clock signal CLK21 and the inverted clock signal CLK22 of the clock terminal 220 are 180 degrees out of phase with each other, and the period is the same clock signal. If CLK21 is high, CLK22 is low. If CLK21 is low, CLK22 is high.

First, when CLK21 is high and CLK22 is low, N21 of the basic pump 211 and P22 of the inversion pump 212 are turned off, and P21 of the basic pump 211 and N22 of the inverted pump 212 are Is turned on. Accordingly, the input voltage Vin of the input terminal 230 is charged to C22 through the turned-on N22, and the voltage charged to the C21 is discharged to become the output voltage Vout of the output terminal 240 through the turned-on P21.

At this time, the voltage charged in C21 is the input voltage Vin of the input terminal 230 charged through N21 turned on by the clock of the previous period, and in general, when charged through the N-type transistor, the threshold voltage drops. However, the gate voltage of N21 is the voltage charged to C22 of the inversion pump 212, which is as large as the clock amplitude compared to the input voltage Vin, so that the loss due to the threshold voltage drop is reduced and the input voltage Vin is transmitted through the N21 as it is. . Therefore, in the Dickson structure shown in FIG. 1, unlike the threshold voltage drop because the gate voltage is the same as the input voltage, the loss caused by the threshold voltage drop can be reduced and the input voltage can be transferred to the output.

Also, in this structure, the filtering capacitor Cout is charged when the clock signals CLK21 and CLK22 are high for each clock period. Therefore, the charge cycle is cut in half so that the ripple voltage at the final output is reduced in half compared to the Dickson structure shown in FIG. When ignoring the effects of parasitic capacitors, the magnitude of the ripple voltage is expressed as:

(2)

The present invention applies a multi-phase clocking method having four or more clock phases based on a cross coupling structure using this concept.

3 is a structural diagram illustrating a ripple reduction circuit of a charge pump applying multi-phase clocking to a cross coupling structure according to the present invention. This circuit is connected to the filtering capacitor Cout just before the final output stage in the charge pump circuit to reduce the ripple of the output voltage. Since the cross coupling structure can reduce the output loss due to the threshold voltage drop and the magnitude of the ripple voltage rather than the Dickson structure, the cross coupling structure shown in FIG. 2B is basically used.

A case where the number of clock phases is 2n (two clock phases exist in each clock stage and the number of clock stages is n) will be described below. Each clock stage has a clock signal and an inverted clock signal, which are 180 degrees out of phase with each other. The clock signal CLK31-k of the kth clock stage-k differs from the clock signal CLK31-1 of the first clock stage-1 (320-1) by (180 / n) ㅧ (k-1) degrees. The inverted clock signal CLK32-k of the k-th clock stage -k is a clock signal having a phase difference of 180 degrees from the clock signal CLK31-k of the k-th clock stage -k.

The pumping circuits 310-1 to 310-n include basic pumps 311-1 to 311-n and inverting pumps 312-1 to 312-n, respectively. The basic pumps 311-1 to 311-n and the inverting pumps 312-1 to 312-n use a cross coupling structure, and the basic N-type transistors of the basic pumps 311-1 to 311-n are used. The source of, the source of the basic P-type transistors of the basic pumps 311-1 to 311-n and the one side of the basic pumping capacitors of the basic pumps 311-1 to 311-n meet at one node and this node is reversed. It is connected to the gates of the inverted N-type transistors of the pumps 312-1 through 312-n and the gates of the inverted P-type transistors of the inverted pumps 312-1 through 312-n. In addition, the source of the inverted N-type transistors of the inverting pumps 312-1 to 312-n, the source of the inverted P-type transistors of the inverting pumps 312-1 to 312-n and the inverting pumps 312-1 to One side of the inverting pumping capacitor of 312-n) meets at one node, and this node is the gate of the basic N-type transistors of the basic pumps 311-1 to 311-n and the basic pumps 311-1 to 311-n. Is connected to the gate of the basic P-type transistor.

In the input terminal 330, the input voltage which has already been boosted is input to the drain of the basic N-type transistor and the drain of the inverted N-type transistor of each of the pumping circuits 310-1 to 310-n. The process of charging the boosted input voltage to each of the pumping capacitors of the pumping circuits 310-1 to 310-n is the same as that of the above-described cross coupled structure charge pump circuit. According to the clock signal waveform shown in FIG. 3, first, when the clock signal CLK31-1 of the first clock stage-1 (320-1) is high and the inverted clock signal CLK32-1 is low, the pumping circuit-1 (310-1) The output voltage Vout is output to the output terminal 340 through the drain of the basic P-type transistor through the basic pump 311-1. When the filtering capacitor Cout is fully charged, P311-1 is turned off, and thus the charged output voltage Vout of the filtering capacitor Cout is discharged by the load connected to the output terminal 340. At this time, when the clock signal CLK31-2 becomes high after the [clock period Tclk / 2n] in the second clock stage-2 (320-2), the basic pump 311- of the pumping circuit-2 (310-2). 2), the output voltage Vout is output to the output terminal 340 through the drain of the basic P-type transistor. Therefore, after the filtering capacitor Cout which is being discharged starts to be charged again and is fully charged, P312-1 is turned off, and then the charged output voltage Vout of the filtering capacitor Cout is again discharged by the load connected to the output terminal 340.

As the above-described process is repeated, the charging and discharging of the filtering capacitor Cout by the n th clock stage-n is repeated, and the clock signal CLK31-1 of the first clock stage-1 320-1 is low and the inverted clock signal CLK32- When 1 becomes high, the output voltage Vout is outputted to the output terminal 340 through the drain of the inverting P-type transistor of the inverting pump 312-1 of the pumping circuit-1 310-1. Thereafter, the output voltage Vout comes out to the output terminal 340 through the inverting pumps of the respective pumping circuits sequentially, and the charging and discharging of the filtering capacitor Cout is made in the same manner as described above.

That is, as the period during which the charging and discharging of the filtering capacitor Cout is 1 / 2n of the clock period, the frequency increases by 2n times, and the ripple of the output voltage is caused by the ripple of the circuit of the Dickson structure shown in FIG. When compared, it is as small as 1 / 2n.

Therefore, if the output voltage due to the parasitic capacitor and the body effect is ignored, the magnitude of the ripple voltage is reduced to 1 / 2n compared to the Dickson charge pump circuit, which is expressed by the following equation.

(3)

In the present invention, the N-type transistor is preferably an N-type thin film transistor (NTFT) and the P-type transistor is a P-type transistor (PTFT) for use in a polycrystalline silicon TFT-LCD having a high operating frequency.

In addition, in the present invention, each of the clock stages and the pumping circuits need only be connected to each other one-to-one, and need not be sequentially connected. This is because the pumping circuits are connected in parallel with the input terminal and the output terminal, so that each of the pumping circuits does not necessarily have to output the output voltage sequentially.

The ripple reduction circuit and its operation principle of the charge pump applying the multi-phase clocking to the cross-coupling structure according to the present invention shown in FIG. 3 have been described below, with reference to the accompanying drawings and described with reference to specific embodiments. Shall be.

4 is a structural diagram illustrating a ripple reduction circuit 410 of a charge pump applying 4-phase clocking to a cross coupling structure according to an exemplary embodiment of the present invention. This can implement the ripple reduction circuit of the 4-phase clocking charge pump by adding one clock stage to the last lower end of the conventional cross coupled charge pump circuit shown in FIG. In this case, in the ripple reduction circuit of the charge pump to which the multi-phase clocking described above is applied, the value of 2n is 4, and the phase difference of the clock signal is 90 (= 360/4) degrees for each clock stage, and the ripple voltage The size is 1/4 of the Dickson structure.

5 is a structural diagram illustrating a ripple reduction circuit 510 of a charge pump applying 6-phase clocking to a cross coupling structure according to an exemplary embodiment of the present invention. This can implement the ripple reduction circuit of the six-phase clocking charge pump by adding two clock stages to the last bottom of the conventional cross coupled charge pump circuit shown in FIG. In this case, in the ripple reduction circuit of the charge pump to which the multi-phase clocking described above is applied, the value of 2n is 6, and the phase difference of the clock signal is 60 (= 360/6) degrees for each clock stage, and the ripple voltage The size is 1/6 of the Dickson structure.

FIG. 7 is a graph illustrating a ripple voltage over time for a charge pump circuit according to the related art and a ripple reduction circuit of a charge pump according to a preferred embodiment of the present invention. When the output current Iout to be obtained is 100 mA, the Dickson structure shown in Figs. 1, 2, 4 and 5 when the filtering capacitor Cout is 100 pF and the clock frequency fclk (= 1 / Tclk) is 1 MHz is crossed. The ripple magnitude of the output voltage is calculated for each coupling structure, four-phase clocking structure, and six-phase clocking structure. Referring to FIG. 7, the output ripple voltages of the charge pump circuit of the Dickson structure and the cross-coupled structure are 508.8 mV and 263.4 mV, while the ripple voltages at the output to which 4-phase and 6-phase clocking are applied are 132.3 mV and 73 mV. It can be seen that the reduction is ideally consistent with that shown in equation (3).

8 is a graph illustrating a ripple voltage according to the size of a filtering capacitor for each charge pump circuit according to the related art and a ripple reduction circuit of the charge pump according to the preferred embodiment of the present invention. When the output current Iout to be obtained is 100 Hz, when the clock frequency fclk is 1 MHz, the Dickson structure, cross coupling structure, 4-phase clocking application structure, and 6-phase clocking shown in Figs. 1, 2, 4, and 5 are shown. The magnitude of the ripple of the output voltage according to the magnitude of the filtering capacitor Cout is calculated for each application structure. Referring to FIG. 8, when the size of the filtering capacitor Cout is fixed, the output voltage ripple decreases in the order of Dickson structure, cross coupling structure, 4-phase clocking structure, and 6-phase clocking structure.

In addition, the filtering capacitor Cout required to have a ripple voltage of 50 mV with an output current Iout of 100 mA and a clock frequency of fclk of 1 MHz is 1092 pF and 575 pF in Dickson and cross-coupled structures, whereas 4-phase and 6-phase clocking are required. Only 290pF and 157pF are needed in the architecture. In addition, the charge pump of the Dickson structure has a pumping efficiency of 61.27%, whereas the four-phase and six-phase clocking structures using the cross-coupled structure have 67.79% and 67.76%, respectively.

In the above embodiment, the output current is based on 100 mA, but for actual system on glass, the output current is generally required to be several mA. Therefore, in order to obtain an output current of about 100 times larger than in the above-described embodiment, according to Equation (3), the size of the filtering capacitor Cout should be increased by about 100 times in proportion. Therefore, increasing the value of 2n increases the area consumption as the number of pumping capacitors increases in proportion to 2n, but this is a very small value in units of several pF. Therefore, the gain in the area for the system on glass can be obtained by not having to increase the size of the filtering capacitor Cout by 100 times by increasing 2n.

In the above-described embodiment, the ripple reduction circuit of the charge pump to which the multi-phase clocking is applied is a circuit connected between an input terminal and an output terminal receiving a boosted input voltage to reduce the magnitude of the ripple voltage. The boost portion, which is a connection portion from the input voltage to the charge pump circuit applying multi-phase clocking to boost the input voltage, may be a charge pump circuit of a conventional Dickson structure, a conventional cross coupling structure. In addition, voltage boosting may be applied by applying multi-phase clocking.

6 is a structural diagram showing a boosted portion of a charge pump circuit applying multi-phase clocking to a cross coupling structure according to the present invention. Referring to FIG. 6, the boosting part includes a boosting clock stage 620-1 to 620-m, a boosting circuit 610-1 to 610-m, a basic input terminal 630, and a boosting output stage, which is a ripple reduction circuit. It has the same components as However, in the coupling, each of the boosting clock stages 620-1 to 620-m is sequentially connected to each of the boosting circuits 610-1 to 610-m in a one-to-one order. However, the booster circuit-1 610-1 receives the basic input voltage from the basic input terminal 630, and the output of the booster circuit-1 610-1 becomes the input of the booster circuit-2 620-2. . Then, the process of the output of the booster circuit-2 (610-2) becomes the input of the booster circuit-3 is repeated to the booster circuit-m (610-m) at the rear end, thereby boosting circuits 610-1 to 610-m. It can be seen that the transfer process of the input voltage is in series.

As a result, when the clock signal and the inverted clock signal of the boost clock stages 620-1 to 620-m are sequentially high, the basic voltage input is sequentially boosted while passing through each of the boost circuits 610-1 to 610-m. Becomes This results in passing m boost circuits 610-1 through 610-m in one clock cycle, resulting in a much faster boosting effect than passing one pumping circuit in one clock cycle in a conventional Dickson structure or cross coupled structure. Indicates.

In the present invention, the clock stages used in the boost portion and the ripple reduction circuit may share the clock stages of the same period or may use clock stages of different periods. However, since the chip area is partially consumed even in the generation of the clock stage to create the multi-phase, it is advantageous to share the same clock stage to reduce the required chip area.

In addition, the connection of each of the booster circuit and the booster clock stage in the present invention is different from the connection of each of the pumping circuit and the clock stage described above. Since the pumping circuits are connected in parallel to the input and output stages, each of the pumping circuits and the clock stages need only be connected one-to-one and not necessarily sequentially. However, in the case of the booster circuit, each of the booster circuit and the booster clock stage must be sequentially connected one-to-one with each other in order to obtain a fast boosting effect in one clock period.

The present invention is not limited to the above embodiments, and many variations are possible by those skilled in the art within the spirit of the present invention.

As described above, the polycrystalline silicon thin film transistor small area charge pump circuit for the system on glass according to the present invention does not increase the limited frequency or increase the area of the filtering capacitor in the polycrystalline silicon thin film transistor. By reducing the area occupied by the panel, the total area of the system on glass can be reduced.

The polycrystalline silicon thin film transistor small area charge pump circuit for system on glass according to the present invention can reduce the magnitude of the ripple voltage and stably supply the output voltage to the system.

The polycrystalline silicon thin film transistor small area charge pump circuit for system-on-glass according to the present invention can obtain a great efficiency as the current consumption increases, and since the efficiency is not reduced, it can be usefully used for large screen and high resolution polycrystalline silicon TFT-LCD. There is a number.

Claims (8)

In the ripple reduction circuit of the charge pump circuit for system on glass, An input terminal for inputting a boosted voltage; An output stage for outputting a pumped voltage; N (n> 1) clock stages for inputting a pair of clock signal and inverted clock signal, wherein the inverted clock signal is a clock signal in which the clock signal is inverted and the n clock signals input to each clock stage. And the pair of inverted clock signals are sequentially shifted by (180 / n) degrees; And Connected in parallel to the input terminal and the output terminal, and connected to each of the n clock terminals in a one-to-one manner, respectively, driven by the pair of the clock signal and the inverted clock signal of the clock terminal connected one-to-one, and boosting the voltage. And n pumping circuits for pumping to produce an output voltage. The method of claim 1, wherein the pumping circuit A basic N-type transistor and an inverted N-type transistor having a drain connected to the input terminal; A basic P-type transistor and an inverted P-type transistor having a drain connected to the output terminal; A basic pumping capacitor having one end connected to a source of the basic N-type transistor and a source of the basic P-type transistor and the other end connected to a clock terminal for inputting the clock signal; And One end is connected to the source of the inverted N-type transistor and the source of the inverted P-type transistor and the other end includes an inverted pumping capacitor connected to the clock terminal for inputting the inverted clock signal, A gate of the basic N-type transistor and a gate of the basic P-type transistor are connected to a source of the inverted N-type transistor and a source of the inverted P-type transistor, and a gate of the inverted N-type transistor and a gate of the inverted P-type transistor Is a ripple reduction circuit of the charge pump circuit, characterized in that it is coupled to and coupled to the source of the basic N-type transistor and the source of the basic P-type transistor. The method of claim 2, And the N-type transistor is an N-type thin film transistor (NTFT) and the P-type transistor is a P-type thin film transistor (PTFT). The method of claim 1, wherein the boost voltage is An input voltage is boosted by either a charge pump circuit of a Dickson structure or a charge pump circuit of a cross-coupled structure. The method of claim 1, A basic input terminal for inputting a basic voltage; A boost output stage configured to output the boost voltage; M (m> 1) step-up clock stages for inputting a pair of a step-up clock signal and a reverse step-up clock signal, wherein the step-up clock signal is a clock signal in which the step-up clock signal is inverted and is input to each step-up clock stage. M pairs of the boosted clock signal and the reversed boosted clock signal are sequentially shifted by (180 / m) degrees; And One-to-one sequentially connected to each of the m boosting clock stages, each of which is driven by a pair of the boosting clock signal and the reverse boosting clock signal of the boosting clock stage connected one-to-one, and boosted by boosting an input voltage; Further comprising m boost circuits for generating a voltage, The booster circuit of the foremost stage is connected to the basic input terminal to receive the basic voltage, and each of the m booster circuits is connected in series so that the output voltage of the booster circuit of the previous stage becomes the input voltage of the booster circuit of the rear stage. And the voltage is an output voltage generated in the last boost circuit. The method of claim 5, wherein the boost circuit A basic N-type transistor and an inverted N-type transistor having a drain connected to an output voltage at the front end of the boost circuit, wherein the output voltage at the front end of the boost circuit at the foremost end is the basic voltage; A basic P-type transistor and an inverted P-type transistor having a drain connected to an input voltage at a rear end of the boost circuit, wherein an input voltage at a rear end of the boost circuit at the last end is the boosted voltage; A basic pumping capacitor having one end connected to a source of the basic N-type transistor and a source of the basic P-type transistor and the other end connected to a boosted clock stage for inputting the boosted clock signal; And One end is connected to the source of the inverted N-type transistor and the source of the inverted P-type transistor and the other end includes an inverted pumping capacitor connected to the boosted clock stage for inputting the inverted boosted clock signal, A gate of the basic N-type transistor and a gate of the basic P-type transistor are connected to a source of the inverted N-type transistor and a source of the inverted P-type transistor, and a gate of the inverted N-type transistor and a gate of the inverted P-type transistor Is a ripple reduction circuit of the charge pump circuit, characterized in that it is coupled to and coupled to the source of the basic N-type transistor and the source of the basic P-type transistor. The method of claim 6, And the N-type transistor is an N-type thin film transistor (NTFT) and the P-type transistor is a P-type thin film transistor (PTFT). In a charge pump circuit for system on glass, An input terminal for inputting a boosted voltage; An output stage for outputting a pumped voltage; N (n> 1) clock stages for inputting a pair of clock signal and inverted clock signal, wherein the inverted clock signal is a clock signal in which the clock signal is inverted, and n clock signals input to each clock stage; The pair of inverted clock signals are sequentially shifted by (180 / n) degrees; Connected in parallel to the input terminal and the output terminal, and connected to each of the n clock terminals in a one-to-one manner, respectively, driven by the pair of the clock signal and the inverted clock signal of the clock terminal connected one-to-one, and boosting the voltage. N pumping circuits for pumping to generate an output voltage; A basic input terminal for inputting a basic voltage; A boost output stage configured to output the boost voltage; M (m> 1) step-up clock stages for inputting a pair of a step-up clock signal and a reverse step-up clock signal, wherein the step-up clock signal is a clock signal in which the step-up clock signal is inverted and is input to each step-up clock stage. A pair of m boosted clock signals and an inverted boosted clock signal are sequentially shifted by (180 / m) degrees; and One-to-one sequentially connected to each of the m boosting clock stages, each of which is driven by a pair of the boosting clock signal and the reverse boosting clock signal of the boosting clock stage connected one-to-one, and boosted by boosting an input voltage; Further comprising m boost circuits for generating a voltage, The booster circuit of the foremost stage is connected to the basic input terminal to receive the basic voltage, and each of the m booster circuits is connected in series so that the output voltage of the booster circuit of the previous stage becomes the input voltage of the booster circuit of the rear stage. The voltage is the charge pump circuit, characterized in that the output voltage generated in the boost circuit of the last stage.