JP3300317B2 - Semiconductor booster circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor booster circuit having a multi-stage charge pump circuit for boosting voltage without using a coil. More specifically, the present invention relates to a charge pump circuit in which a charge kick capacitor is provided for each stage. The present invention relates to a semiconductor booster circuit provided with opening / closing means for preventing backflow between stages.

[0002]

2. Description of the Related Art A semiconductor booster circuit whose circuit diagram is shown in FIG. 7A is used to boost a power supply voltage Vdd to a higher output voltage Vo without using a non-semiconductor element such as a coil.
It comprises a multi-stage charge pump circuit 1 and a clock signal generating circuit 2 for supplying clock signals φ and φ * thereto. The clock signal φ and the clock signal φ * are 180 ° out of phase with each other and are a pair of generally inverted signals (see FIG. 7B. In the figure, the inverted signal indicated by the superimposed bar is shown). The symbol is denoted by * at the end of the specification).

A charge pump circuit 1 receives a power supply voltage Vdd on an input line and supplies an output current Io boosted to an output voltage Vo from an output line to a load circuit 3 and the like. One end of a kick capacitor Ck is connected to the line for each stage, and MOS transistors M1 to M5 are connected to the conductive line at the first stage and between the stages.
The MOS transistors M1 to M5 are diode-connected, and serve as opening / closing means for opening / closing a conductive line for transmission. At the last stage, a MOS transistor Mr for opening and closing a conductive line for rectification is inserted.

When one of the clock signals φ and φ * is alternately supplied to the other end of each kick capacitor Ck (in FIG. 7, φ is supplied to the first, third and fifth Ck from the left). And φ * is supplied to the second and fourth Ck),
The MOS transistors M1, M3, M5 and the MOS transistors M2, M4, Mr alternately turn on and off, and each time the kick capacitor Ck, which has been boosted by an amount corresponding to the power supply voltage Vdd, from the adjacent kick capacitor Ck, which is not so
k (ie, when φ is high and φ * is low, the second Ck from the first Ck via M2)
The current corresponding to the potential difference between the two flows through M4, the current corresponding to the potential difference flows from the third Ck to the fourth Ck via M4, and the current flows from the fifth Ck to the load circuit 3 via Mr. The current according to the potential difference flows, and when φ is low, φ *
Is high, the power supply voltage Vdd is
A current corresponding to the potential difference between the two flows through the third Ck via M3, a current corresponding to the potential difference between the two flows from the second Ck to the third Ck via M3, and a fifth current via the fifth Ck via M5. If the output voltage Vo has 5 stages as shown in FIG. 7 (the voltage at one end of the first Ck from the left is alternately synchronized with φ and the power supply voltage is alternately supplied to Ck). V
dd or 2 × Vdd, and the voltage at one end of the second Ck alternately becomes 2 × Vdd or 3 × Vdd in synchronization with φ *,
The voltage at one end of the third Ck is alternately 3 × V in synchronization with φ.
dd or 4 × Vdd, and the voltage at one end of the fourth Ck alternately becomes 4 × Vdd or 5 × Vdd in synchronization with φ *,
The voltage at one end of the fifth Ck is alternately 5 × V in synchronization with φ.
dd or 6 × Vdd, and ideally reaches 6 × Vdd (due to the rectification of Mr). In the case of n stages, an output voltage Vo of (n + 1) × Vdd is ideally output.

However, in such a semiconductor booster circuit, if it is formed as it is on a one-chip IC, the back gate portion (further deep portion of the channel region below the gate) of the MOS transistor serving as the opening and closing means is in a state of being commonly connected. Therefore, the on-characteristics of the subsequent MOS transistor are degraded because of the influence of an undesired substrate effect called substrate modulation. Therefore, there is an inconvenience that a desired output voltage cannot be easily obtained even if the number of stages is increased as the number of stages is increased.

In order to solve this problem, the MOS transistor is separated by applying an element isolation technique which is the basis of an integrated circuit, for example, by using an insulating substrate or forming an individual well, and then the respective back gates are separated. It is conceivable as a direct countermeasure that the section is brought into a floating state or connected to a source or the like by a clamp.
607, JP-A-7-327357, JP-A-8-83486, etc.). According to such measures, the problem of substrate modulation has been reduced, and the output voltage has been improved.

[0007]

However, in a case where the load is light and the condition is stable, for example, in an application in which the output current becomes almost constant at about several μA, the liquid crystal device ( In the case of driving an LCD (LCD), this is not the case, so there are the following problems. That is, the required output current is about several mA, the load is heavy, and the driving state changes according to display data and the like.
The output current frequently fluctuates greatly. Then, the influence of such output fluctuation also affects the gate control state of the MOS transistor via the output line or the conductive line, and deteriorates the ON characteristics of the MOS transistor. The effect is larger as the boosting at each stage is smaller, and the larger the effect is, the larger the output voltage fluctuates and the slower the recovery from the fluctuation.

Therefore, it is a technical problem to devise a circuit configuration such that the control state of the switching means does not change or hardly changes even if the state of the output load changes. The present invention has been made to solve such a problem, and has as its object to realize a semiconductor booster circuit that is resistant to output load fluctuation.

[0009]

According to the present invention, a basic charge pump circuit similar to the circuit shown in FIG. 7 is used for driving, and a charge pump circuit similar to the circuit described in Japanese Patent Application Laid-Open No. 7-298607 is controlled. The purpose of the present invention is to solve the above-mentioned problems by properly using them for different purposes and by taking further measures into consideration when combining the two. Less than,
The configuration, operation, and effect of the first to fourth solving means invented for that purpose will be described.

[First Solution] The semiconductor booster circuit of the first solution (as described in claim 1 at the time of filing the application)
Multi-stage connected to the output line (to the load) at one or more stages (of the final rectification stage and each stage in the middle) (capable of outputting boosted current) And a multi-stage second charge connected to the first charge pump circuit for each stage and not connected to the output line at any stage (directly or in a state where current can be output). And a pump circuit.
That is.

Here, the above-mentioned "charge pump circuit"
Is characterized in that a kick capacitor for charging is provided in multiple stages and an opening / closing means for preventing backflow is provided between each stage.Each "kick capacitor" receives a predetermined clock and boosts and boosts one stage. It is a capacitor that repeats step-down. The “multi-stage” is most practical at several stages to tens of stages at present, and naturally includes several tens or more stages, but the effect is not conspicuous at one or two stages. Corresponding to or higher.

In the semiconductor booster circuit according to the first solving means, the charge pump circuit is divided into two rows, and the second charge pump circuit is separated from the output line to provide the first drive circuit. It is for controlling the charge pump circuit. Therefore, even if the first charge pump circuit receives a load change via the output line, the second charge pump circuit operates stably without being affected by the load change, and the second charge pump circuit operates based on the stabilized boosted voltage of each stage. Since the opening / closing means of each stage in one charge pump circuit is controlled, their control states are stabilized irrespective of output load fluctuations.

As described above, since the control and the drive are divided into two rows, even if the state of the output load fluctuates, and even if the drive side is connected to the output line, the control state of the opening / closing means is controlled. Does not vary much. Therefore, according to the present invention, a semiconductor booster circuit that is resistant to output load fluctuation can be realized.

[Second Solution] A semiconductor booster circuit according to a second solution (as described in claim 2 at the beginning of the application)
In the above-mentioned semiconductor booster circuit according to the first solution, all the switching means between the stages in the first charge pump circuit are MOS transistors, and the second charge pump circuit is connected to the first charge pump circuit. Connection is M
This is done for the gate of the OS transistor.

In the semiconductor booster circuit according to the second solution, the load on the second charge pump circuit for control is extremely light, so that the portion can be easily miniaturized, and furthermore, the influence of load fluctuations can be obtained. Is reliably stopped from propagating through the first charge pump circuit for driving, so that the operation state is always stable. Under stable and appropriate control conditions, M
Since the OS transistor is reliably turned on and off, the voltage loss due to the switching means can be reduced, and the current driving capability is maintained at a high level, so that the capability of recovering from output fluctuations is further improved. Therefore, according to the present invention,
A semiconductor booster circuit that is more resistant to output load fluctuations can be realized.

[Third Solution] A semiconductor booster circuit according to a third solution (as described in claim 3 at the beginning of the application) is:
In the semiconductor booster circuit according to the second solution means, all the switching means between the stages in the second charge pump circuit are MOS transistors.

In the semiconductor booster circuit of the third solution, not only the switching means of the first charge pump circuit but also the switching means of the second charge pump circuit are all MOS transistors. It is unified. As a result, the operating characteristics of each stage are well aligned, so that even if the number of stages is increased, no mismatch occurs between the drive-side opening / closing means and its control state. Therefore, according to the present invention, it is possible to realize a semiconductor booster circuit that is more resistant to output load fluctuation and multi-stage operation.

[Fourth Solution] The semiconductor booster circuit of the fourth solution (as described in claim 4 at the beginning of the application)
In the semiconductor booster circuit according to any one of the first to third solving means, each of the kick capacitors at each stage in the first charge pump circuit has a larger capacity than the kick capacitors at each stage in the second charge pump circuit. That is.

In the semiconductor booster circuit according to the fourth solution, the first charge pump circuit supports a large output current with a large-capacity kick capacitor, while the second charge pump circuit supports a large output current. Stable control is performed. As a result, even if a large current is taken out and the current value greatly changes, a stable operation result can be obtained under stable control, and the driving capability is improved. Therefore, according to the present invention, it is possible to realize a semiconductor booster circuit capable of extracting a large current and resistant to output load fluctuation.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments for implementing the semiconductor booster circuit of the present invention achieved by such a solution will be described with reference to the following first to third embodiments. The first embodiment shown in FIGS. 1 to 3, the second embodiment shown in FIG. 4, and the third embodiment shown in FIG. 5 all implement the above-described first to fourth solving means. And
The main difference between the first embodiment and the second embodiment is that the MOS transistor as the opening / closing means is a pMOS (P-channel MO).
S) or nMOS (N-channel MOS). The main difference between them and the third embodiment is that the connection destination of the back gate of the MOS transistor as the opening / closing means is another charge pump circuit. That is.

[0021]

First Embodiment A first embodiment of a semiconductor booster according to the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram thereof, and FIG. 2 is a waveform example of a clock signal.

This semiconductor booster circuit includes a control charge pump circuit 4 (second charge pump circuit), a driving charge pump circuit 5 (first charge pump circuit),
A clock signal generation circuit 6 is provided in a one-chip IC, receives a power supply voltage Vdd on an input line, boosts it to an output voltage Vo, and supplies the output voltage Vo from the output line. An appropriate load circuit 7 is connected to the output line to supply the boosted current to the load.
In a driving circuit or the like, the charge pump circuit is divided into a control circuit and a driving circuit, and is connected to an output line so as to be applicable to an application requiring a large output current Io due to its small equivalent resistance R and large capacitance C. The charge pump circuit 5 has a sufficient driving capability.

More specifically, in order to obtain an output voltage Vo that is slightly less than six times the power supply voltage Vdd, the charge pump circuit 5 includes:
Five kick capacitors Ck are provided, and one end of each is connected to a conductive line from an input line to an output line. In addition, the conductive line between the input line and the first stage kick capacitor Ck, between respective connection points, that is, between stages in the conductive line, and between the fifth stage kick capacitor Ck and the output line. , PMOS transistors M1, M2, M3, M4, M5, and Mr are sequentially inserted as opening / closing means.

The last MOS transistor Mr connected to the output line is used for rectifying the output current Io. Therefore, the number of switching transistors is one more than the kick capacitor Ck. The transistors M1 to Mr are formed in individual well regions, and all have a drain connected to the input side / front stage and a source connected to the rear stage / output side.
It is determined for the sake of convenience, and since the MOS transistors are symmetrical, they may be reversed. The same applies to the following description. ). The gate and the back gate are connected to corresponding stages in the charge pump circuit 4 as described later.

The charge pump circuit 4 controls the MO to be controlled.
Six stages are provided corresponding to the six S transistors M1 to Mr. A kick capacitor Ca is provided for each stage, and one end of each is connected to another conductive line extending from the input line. ing. Further, between the input line and the kick capacitor Ca in the first stage and between the respective connection points, that is, between the stages in the other conductive lines, the pMOS transistor Q1 is used as an opening / closing means for the conductive lines one by one. , Q2, Q3, Q4, Q5
Qr is interposed and connected.

These transistors Q1 to Qr are also formed in individual well regions, and all have drains on the input side.
The source and back gate are connected to the front stage,
Connected to output side. However, the number of switching transistors is the same as that of the kick capacitor Ca, and there is no connection of a rectifying transistor or the like to the output line. That is, not only at the last stage but also at any stage in the middle, no direct connection to the output line is made, and no connection is made at all in a state where current can be output to the output line.

The charge pump circuit 4 is provided for each stage.
And the charge pump circuit 5 are connected. Specifically, the gate of MOS transistor Q1 and the gate of MOS transistor M1 are connected, and MOS transistor M1
1 is connected to the back gate of the MOS transistor Q1 and the source of the MOS transistor Q1. Other MOS transistors Q2-Qr, M2-
Similar connections are made for each of Mr.

Further, for each stage, another pMOS
Transistors P1 to Pr and a capacitor Cb having one end connected to the drain thereof are provided. The connection line is connected to the connection line between the gates of MOS transistors Q1 to Qr and M1 to Mr.
The source and back gate of Pr are connected to one end of a kick capacitor Ca in each stage, ie, MOS
Connected to the sources of transistors Q1-Qr. Also,
The gates of the MOS transistors P2 to Pr in the second and subsequent stages are connected to the drains of the MOS transistors Q2 to Qr in the respective stages, that is, to the sources of the MOS transistors Q1 to Q5 in the immediately preceding stage.

Here, the capacitance of each capacitor will be described. The kick capacitor Ck has the largest value of several thousand pF.
The kick capacitor Ca has a smaller capacity of several pF, and the capacitor Cb has a smaller capacity and a kick capacitor CF.
This is about a fraction of a, and several mA can be taken out as the output current Io. However, if the output current Io is smaller than that, the capacity of the kick capacitor Ck may be reduced as appropriate to facilitate the IC integration. For example, even if the kick capacitor Ck is reduced to the same level as the kick capacitor Ca, it is strong against output fluctuation. The benefits are maintained. Note that the driving capabilities of the MOS transistors M1 to Mr are also set appropriately according to the capacity of the kick capacitor Ck. That is, in the case of this example, the MOS transistors M1 to Mr
As compared with the MOS transistors Q1 to Qr, the driving capability is large and the on-resistance is small.

The clock signal generating circuit 6 generates four types of clock signals φ required by the charge pump circuits 4 and 5.
1, φ2, φ3, φ4, and all of the clock signals φ1 to φ4 are repeatedly turned on and off at the same frequency of several MHz. In the on state, the power supply voltage becomes almost equal to Vdd, and in the off state, it becomes almost 0 V of the ground GND (see FIG. 2). Among them, the clock signal φ1 has a duty ratio of less than 50% (turns on only during the period t2 to t4),
The clock signal φ2 also has a duty ratio of slightly less than 50%, but has a phase shift of about 180 ° so as not to overlap with the clock signal φ1 (turns on only during the period t6 to t8). The clock signal φ3 is turned off only during a part (period t7) of the period during which the clock signal φ2 is turned on, and the clock signal φ4 is turned off.
Is turned off only in a part (period t3) of the period when the clock signal φ1 is on. .

Further, the clock signal φ1 is sent to the other ends of the first, third and fifth kick capacitors Ca and Ck, and the clock signal φ2 is output to the second, fourth and final stages. The other end of the kick capacitor Ca and 2
The other ends of the kick capacitors Ck of the fourth and fourth stages and the MOS
The clock signal φ3 is sent to the gate of the transistor P1, the clock signal φ3 is sent to the other end of the first, third and fifth stage capacitors Cb, and the clock signal φ4 is sent to the second, fourth and last stage capacitors Cb. To the other end. Note that when the clock signal φ2 is applied to the first stage, the above is all reversed.

The usage and operation of the semiconductor booster circuit of the first embodiment will be described with reference to the drawings. FIG. 3 is an example of a voltage waveform of each part showing the operation state. The gate voltage Va of the MOS transistors M1 and Q1, the source voltage of the MOS transistor Q1, ie, the voltage Vb at one end of the first-stage kick capacitor Ca,
The source voltage of the transistor M1, that is, the voltage Vc at one end of the first-stage kick capacitor Ck and the MOS transistor M
2, the gate voltage Wa of Q2 and the MOS transistor Q2
, Ie, the voltage Wb at one end of the second-stage kick capacitor Ca, and the source voltage of the MOS transistor M2, ie, the voltage Wc at one end of the second-stage kick capacitor Ck.
With respect to and, a waveform for one cycle is illustrated. In the drawings and the following description, for simplicity and the like, a switching MOS
The on-resistance of the transistor and the parasitic element of the conductive line are ignored.

First, in an ideal steady state, a kick is made via a kick capacitor Ck as the clock signal φ1 is turned on and off, so that the voltage Vc is equal to the power supply voltage Vdd.
When the clock signal φ1 is on (period t2 to t4), the voltage value becomes (2 × Vdd), and when the clock signal φ1 is off (period t1, t5 to t8), the voltage value is (Vdd). Becomes The voltage Vb is also the kick capacitor C
It becomes the same by the intervention of a. On the other hand, the voltage Va
Is determined by the magnitude relationship between the clock signals φ2 and φ3 and the voltage Vb, and while the clock signal φ3 is on (period t1 to t1).
6, t8) The same as the voltage Vb, but the clock signal φ3
Is off (period t7), the power supply voltage V is higher than the voltage Vb.
dd. Thus, only then MOS
The transistors Q1 and M1 are turned on to be in an open state, that is, a conductive state.

In addition, since the kick via the kick capacitor Ck is performed as the clock signal φ2 is turned on and off, the voltage Wc rises and falls by the power supply voltage Vdd, and the clock signal φ2 is turned on (period t6 to t8). When the voltage value is (3 × Vdd) and the clock signal φ2 is off (period t1 to t5), the voltage value is (2 × Vdd). The voltage Wb also becomes the same due to the presence of the kick capacitor Ca. On the other hand, the voltage Wa is determined by the magnitude relationship between the clock signal φ4, the voltage Vb, and the voltage Wb. While the clock signal φ4 is on, it becomes the same as the voltage Wb (period t1, t2, t4 to t8). When the clock signal φ4 is off (period t3), the voltage becomes lower than the voltage Wb by the power supply voltage Vdd. Thus, only at that time, the MOS transistors Q2 and M2 are turned on to be in an open state, that is, a conductive state.

Similarly, the charge voltage increases by the power supply voltage Vdd as it goes to the subsequent stage, but the MOS transistors M3, M5, Q3 and Q5
1 and at the same timing as Q1. Further, the MOS transistors M4, Mr, Q4, Qr are turned on at the same timing as the MOS transistors M2, Q2. And
In the charge pump circuit 5, the first half of each cycle (period t3)
Every other stage in the second half (period t7), the conductive line extending between one end of the kick capacitor Ck of the preceding stage, which has been kicked and increased, and one end of the kick capacitor Ck of the subsequent stage, which has been lowered without being kicked, is made conductive. (That is, in the case of FIG. 1, at t3, the conductive lines at M2, M4, and Mr conduct, and at t4, the conductive lines at M1, M3, and M5 conduct.)

At this time, if the output current Io is taken out from the output line and the amount of charge of the subsequent kick capacitor Ck is reduced, the voltage of the subsequent stage is lower than the voltage of the subsequent stage. During the conduction of .about.M5, the charge moves from the kick capacitor Ck on the preceding stage to the kick capacitor Ck on the subsequent stage, and the charge amount is replenished. Thus, in the charge pump circuit 5, the power supply voltage Vdd is boosted to the output voltage Vo via each stage, and the boosted output current Io is taken out from the output line and supplied to the load circuit 7.

In the charge pump circuit 4 as well, the kick capacitor C of the previous stage which has been kicked and increased in the first half (period t3) and the second half (period t7) of each cycle is provided every other stage.
a, and a conductive line extending to one end of a kick capacitor Ca at the subsequent stage, which is lowered without being kicked, is made conductive (that is, Q2, Q4, Qr at t3 in FIG. 1).
At t4, Q1, Q3, Q3
The conductive line at Q5 becomes conductive), and the power supply voltage Vdd is boosted by each stage, but the electric charge charged in each of the kick capacitors Ca and Cb is MOS
Since it is only used to control the gates and the like of the transistors M1 to Mr, an explicit current extraction such as supply to the load circuit 7 is not performed, and in a steady state, the charging of each kick capacitor Ca and the capacitor Cb is performed. The clock signal φ1, φ1
Follow 2

Then, such stable voltages Vb, W
The voltages Va, Wa, etc. generated based on the clock signals .phi.3, .phi.4 and the like become stable voltage signals that clearly change when they should change, and operate by receiving those voltage signals at the gate and the back gate unit. MOS transistor M
1 to Mr always operate in a stable unsaturated state, excluding the influence of the substrate modulation. Therefore, the MOS transistors M1 to Mr, Q1 to Qr omitted in the above description
Are substantially constant at small values of about 0.1 V to 0.2 V, respectively, so that the output voltage Vo is clearly determined and the calculation at the time of design is easy. Thus, in the steady state, a sufficient amount of output current Io boosted to the desired output voltage Vo is supplied to the load circuit 7.

On the other hand, if the output current Io becomes excessive due to the state fluctuation of the load circuit 7 even if it is temporary, the charge amount of the last-stage kick capacitor Ck sharply decreases and the output voltage Vo decreases. start. Then, the phenomenon propagates from the subsequent stage to the preceding stage in order. Regardless of the state of the charge pump circuit 5 side, the charge pump circuit 4 always generates a control signal of an appropriate voltage level. Since the gates and the like of M1 to Mr are controlled, the MOS transistors M1 to Mr on the side of the charge pump circuit 5 whose source and drain voltages fluctuate with the fluctuation of the output voltage Vo are stable as in the steady state. Works. In addition, since their on-resistance is also maintained at a small value, the shortage of the charge amount is quickly replenished between the kick capacitors Ck from the former stage to the latter stage. Then, the output voltage Vo recovers quickly. Thus, regardless of the state change, the load circuit 7
An output current Io that is stable at the output voltage Vo is always sufficiently supplied.

[0040]

Second Embodiment A specific configuration of a semiconductor booster circuit according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 4 is a circuit diagram corresponding to FIG. 1 described above.

This semiconductor booster circuit differs from that of the first embodiment in that the input line is grounded,
Each MOS transistor M1-Mr, Q1-Qr, P1-
The point where Pr is changed from pMOS to nMOS and the clock signals φ1 to φ4 are clock signals φ
1 * to φ4 * (in the figure, the inverted symbol shown by the superscript bar is indicated by the asterisk * in the present specification).

In this case, except that the polarity of the voltage is reversed,
Since the operation is performed in the same manner as described above, the output voltage Vo is boosted to the negative side. In this way, not only the positive output voltage but also the negative output voltage can be reliably boosted and a sufficient current can be stably supplied regardless of the load fluctuation.

[0043]

Third Embodiment A specific configuration of a third embodiment of the semiconductor booster circuit according to the present invention will be described with reference to the drawings. FIG. 5 is a circuit diagram corresponding to FIG. 1 described above.

The difference between this semiconductor booster circuit and the first embodiment is that each of the MOS transistors M1 to M
5, Mr, Q1 to Q5, Qr, P1 to P5, and the connection destination of the back gate section has moved from the charge pump circuit 4 to the charge pump circuit 5. Specifically, each stage in the charge pump circuit 5 is connected to one end of the corresponding kick capacitor Ck, that is, the MOS transistor M1
It is connected to the sources of M5 and Mr.

In this case, although each MOS transistor is affected to some extent by the output load fluctuation via the conductive lines and the respective back gate portions, it is necessary that the kick capacitor Ck has a sufficiently large capacity. Since the on-resistances of the transistors M1 to Mr are very small, and the gates of all the MOS transistors receive a stable control signal from the charge pump circuit 4 side, the operation state is stable and the output is moderate. Withstands load fluctuations. Thus, also in this case, reliable boosting and stable supply of sufficient current are performed.

[0046]

[Others] In each of the above embodiments, the number of stages of the charge pump circuit 5 is five, which is easy to illustrate. However, the number of stages is not limited to this, and three or four stages may be used. The number of stages may be six or more depending on the level. As the number of stages increases, the output voltage Vo also increases substantially in proportion (see the graph of FIG. 6, where the horizontal axis indicates the number of stages of the charge pump circuit and the vertical axis indicates the output voltage Vo).

Further, in each of the above embodiments, the output is extracted only from the final rectification stage, but the output extraction is not limited to the final stage. If the current drive capability limit is satisfied, separate rectifiers and output lines are connected to any one or more of the intermediate stages to extract various voltages with different boost levels. It is also possible.

Further, clock signals φ1 to φ4, φ1 *
~ Φ4 * can be shared by multiple semiconductor booster circuits,
If you can use the clock signal for other circuits,
Even when the clock signal is supplied from outside the IC of the semiconductor booster circuit, the semiconductor booster circuit of the present invention can operate, so that the clock signal generating circuit 6 is not essential.

[0049]

As is apparent from the above description, in the semiconductor booster circuit according to the first solution of the present invention, the charge pump circuit is divided into a control circuit and a drive circuit in a double row, There is an advantageous effect that a semiconductor booster circuit resistant to output load fluctuation can be realized.

Further, in the semiconductor booster circuit according to the second solution of the present invention, since the control target is the gate portion of the MOS transistor, a semiconductor booster circuit that is more resistant to output load fluctuation can be realized. It has the advantageous effect that

Further, in the semiconductor booster circuit according to the third solution of the present invention, the characteristics of the opening and closing means are made uniform on both the control side and the drive side, so that both the output load fluctuation and multi-stage can be achieved. There is an advantageous effect that a strong semiconductor booster circuit can be realized.

Further, in the semiconductor booster circuit according to a fourth solution of the present invention, the charge pump circuit is divided into a control circuit and a drive circuit to form a double row, and the drive side has a large output. As a result, there is an advantageous effect that a semiconductor booster circuit capable of extracting a large current and resistant to fluctuations in output load can be realized.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a semiconductor booster circuit of the present invention.

FIG. 2 is a waveform example of the clock signal.

FIG. 3 is a voltage waveform example showing an operation state thereof.

FIG. 4 is a circuit diagram of a second embodiment of the semiconductor booster circuit of the present invention.

FIG. 5 is a circuit diagram of a third embodiment of the semiconductor booster circuit of the present invention.

FIG. 6 shows first and second semiconductor booster circuits according to the present invention;
5 is a graph obtained by changing the number of stages of a kick capacitor and the like in a charge pump and measuring each output voltage Vo.

7A and 7B show a conventional semiconductor booster circuit, FIG. 7A is a circuit diagram, and FIG. 7B is a waveform example of a clock signal.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Charge pump circuit (single-row type) 2 Clock signal generation circuit 3 Load circuit (light load) 4 Charge pump circuit (second charge pump circuit, dedicated control side, double-row type) 5 Charge pump circuit (first charge pump circuit) , Load drive side, double row type) 6 Clock signal generation circuit 7 Load circuit (heavy load)

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-10-248239 (JP, A) JP-A-6-217527 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H02M 3/07

Claims (3)

(57) [Claims] 1. A multistage first charge pump circuit connected to an output line at any stage, and the first charge pump circuit for each stage.
E Bei a second charge pump circuit of a multi-stage not connected to the output line in the connected one stage to the charge pump circuit, both the opening and closing means between stages before Symbol first charge pump circuit has a MOS transistor , The second
A semiconductor booster circuit for an LCD, wherein a connection from a charge pump circuit to the first charge pump circuit is made to a gate of the MOS transistor. 2. A semiconductor booster circuit for an LCD according to claim 1, wherein the switching means between the stages in the second charge pump circuit are all MOS transistors. 3. The kick capacitor of each stage in the first charge pump circuit has a larger capacity than the kick capacitor of each stage in the second charge pump circuit. LC
Semiconductor booster circuit for D.