JP2005102375A - Charge pump circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a charge pump circuit which can obtain a desired output voltage, with the number of stages smaller than before. <P>SOLUTION: As the power voltage of a clock driver 3, the output voltage (the voltage V1 at the junction between MOS transistors M1 and M2) of a MOS transistor M1 on two stages before that is used, and as the power voltage of a clock driver 4, the output voltage (the voltage V2 at the junction between MOS transistors M2 and M3) of the MOS transistor M2 on two stages before that is used. The high-level output of the clock driver 3 becomes a voltage higher than Vdd called V1(2Vdd), and the high-level voltage of the clock driver 4 becomes a further higher voltage called V2(3Vdd). Hereby, as compared with a conventional charge pump circuit, a higher boosted voltage Vout=8Vdd can be obtained with the same number of stages. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a charge pump circuit, and more particularly to a charge pump circuit using a capacitor and a charge transfer element.

  In EEPROM (Electrically Erasable Programmable Read Only Memory) and Flash Memory (Flash Memory) write / erase systems, LCD (Liquid Crystal Display) systems, systems that drive analog switches, etc., it is necessary to supply a voltage higher than the power supply voltage. is there. For this reason, providing various types of power supplies independently is complicated, large-scale, and expensive as a system, and a single power supply is desired.

  Therefore, a method of incorporating a charge pump circuit is widely used in MOS integrated circuits. The charge pump circuit is a circuit that can boost the power supply voltage with a simple circuit, and can provide a higher voltage with a single power supply of the system.

FIG. 5 is a circuit diagram showing a four-stage charge pump circuit. M1, M2, M3, M4, and M5 are five N-channel MOS transistors connected in series, and C1, C2, C3, and C4 are four capacitors. The N-channel MOS transistors M1, M2, M3, and M4 , M5, one terminal of capacitors C1, C2, C3, C4 is connected to each connection point.
Reference numerals 10, 11, 12, and 13 denote clock drivers composed of inverter circuits. A clock pulse Φ is input to the clock drivers 10 and 12, and a clock pulse * Φ having a phase opposite to that of the clock pulse Φ is input to the clock drivers 11 and 13. Is entered.
The outputs of the clock drivers 10 and 12 are applied to the other terminals of the capacitors C1 and C3, respectively, and the outputs of the clock drivers 11 and 13 are applied to the other terminals of the capacitors C2 and C4, respectively.

Vdd is an input voltage generated from the input voltage source 15, and is applied to the drain of the first-stage N-channel MOS transistor M1. The voltage Vdd is also used as a power supply voltage for the clock drivers 10, 11, 12, and 13.
Vout is an output voltage, which is output from the source of the N-channel MOS transistor M5 at the subsequent stage. The drains and gates of the N-channel MOS transistors M1, M2, M3, M4, and M5 are connected to each other and function as diodes.

  FIG. 6 is an operation waveform diagram in the steady state of the charge pump circuit. In the figure, V1 is the voltage at the connection point of N-channel MOS transistors M1 and M2, V2 is the voltage at the connection point of N-channel MOS transistors M2 and M3, and V3 is the voltage at the connection point of N-channel MOS transistors M3 and M4. , V4 indicates the voltage at the connection point of the N-channel MOS transistors M4 and M5. In the figure, the threshold voltage of the N-channel MOS transistor is set to 0 V for the sake of simplicity.

In this charge pump circuit, if Vt is the threshold voltage of an N-channel MOS transistor, the boosted voltage Vout is expressed by the following equation.
Vout = 5 (Vdd−Vt)
In general, in the n-stage charge pump circuit, the boosted voltage Vout is expressed by the following equation. Vout = (n + 1) (Vdd−Vt)
As prior art documents, there are the following Patent Document 1 and Non-Patent Document 1.
JP 2001-211637 A “On-chip High-Voltage Generation in NMOS Integrated Circuits Using an Improved Voltage Multiplier Technique” Of Solid State Circuit SC-11 Volume NO. 3 pages 374-378 June 1976

  In the conventional charge pump circuit, the voltage of a single power source is sequentially boosted by 1 ×, 2 ×, and 3 × to generate a desired output voltage. Therefore, in order to obtain a large output voltage, the number of stages of the charge pump is large. As a result, the number of elements, especially the number of external capacitors, has increased, leading to high costs.

  Therefore, the present invention provides a charge pump circuit capable of obtaining a desired output voltage with a smaller number of stages than in the prior art.

  The charge pump circuit according to the present invention is characterized in that the output voltage of the charge transfer element in the previous stage is used as the power supply voltage of at least one clock driver among the plurality of clock drivers.

  The charge pump circuit according to the present invention is characterized in that the voltage of the input voltage source applied to the first-stage charge transfer element is different from the power supply voltage supplied to at least one clock driver. is there.

  According to the present invention, since a desired output voltage can be obtained with a small number of charge pump stages, the number of elements of the charge pump circuit, in particular, the number of external capacitors can be reduced, and the cost of the IC can be reduced. it can. In addition to this, various power supply voltages can be combined, and the circuit efficiency can be improved when the charge pump circuit is used as a power supply circuit.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. First, the charge pump circuit according to the first embodiment will be described. FIG. 1 is a circuit diagram of a four-stage charge pump circuit.

  M1, M2, M3, M4, and M5 are five N-channel MOS transistors that are charge transfer elements connected in series, and C1, C2, C3, and C4 are four capacitors, and an N-channel MOS transistor M1 , M2, M3, M4 and M5 are connected to one terminal of capacitors C1, C2, C3 and C4.

  Reference numerals 1, 2, 3, and 4 denote clock drivers. The clock drivers 1 and 3 receive a clock pulse Φ, and the clock drivers 2 and 4 receive a clock pulse * Φ having a phase opposite to that of the clock pulse Φ. Yes. The outputs of the clock drivers 1 and 3 are applied to the other terminals of the capacitors C1 and C3, respectively, and the outputs of the clock drivers 2 and 4 are applied to the other terminals of the capacitors C2 and C4, respectively.

  Vdd is an input voltage generated from the input voltage source 15, and is applied to the drain of the first-stage N-channel MOS transistor M1. The voltage Vdd is also used as a power supply voltage for the clock drivers 1 and 2.

  Vout is an output voltage, which is output from the source of the N-channel MOS transistor M5 at the subsequent stage. The drains and gates of the N-channel MOS transistors M1, M2, M3, M4, and M5 are connected to each other and function as diodes.

  The feature of this embodiment is that the output voltage of the MOS transistor M1 in the previous stage (the voltage V1 at the connection point of the MOS transistors M1 and M2) is used as the power supply voltage of the clock driver 3, and the power supply voltage of the clock driver 4 is used. The output voltage of the preceding MOS transistor M2 (the voltage V2 at the connection point of the MOS transistors M2 and M3) is used. The high level output of the clock driver 3 becomes a voltage higher than Vdd of V1 (2 Vdd), and the high level output of the clock driver 4 becomes a higher voltage of V2 (3 Vdd). Thereby, a higher boosted voltage Vout = 8 Vdd can be obtained with the same number of stages as compared with the conventional charge pump circuit. In other words, a higher boosted voltage can be obtained with a smaller number of stages. Here, for convenience of explanation, the threshold voltages of the N-channel MOS transistors M1, M2, M3, M4, and M5 are ignored.

  FIG. 2 is an operation waveform diagram in the steady state of the charge pump circuit. In FIG. 2, V1 is the voltage at the connection point of N-channel MOS transistors M1 and M2, V2 is the voltage at the connection point of N-channel MOS transistors M2 and M3, and V3 is the connection point of N-channel MOS transistors M3 and M4. Voltage V4 indicates the voltage at the connection point of the N-channel MOS transistors M4 and M5.

  As can be understood from this figure, when the clock pulse Φ is at the low level, the clock drivers 1 and 3 output a high level, the voltage V1 is boosted to 2Vdd, and the boosted voltage V1 is the power supply of the clock driver 3. Since it is used for the voltage, the voltage V3 is boosted to 5Vdd. Further, when the clock pulse Φ is at the high level, the clock drivers 2 and 4 output the high level, the voltage V2 is boosted to 3Vdd, and the boosted voltage V2 is used as the power supply voltage of the clock driver 4, so that the voltage V4 is boosted to 8Vdd. The voltage V4 is rectified by the final-stage N-channel MOS transistor M5, and a DC voltage 8Vdd is obtained as the output voltage Vout.

  Each of the clock drivers 1, 2, 3, and 4 can be configured with a CMOS inverter. In this case, for the clock drivers 1 and 2, a P-channel MOS transistor and an N-channel MOS transistor are connected between the voltage Vdd and the ground voltage Vss. The clock driver 3 is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in series between a voltage V1 and a ground voltage Vss. The clock driver 4 is configured by connecting a P-channel MOS transistor and an N-channel MOS transistor in series between a voltage V2 and a ground voltage Vss.

  Here, since the clock pulses Φ and * Φ swing between the voltage Vdd and the ground voltage Vss, the outputs of the clock drivers 3 and 4 may not fully swing. Therefore, the clock drivers 3 and 4 are preferably composed of level shift circuits. That is, the clock driver 3 level-shifts the clock pulse φ to a clock that swings between V1 and Vss, and the clock driver 4 level-shifts the clock pulse * φ to a clock that swings between V2 and Vss.

  The N-channel MOS transistors M1, M2, M3, M4, and M5 are diode-connected. However, the present invention is not limited to this, and a switching signal may be applied to their gates. Further, the number of stages of the charge pump can be arbitrarily selected.

  Next, a charge pump circuit according to a second embodiment will be described. FIG. 3 is a circuit diagram of the four-stage charge pump circuit of the present embodiment. In FIG. 3, the same components as those in FIG. FIG. 4 is an operation waveform diagram in the steady state of the charge pump circuit. In the figure, V1 is the voltage at the connection point of N-channel MOS transistors M1 and M2, V2 is the voltage at the connection point of N-channel MOS transistors M2 and M3, and V3 is the voltage at the connection point of N-channel MOS transistors M3 and M4. , V4 indicates the voltage at the connection point of the N-channel MOS transistors M4 and M5.

  If the voltage of the input voltage source 20 is Vdd1, and the power supply voltages of the clock drivers 5, 6, 7, and 8 are Vdd2, Vdd3, Vdd4, and Vdd5, respectively, the output voltage Vout is the sum of these. Become. However, for simplicity, the N-channel MOS transistors M1, M2, M3, M4, and M5 are set to 0V.

In the conventional charge pump circuit, the voltage Vdd1 of the input voltage source 20 and the voltages of all the clock drivers are set equal to each other, but the feature of this embodiment is that Vdd1, Vdd2, Vdd3, Vdd4. , Vdd5, at least one voltage is a different voltage. For example, Vdd1 = 3V, Vdd2 = 10V,
If Vdd3 = Vdd4 = Vdd5 = 3V, Vout = 24V.

  As a result, this charge pump circuit can obtain a higher boosted voltage Vout with the same number of stages as compared with the conventional charge pump circuit. In other words, a higher boosted voltage can be obtained with a smaller number of stages.

  Also, according to this charge pump circuit, various power supply voltages can be combined, and when the charge pump circuit is used as a power supply circuit, the efficiency can be improved. For example, when the input voltage source 20 is a voltage source of 5V and an attempt is made to obtain a boosted voltage Vout of 16V, conventionally, 20V is generated by a four-stage normal charge pump circuit, and this 20V is dropped to 16V by a regulator. There must be. Then, the efficiency of the circuit (desired voltage / boosted voltage Vout × 100%) is reduced to 80%.

  On the other hand, according to the charge pump circuit of the present embodiment, two power sources of 5V and 3V can be used, so that 18V can be obtained by configuring the charge pump circuit with 5V3 stages + 3V1 stages. For example, Vdd1 = Vdd2 = Vdd3 = 5V and Vdd4 = 3V may be set. Thereby, the circuit efficiency is improved to 89%.

1 is a circuit diagram of a four-stage charge pump circuit according to a first embodiment of the present invention. FIG. 2 is an operation waveform diagram in a steady state of the charge pump circuit of FIG. 1. FIG. 4 is a circuit diagram of a four-stage charge pump circuit according to a second embodiment of the present invention. FIG. 4 is an operation waveform diagram in a steady state of the charge pump circuit of FIG. 3. It is a circuit diagram of a four-stage charge pump circuit according to a conventional example. FIG. 6 is an operation waveform diagram in a steady state of the charge pump circuit of FIG. 5.

Explanation of symbols

1,2,3,4 clock driver
5, 6, 7, 8 Clock drivers C1, C2, C3, C4 Capacitors M1, M2, M3, M4, M5 N-channel MOS transistors 15, 20 Input voltage source

Claims (4)

A plurality of charge transfer elements connected in series;
An input voltage source connected to the charge transfer element in the first stage;
A plurality of capacitors having one end connected to each connection point of the plurality of charge transfer elements;
A charge pump circuit comprising: a plurality of clock drivers that alternately supply opposite-phase clock pulses to the other ends of the plurality of capacitors;
A charge pump circuit characterized in that an output voltage of a charge transfer element at the preceding stage is used as a power supply voltage of at least one clock driver among the plurality of clock drivers. 2. The charge pump circuit according to claim 1, wherein the clock driver using the output voltage of the charge transfer element at the preceding stage as a power supply voltage is a level shift circuit. A plurality of charge transfer elements connected in series;
An input voltage source connected to the charge transfer element in the first stage;
A plurality of capacitors having one end connected to each connection point of the plurality of charge transfer elements;
A charge pump circuit comprising: a plurality of clock drivers that alternately supply opposite-phase clock pulses to the other ends of the plurality of capacitors;
The charge pump circuit according to claim 1, wherein a voltage of the input voltage source is different from a power supply voltage supplied to at least one clock driver. 4. The charge pump circuit according to claim 1, wherein the charge transfer element is composed of a MOS transistor.