JP4877334B2 - Charge pump circuit - Google Patents

Description

  The present invention relates to a charge pump circuit that boosts a DC low voltage to generate a DC high voltage.

  In recent LSIs (Large Scale Integrated Circuits), multiple power sources such as 3V, 5V, and 10V are often required inside the circuit. Conventionally, when such multiple power supplies are required, a plurality of power supplies are generated outside the LSI and supplied to the LSI. However, recently, the power supplied to the LSI is one power supply, and it is required to generate multiple power supplies inside the LSI.

  Inside the LSI, a charge pump circuit is used as a circuit for generating a voltage higher than the power supply voltage Vcc supplied from the outside. FIG. 10 is a circuit diagram showing a configuration of a conventional charge pump circuit. In this figure, reference numeral 201 is an input terminal to which a periodic pulse having a peak value Vcc and a duty of 50% is supplied, 202 is a terminal to which a power supply voltage Vcc is applied, 203 to 207 are diodes, 211 to 214 are capacitors, 220 is an inverter, 230 is an output terminal.

In such a configuration, when the input terminal 201 is at voltage 0 (ground potential), the capacitor 211 is charged to the voltage Vcc via the diode 203. Next, when the input terminal 201 becomes the voltage Vcc, one end of the capacitor 211 (the anode side of the diode 204) becomes 2Vcc, and the output of the inverter 220 becomes the voltage 0. As a result, the capacitor 212 is charged to a voltage of 2 Vcc. Next, when the input terminal 201 is again at voltage 0 and the output of the inverter 220 becomes voltage Vcc, one end of the capacitor 212 becomes voltage 3Vcc, and the capacitor 213 is charged to this voltage 3Vcc. Next, when the input terminal 201 becomes the voltage Vcc and the output of the inverter 220 becomes the voltage 0, one end of the capacitor 213 becomes the voltage 4Vcc, and the capacitor 214 is charged to this voltage 4Vcc. Next, when the input terminal 201 is at voltage 0 and the output of the inverter 220 is at voltage Vcc, one end of the capacitor 214 is at voltage 5Vcc. This voltage 5 Vcc is output to the output terminal 230 via the diode 207. The output voltage is precisely a voltage obtained by subtracting the forward drop voltage of the diodes 203 to 207.
In addition, what is described in patent document 1 is known as a prior art.

JP 2002-208290 A

By the way, in recent years, for example, in mobile phones, the size of the device has been reduced, and the battery has been further reduced in size. As a result, the output voltage of the battery has become considerably low, for example, 1V (volt). For this reason, when the power supply voltage of 1 V is to be boosted to, for example, 10 V by the above-described charge pump circuit, 10 or more blocks including one capacitor and one diode in FIG. 10 are required. However, in particular, the capacitor requires a large area inside the LSI. Therefore, it is extremely undesirable to create a large number of capacitors in the LSI because the area for creating other circuits is reduced. On the other hand, if the capacity of the capacitor is reduced to reduce the area of the capacitor, there arises a problem that the load current cannot be obtained.
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a charge pump circuit capable of making the capacitor area smaller than the conventional one. Another object of the present invention is to provide a charge pump circuit capable of taking a larger load current than the conventional one.

  The present invention has been made to solve the above-described problems. The invention according to claim 1 is directed to the first to n-th (n is a positive integer) diode elements connected in series in the forward direction, and 1st to nth pulse booster circuits provided corresponding to the 1st to nth diode elements and boosting and outputting a periodic pulse, and an output terminal of each pulse booster circuit and a connection point of each diode element N capacitors interposed therebetween, a charging current pulse booster circuit that boosts a periodic pulse and outputs the boosted pulse to the first diode, and the periodic pulse obtained at an input terminal is the first, third,... .., And a circuit that inverts the periodic pulse and supplies the inverted pulse to the second, fourth,... Pulse booster circuits and the charge current pulse booster circuit. A charge pump circuit.

  The invention according to claim 2 is provided corresponding to the first to n-th (n is a positive integer) diode elements connected in series in the forward direction, and the first to n-th diode elements. 1st to n-th pulse booster circuit for boosting and outputting a pulse, n capacitors interposed between the output terminal of each pulse booster circuit and the connection point of each diode element, and boosting a periodic pulse And supplying the charging current pulse booster circuit to be output to the first diode and the periodic pulse obtained at the input terminal to the first, third,... Pulse booster circuit and inverting the periodic pulse. Are connected in series in the forward direction with the second, fourth,... Pulse booster circuit and the first circuit supplying the charge current pulse booster circuit, and the (n + 1) th diode element is the nth Nth (n +) connected to the diode element ) To m-th (m is a positive integer greater than n) diode element, and (n + 1) to m-th capacitors having one end connected to the connection point of each of the (n + 1) -th to m-th diode elements. The periodic pulse obtained at the input terminal or the inverted periodic pulse obtained by inverting the periodic pulse is supplied to the other ends of the (n + 1) th, (n + 3),... Capacitors, and at the inverted periodic pulse or the input terminal. And a second circuit for supplying the obtained periodic pulse to the other ends of the (m + 2) th, (m + 4) th,... Capacitors.

  The invention according to claim 3 is provided corresponding to the first to nth (n is a positive integer) diode elements connected in series in the forward direction and the first to nth diode elements. First to nth pulse booster circuits that boost and output pulses, first to nth capacitors interposed between the output terminals of the pulse booster circuits and the diode elements, and boost periodic pulses A charge current pulse booster circuit for outputting to the first diode, and a first periodic pulse obtained at a first input terminal to the first, third,... Pulse booster circuit, A circuit that inverts the first periodic pulse and supplies the inverted pulse to the second, fourth,... Pulse booster circuit and the charge current pulse booster circuit; a first output capacitor; a second output capacitor; When the second periodic pulse obtained at the input terminal is at ground level The first output capacitor is charged by the charge of the nth capacitor, and a voltage obtained by adding a power supply voltage to the charge voltage of the second output capacitor is output to an output terminal, and the second periodic pulse is A charging circuit for charging the second output capacitor with the charge of the n-th capacitor at a power supply voltage level and outputting a voltage obtained by adding the power supply voltage to the charge voltage of the first output capacitor to an output terminal; A charge pump circuit comprising:

  According to a fourth aspect of the present invention, in the charge pump circuit according to any one of the first to third aspects, the pulse booster circuit includes a capacitor when the input periodic pulse is at the first level. The first level and the voltage obtained by adding the power supply voltage to the charging voltage of the capacitor are alternately output according to the change of the periodic pulse at the input terminal that repeats the first and second levels. And a switching circuit for outputting to a terminal.

According to a fifth aspect of the present invention, in the charge pump circuit according to the fourth aspect, the switching circuit includes first and second amplifying elements having different conductivity types connected in series.
According to a sixth aspect of the present invention, in the charge pump circuit according to the fifth aspect, the first periodic pulse that repeats the first and second levels and a rising time slightly earlier than a rising edge of the first periodic pulse. A pulse generation circuit for outputting a second periodic pulse that falls slightly later than the falling edge of the first periodic pulse, and the first and second amplifying elements are respectively connected to the first and second periodic pulses. It is characterized by driving by.

  As described above, according to the present invention, there is an effect that the area of the capacitor can be made smaller than that of the conventional one. Further, according to the invention of claim 3, an effect that a load current higher than that of the conventional one can be obtained is also obtained.

1 is a block diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention. It is a block diagram which shows the structure of the charge pump circuit by 2nd Embodiment of this invention. It is a block diagram which shows the structure of the charge pump circuit by 3rd Embodiment of this invention. FIG. 2 is a circuit diagram showing a first configuration example of a pulse booster circuit 102 in FIG. 1. FIG. 3 is a circuit diagram showing a second configuration example of the pulse booster circuit 102 in FIG. 1. FIG. 6 is a circuit diagram showing a third configuration example of the pulse booster circuit 102 in FIG. 1. FIG. 7 is a timing chart for explaining the operation of the pulse generation circuit 20 in FIG. 6. It is a circuit diagram which shows the specific example of the pulse generation circuit 20 in FIG. FIG. 6 is a circuit diagram showing a fourth configuration example of the pulse booster circuit 102 in FIG. 1. It is a circuit diagram which shows the structural example of the conventional charge pump circuit.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a configuration of a charge pump circuit according to a first embodiment of the present invention. In FIG. 1, symbol INa is an input terminal to which a peak value Vcc (power supply voltage) and a rectangular periodic pulse with a duty ratio of 50% are input, and is connected to the input terminal of the pulse booster circuit 102 and is connected to the inverter 103. To the input terminals of the pulse booster circuits 104 and 105. The pulse boosting circuits 102, 104, and 105 are the same circuit, and boost and output the input periodic pulse having a peak value Vcc to a peak value 2Vcc. That is, the pulse booster circuit 102 outputs a periodic pulse having the same phase as the periodic pulse supplied to the input terminal INa and a peak value of 2 Vcc, and the pulse boosting circuits 104 and 105 are opposite in phase to the periodic pulse supplied to the input terminal INa. A periodic pulse with a peak value of 2 Vcc is output in the phase.

  FIG. 4 is a circuit diagram showing a specific configuration of the pulse booster circuit 102 (104, 105). In this figure, symbol IN is an input terminal to which a rectangular periodic pulse having a peak value Vcc and a duty ratio of 50% is input, and the periodic pulse input to this input terminal IN is inverted by an inverter 8 and FET ( To the gate of the field effect transistor 3). The FET 3 is an N-channel FET, the drain thereof is connected to the power supply voltage Vcc, the source is connected to the input terminal IN via the capacitor 4, and is connected to the gate of the FET 5. The FET 5 is an N-channel FET, its drain is connected to the power supply voltage Vcc, and its source is connected to one end of the capacitor 6 and the source of the FET 7. The inverter 8 inverts the periodic pulse at the input terminal IN and outputs it to the other end of the capacitor 6. FET 7 and FET 9 are respectively a P-channel and an N-channel FET, and the gates and drains of these FETs 7 and 9 are connected in common, thereby constituting an inverter. The gates of the FETs 7 and 9 are connected to the input terminal IN, the drain is connected to the output terminal OUT, and the source of the FET 9 is grounded.

In such a configuration, when the voltage of the input terminal IN is “H” (high level = Vcc), the output of the inverter 8 is “L” (low = ground potential), and the FET 3 is turned off. At this time, “H” of the input terminal IN is supplied to the gate of the FET 5 through the capacitor 4 and the FET 5 is turned on. Here, as will be described later, since the connection point A is charged to Vcc−Vth (Vth is the threshold value of the FET 3) in advance, the connection point B becomes 2Vcc−Vth, which is higher than Vcc. Becomes triode operation.
When the FET 5 is turned on, the voltage Vcc is charged to the capacitor 6 via the FET 5. At this time, “H” is applied to the gates of the FETs 7 and 9, whereby the FET 9 is turned on, the FET 7 is turned off, and the output terminal OUT becomes the ground potential. At this time, the voltage at the connection point A is Vcc-Vth, which is lower than Vcc.

  Next, when the input terminal IN becomes “L”, the output of the inverter 8 becomes “H”, and the FET 3 is turned on. As a result, the charging current of the capacitor 4 flows from the FET 3, the gate of the FET 5 becomes “L”, and the FET 5 is turned off. At this time, since the voltage Vcc is charged in the capacitor 6, when the output of the inverter 8 becomes “H”, the voltage at the connection point B becomes 2 Vcc. At this time, the FET 7 is turned on and the FET 9 is turned off, so that the voltage 2Vcc is output from the output terminal OUT.

Next, when the input terminal IN becomes “H” again, the output terminal OUT becomes the ground potential again, and the capacitor 6 is charged. When the input terminal IN becomes “L”, the output terminal OUT becomes the voltage 2Vcc. Thereafter, this operation is repeated.
Thus, according to the pulse booster circuit of the above embodiment, the periodic pulse with the peak value Vcc can be converted into the periodic pulse with the peak value 2Vcc.

  Next, referring back to FIG. 1, reference numerals 106 and 107 are capacitors each having one end connected to each output terminal of the pulse booster circuits 102 and 104. Reference numerals 110 to 112 denote diodes, the anode of the diode 110 is connected to the output terminal of the pulse booster circuit 105, the cathode of the diode 110 is connected to the anode of the diode 111 and the other end of the capacitor 106, and the cathode of the diode 111 is connected to the diode 112. And the cathode of the diode 112 are connected to the output terminal OUTa.

Next, the operation of the circuit shown in FIG. 1 will be described.
First, when the input terminal INa becomes a voltage 0 (ground potential), the output voltage of the pulse booster circuit 102 becomes 0, the output of the pulse booster circuit 105 becomes 2Vcc, and the capacitor 106 is charged to the voltage 2Vcc via the diode 110. . Actually, the diode 110 is charged to a voltage lower than the power supply voltage Vcc by the forward drop voltage of the diode 110. Here, the forward drop voltage of the diode is assumed to be 0 for simplification of description. Next, when the input terminal INa becomes the voltage Vcc, the output voltage of the pulse booster circuit 102 becomes the voltage 2Vcc, and as a result, the voltage at the point C1 (the anode voltage of the diode 111) becomes 4Vcc. At this time, the voltage of the inverter 103 becomes 0, and the output voltage of the pulse booster circuit 104 becomes 0. As a result, the capacitor 107 is charged by the voltage 4Vcc at the point C1, while the capacitor 106 is discharged. Next, when the voltage at the input terminal INa becomes 0, the capacitor 106 is charged. When the voltage at the input terminal INa becomes Vcc, the capacitor 107 is charged and the capacitor 106 is discharged. As a result, the charging voltage of the capacitor 107 becomes 4 Vcc.

  When the voltage of the input terminal INa becomes 0 and the output of the inverter 103 becomes Vcc, the output voltage of the pulse booster circuit 104 becomes 2Vcc. As a result, the charging voltage of the capacitor 107 is added to the output voltage of the pulse booster circuit 104. The voltage at the point C2 (the anode voltage of the diode 112) is 6Vcc. The voltage 6Vcc is output to the output terminal OUTa via the diode 112. When the voltage of the input terminal INa becomes Vcc and the output of the inverter 103 becomes 0, the output voltage of the pulse booster circuit 104 becomes 0. As a result, the voltage at the point C2 becomes 4Vcc. To the output terminal OUTa.

The above is the operation of the first embodiment of the present invention. By the way, each of the capacitors 211 to 214 in the circuit of FIG. 10 requires an area of 3000 μm ^2. Therefore, to create the circuit of FIG. 10 in an LSI, an area of 12000 μm ² is required for the capacitor. . In contrast, it requires an area of each 500 [mu] m ² and 1000 .mu.m ² to the capacitor 4, 6 of Figure 4, also, the capacitor 106 and 107 in FIG. 1 requires an area of 1000 .mu.m ^2. As a result, in order to configure the circuit of FIG.
The area of 1500 × 3 + 1000 + 1000 = 6500 μm ² is sufficient.
In the above embodiment, two pairs of diodes, capacitors and pulse booster circuits (a pair of reference numerals 110, 106 and 102 and a pair of reference numerals 111, 107 and 104) are provided. Of course, a larger number of sets may be provided according to the above.

Next explained is the second embodiment of the invention.
FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention. The embodiment shown in this figure can take more load current than the embodiment shown in FIG. In this figure, parts corresponding to those in FIG. 1 are denoted by the same reference numerals. The circuit shown in this figure is different from the circuit shown in FIG. 1 in that a capacitor 108 interposed between the input terminal INa and the cathode of the diode 112 and an insertion between the cathode of the diode 112 and the output terminal OUTa. The diode 113 is provided.

  According to such a configuration, when the voltage at the input terminal INa is 0, the voltage at the point C2 (the anode of the diode 113) becomes 6Vcc as described above, and this voltage is charged in the capacitor 108. The voltage is output to the output terminal OUTa via the diode 113. When the voltage at the input terminal INa becomes Vcc, the voltage at the point C3 becomes 7Vcc, and the voltage at the point C3 is output to the output terminal OUTa through the diode 113.

Here, if the capacitor 108 is configured with an area of 2000 μm ² , the area of all the capacitors becomes 8500 μm ² , which is about 70% of the area of the circuit of FIG. According to this circuit, the same load current as that of the conventional circuit shown in FIG. 10 can be obtained.

  In the above embodiment, a pair of a diode and a capacitor is provided at the back of the point C2 in the first embodiment shown in FIG. 1, but a plurality of diodes and capacitors are further provided at the back of the point C3 in FIG. A set may be provided. In this case, of course, every other periodic pulse supplied to the capacitor reverses the phase.

Next explained is the third embodiment of the invention.
FIG. 3 is a circuit diagram showing the configuration of the third embodiment of the present invention. The embodiment shown in this figure improves the embodiment shown in FIG. 2 so that a load current can be obtained more than that shown in FIG. It is a thing.

  The embodiment shown in this figure is different from that shown in FIG. 2 in that diodes 115 to 118, capacitors 120 and 121, an inverter 123, and an input terminal INb are provided in place of the diodes 112 and 113 and the capacitor 108 in FIG. Is a point. That is, the anodes of the diodes 115 and 117 are both connected to the cathode of the diode 111, the cathode of the diode 115 and the anode of the diode 116 are connected, and one end of the capacitor 120 is connected to the connection point. The anode of the diode 118 is connected, and one end of the capacitor 121 is connected to the connection point. The cathodes of the diodes 116 and 117 are both connected to the output terminal OUTa, and the input terminal of the inverter 123 is connected to the input terminal INb. In addition, the other end of the capacitor 120 is connected, and the output end of the inverter 123 is connected to the other end of the capacitor 121. Here, to the input terminal INb, a periodic pulse having a peak value Vcc (power supply voltage) and a duty cycle of 50% and a frequency of 1/3 of the frequency of the periodic pulse of the input terminal INa is input.

Next, the operation of the above-described third embodiment will be described.
As described in FIG. 1, when the input terminal INa is at Vcc, the capacitor 107 is charged with the voltage 4Vcc, and when the input terminal INa becomes 0, the output of the pulse booster circuit 104 becomes 2Vcc. Becomes 6Vcc. When the voltage at the input terminal INb is 0, the capacitor 120 is charged by the voltage at the point C2. Next, when the input terminal INa becomes Vcc, the capacitor 107 is charged, and when the input terminal INa becomes 0, the capacitor 120 is charged again by the charge of the capacitor 107.

  When charging of the capacitor 120 is repeated three times, the input terminal INb becomes Vcc. As a result, the voltage at the point C3 (the anode voltage of the diode 116) becomes 7Vcc which is the sum of the voltage Vcc and the charging voltage 6Vcc of the capacitor 120, and this voltage is output to the output terminal OUTa via the diode 116. At this time, the output of the inverter 123 becomes 0, and the capacitor 121 is charged by the charge of the capacitor 107. When charging of the capacitor 121 by the charge of the capacitor 107 is repeated three times, the input terminal INb becomes 0, the voltage at one end of the capacitor 121 is output to the output terminal OUTa via the diode 118, and the capacitor 120 is charged. Thereafter, the above-described process is repeated.

  According to the third embodiment described above, a larger load current can be obtained than in the circuit of FIG. In other words, the circuit of FIG. 1 has a voltage whose output fluctuates. Therefore, in order to use it as a direct current, it is naturally necessary to add a capacitor to the load circuit and smooth it. A large load current cannot be taken from a power supply smoothed by a capacitor. On the other hand, in the circuit of FIG. 3, the voltages of the capacitors 120 and 121 are alternately output to the output terminal OUTa every half cycle of the input terminal INb. As a result, a larger load current can be obtained as compared with the circuit of FIG.

  In the third embodiment, the frequency of the periodic pulse at the input terminal INb is 1/3 of the frequency of the periodic pulse at the input terminal INa. However, this is not limited to 1/3. For example, 1/2 or 1/5 may be used.

Next, another configuration example of the pulse booster circuit 102 (104, 105) will be described.
FIG. 5 is a circuit in which the configuration of FIG. 4 is further simplified. In this figure, the periodic pulse input to the input terminal IN is inverted by the inverter 11 and supplied to one end of the capacitor 12. The drain of the N-channel FET 13 is connected to the power supply voltage Vcc, the gate is connected to the drain, and the source is connected to the other end of the capacitor 12 and the source of the P-channel FET 14. The FET 14 and the N-channel FET 15 constitute an inverter, the voltage of the input terminal IN is applied to the connection point of each gate, and the connection point of each drain is connected to the output terminal OUT.

In such a configuration, when the voltage of the input terminal IN is “H”, the output of the inverter 11 is “L”. As a result, the voltage (Vcc−Vth) is charged to the capacitor 12 via the FET 13. Here, the voltage Vth is a gate-source voltage of the FET 13 and is about 0.7V. At this time, the FET 14 is turned off, the FET 15 is turned on, and the output terminal OUT becomes the ground potential. Next, when the input terminal IN becomes “L”, the output of the inverter 11 becomes “H”, and as a result, the source voltage of the FET 14 becomes Vcc + (Vcc−Vth) = 2Vcc−Vth. At this time, the FET 13 is reverse-biased between the source and the drain and cut off. At this time, the FET 14 is turned on and the FET 15 is turned off, so that the voltage (2Vcc−Vth) is output from the output terminal OUT.

  FIG. 6 is a circuit diagram showing still another configuration example of the pulse booster circuit 102. In this figure, parts corresponding to those in FIG. 4 are denoted by the same reference numerals. In the circuit of FIG. 4, a one-phase periodic pulse is supplied to the input terminal IN, and this periodic pulse is input to the gates of the FETs 7 and 9. However, in such a configuration, there is a possibility that a through current that passes through the FETs 7 and 9 flows when the FETs 7 and 9 are switched on / off. Therefore, this circuit is provided with a pulse generation circuit 20 that generates two-phase periodic pulses P1 and P2 having a peak value Vcc based on the periodic pulse at the input terminal IN. FIG. 7 is a waveform diagram of the two-phase periodic pulses P1 and P2 output from the pulse generation circuit 20. As shown in this figure, after the periodic pulse P2 rises, the periodic pulse P1 rises after a lapse of a minute time, and the period After the pulse P1 falls, the periodic pulse P2 falls after a minute time. Periodic pulses P1 and P2 are input to the gates of the FETs 9 and 7, respectively. The pulse generation circuit 20 is a known circuit, and an example thereof is shown in FIG. In this figure, reference numerals 31 to 38 denote inverters, and reference numerals 41 and 42 denote NAND gates.

  In this circuit, a P-channel FET 21 and an N-channel FET 22 are provided instead of the inverter 8 in FIG. 4, a periodic pulse P2 is applied to the gate of the FET 21, the source is connected to the power supply voltage Vcc, and the drain is connected to the drain of the FET 22. In addition, a periodic pulse P1 is applied to the gate of the FET 22, and the source of the FET 22 is grounded. A capacitor 6 is connected between the common drain of the FETs 21 and 22 and the source of the FET 7. Further, the respective substrates of the FETs 7 and 21 are connected to the respective sources.

  According to such a configuration, after the periodic pulse P1 becomes “L” and the FET 9 is turned off, the periodic pulse P2 becomes “L” and the FET 7 turns on, and the periodic pulse P2 becomes “H”. After the FET 7 is turned off, the periodic pulse P1 becomes “H” and the FET 9 is turned on. As a result, no through current flows through the FETs 7 and 9.

FIG. 9 is a circuit diagram showing still another configuration example of the pulse booster circuit 102. In this figure, portions corresponding to the respective portions in FIG. 5 are denoted by the same reference numerals. The pulse booster circuit shown in this figure is a circuit for preventing the through current of the FETs 14 and 15 in the circuit shown in FIG. That is, similarly to FIG. 6, a pulse generation circuit 20 that outputs a two-phase periodic pulse is provided, and periodic pulses P1 and P2 are input to the gates of the FETs 15 and 14, respectively. Further, a P-channel FET 24 and an N-channel FET 25 are provided in place of the inverter 11 of FIG. 5, a periodic pulse P2 is applied to the gate of the FET 24, the source of the FET 24 is connected to the power supply voltage Vcc, and the drain is connected to the drain of the FET 25. The periodic pulse P1 is applied to the gate of the FET 25, and the source of the FET 25 is grounded. The capacitor 12 is connected between the common drain of the FETs 24 and 25 and the source of the FET 4.
And this circuit can also prevent the through currents of the FETs 14 and 15 as in the circuit of FIG.

  In the first to third embodiments described above, only two sets of blocks (blocks corresponding to the diodes 110 and 111) including a diode, a pulse booster circuit, and a capacitor are provided. Needless to say, a larger number is provided according to the output voltage.

102, 104, 105 ... pulse booster circuits 103, 123 ... inverters 106, 107, 108, 120, 121 ... capacitors 110-113, 115-118 ... diodes INa, INb ... input terminals, OUTa ... output terminals

Claims (8)

A plurality of first diode elements connected in series in the forward direction;
A first capacitor provided at each first connection point between the first diode elements and having one end connected to the first connection point;
A pulse booster circuit provided for each of the first capacitors and connected to the other end of the first capacitor;
A charging current pulse booster circuit connected to the terminal end on the anode side in the series connection of the first diode elements,
The odd-numbered pulse booster circuit among the plurality of pulse booster circuits receives a first periodic pulse as an input pulse, boosts the input pulse, and outputs it to the other end of the connected first capacitor. ,
The even-numbered pulse booster circuit among the plurality of pulse booster circuits receives an inverted periodic pulse obtained by inverting the first periodic pulse as the input pulse, boosts the input pulse, and connects the connected first Output to the other end of the capacitor
In the charging current pulse booster circuit, an inversion period pulse obtained by inverting the first period pulse is input as the input pulse, and the input pulse is stepped up in series connection of the connected first diode elements. Output to the anode end,
The boosted voltage is output from the cathode-side termination in the series connection of the plurality of first diode elements,
The pulse boosting circuit and the charging current pulse boosting circuit are:
A pulse generation circuit for outputting a second periodic pulse and a third periodic pulse which are two-phase periodic pulses from the input pulse;
A first P-channel FET having a source connected to a power supply terminal and a gate receiving the third periodic pulse;
A first N-channel FET having a drain connected to a drain of the first P-channel FET, a source grounded, and a gate receiving the second periodic pulse;
A second N-channel FET whose drain and gate are connected to the power supply terminal;
A second capacitor having one end connected to the drain of the first P-channel FET and the other end connected to the source of the second N-channel FET;
A second P-channel FET having a source connected to the other end of the second capacitor and a gate receiving the third periodic pulse;
A third N-channel FET, the drain of which is connected to the drain of the second P-channel FET, the second periodic pulse is input to the gate, and the source is grounded,
The pulse generation circuit is
When the third periodic pulse is at the H level, the second capacitor is charged through the second N-channel FET, and when the third periodic pulse is at the L level, the second capacitor is charged. When the source voltage of the second P-channel FET is boosted using the measured voltage, the second capacitor is charged by turning on the second P-channel FET and the third N-channel FET at the same time. because it was not to discharge the charge, and the state of the third period pulse is L level, so that the second periodic pulse and the state is at the H level do not occur at the same time, the second periodic pulse, the second 3 of the periodic pulse causes reluctant Tachinobo to H level after the rises to the H level, said third periodic pulse, under stand L level after the second period pulse falls to the L level is al A charge pump circuit, characterized in that that. At least one second diode element connected in series in the forward direction to a cathode-side end in the series connection of the plurality of first diode elements;
At least one third capacitor provided for each of the second diode elements and having one end connected to the anode of the second diode element;
With
The first periodic pulse is inputted to the other end of the odd-numbered third capacitor in combination with the pulse booster circuit and the third capacitor,
The inversion cycle pulse is input to the other end of the third capacitor that is even-numbered together with the pulse booster circuit and the third capacitor,
2. The charge pump circuit according to claim 1, wherein a boosted voltage is output from a cathode-side termination in a series connection of the plurality of first diode elements and the second diode element. A third diode element having an anode connected to an end on the cathode side in the series connection of the first diode elements;
A fourth diode element having an anode connected to an anode of a final-stage diode element that is a final stage on the cathode side in the series connection of the first diode elements;
A fifth diode element having an anode connected to the cathode of the fourth diode element and a cathode connected to the cathode of the third diode element;
A first output capacitor having one end connected to a connection point between the final-stage diode element and the third diode element;
A second output capacitor having one end connected to a connection point between the fourth diode element and the fifth diode element;
A fourth periodic pulse is input to the other end of the first output capacitor,
The charge pump circuit according to claim 1, wherein the fourth periodic pulse is inverted and input to the other end of the second output capacitor. A plurality of first diode elements connected in series in the forward direction;
A first capacitor provided at each first connection point between the first diode elements and having one end connected to the first connection point;
A pulse booster circuit provided for each of the first capacitors and connected to the other end of the first capacitor;
A charging current pulse booster circuit connected to the anode-side termination in the series connection of the first diode elements;
At least one second diode element connected in series in the forward direction to a cathode-side end in the series connection of the plurality of first diode elements;
At least one third capacitor provided for each of the second diode elements, having one end connected to the anode of the second diode element and having a larger capacitance than the first capacitor;
With
The odd-numbered pulse booster circuit among the plurality of pulse booster circuits receives a first periodic pulse as an input pulse, boosts the input pulse, and outputs it to the other end of the connected first capacitor. ,
The even-numbered pulse booster circuit among the plurality of pulse booster circuits receives an inverted periodic pulse obtained by inverting the first periodic pulse as the input pulse, boosts the input pulse, and connects the connected first Output to the other end of the capacitor
In the charging current pulse booster circuit, an inversion period pulse obtained by inverting the first period pulse is input as the input pulse, and the input pulse is stepped up in series connection of the connected first diode elements. Output to the anode end,
The boosted voltage is output from the cathode-side termination in the series connection of the plurality of first diode elements,
The first periodic pulse is inputted to the other end of the odd-numbered third capacitor in combination with the pulse booster circuit and the third capacitor,
The inversion cycle pulse is input to the other end of the third capacitor that is even-numbered together with the pulse booster circuit and the third capacitor,
A charge pump circuit, wherein a boosted voltage is output from a cathode-side termination in a series connection of the plurality of first diode elements and the second diode element. A plurality of first diode elements connected in series in the forward direction;
A first capacitor provided at each first connection point between the first diode elements and having one end connected to the first connection point;
A pulse booster circuit provided for each of the first capacitors and connected to the other end of the first capacitor;
A charging current pulse booster circuit connected to the anode-side termination in the series connection of the first diode elements;
A third diode element having an anode connected to an end on the cathode side in the series connection of the first diode elements;
A fourth diode element having an anode connected to an anode of a final-stage diode element that is a final stage on the cathode side in the series connection of the first diode elements;
A fifth diode element having an anode connected to the cathode of the fourth diode element and a cathode connected to the cathode of the third diode element;
A first output capacitor having one end connected to a connection point between the final-stage diode element and the third diode element and having a larger capacitance than the first capacitor;
A second output capacitor having one end connected to a connection point between the fourth diode element and the fifth diode element and having a larger capacitance than the first capacitor;
With
The odd-numbered pulse booster circuit among the plurality of pulse booster circuits receives a first periodic pulse as an input pulse, boosts the input pulse, and outputs it to the other end of the connected first capacitor. ,
The even-numbered pulse booster circuit among the plurality of pulse booster circuits receives an inverted periodic pulse obtained by inverting the first periodic pulse as the input pulse, boosts the input pulse, and connects the connected first Output to the other end of the capacitor
In the charging current pulse booster circuit, an inversion period pulse obtained by inverting the first period pulse is input as the input pulse, and the input pulse is stepped up in series connection of the connected first diode elements. Output to the anode end,
A fourth periodic pulse is input to the other end of the first output capacitor,
The charge pump circuit, wherein the fourth periodic pulse is inverted and input to the other end of the second output capacitor. The pulse boosting circuit and the charging current pulse boosting circuit are:
A pulse generation circuit for outputting a second periodic pulse and a third periodic pulse which are two-phase periodic pulses from the input pulse;
A first P-channel FET having a source connected to a power supply terminal and a gate receiving the third periodic pulse;
A first N-channel FET having a drain connected to a drain of the first P-channel FET, a source grounded, and a gate receiving the second periodic pulse;
A second N-channel FET whose drain and gate are connected to the power supply terminal;
A second capacitor having one end connected to the drain of the first P-channel FET and the other end connected to the source of the second N-channel FET;
A second P-channel FET having a source connected to the other end of the second capacitor and a gate receiving the third periodic pulse;
A third N-channel FET, the drain of which is connected to the drain of the second P-channel FET, the second periodic pulse is input to the gate, and the source is grounded;
The charge pump circuit according to claim 4, wherein the charge pump circuit includes: The pulse boosting circuit and the charging current pulse boosting circuit are:
A pulse generation circuit for outputting a second periodic pulse and a third periodic pulse which are two-phase periodic pulses from the input pulse;
A first P-channel FET having a source connected to a power supply terminal and a gate receiving the third periodic pulse;
A first N-channel FET having a drain connected to a drain of the first P-channel FET, a source grounded, and a gate receiving the second periodic pulse;
A second N-channel FET whose drain and gate are connected to the power supply terminal;
A second capacitor having one end connected to the drain of the first P-channel FET and the other end connected to the source of the second N-channel FET;
A second P-channel FET having a source connected to the other end of the second capacitor and a gate receiving the third periodic pulse;
6. A third N-channel FET having a drain connected to a drain of the second P-channel FET, a gate receiving the second periodic pulse, and a source grounded. The charge pump circuit described. The pulse boosting circuit and the charging current pulse boosting circuit are:
A fourth capacitor in which the input pulse is input to one end and the other end is connected to a second connection point;
A fifth capacitor in which an inverted input pulse obtained by inverting the input pulse is input to one end and the other end is connected to a third connection point;
A first N-channel FET having a drain connected to a power supply terminal, a source connected to the second connection point, and a gate to which the inverted input pulse is input;
A second N-channel FET having a drain connected to a power supply terminal, a source connected to the third connection point, and a gate connected to the second connection point;
A switching circuit connected to the third connection point and alternately outputting a potential obtained by adding a power supply voltage to the charging voltage of the fifth capacitor and a ground potential in response to the input pulse. 6. The charge pump circuit according to claim 4, wherein the charge pump circuit is characterized.

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