KR20050000208A - Method for removing tungsten contamination in semiconductor device employing tungsten/polysilicon gate - Google Patents

Method for removing tungsten contamination in semiconductor device employing tungsten/polysilicon gate Download PDF

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KR20050000208A
KR20050000208A KR1020030040809A KR20030040809A KR20050000208A KR 20050000208 A KR20050000208 A KR 20050000208A KR 1020030040809 A KR1020030040809 A KR 1020030040809A KR 20030040809 A KR20030040809 A KR 20030040809A KR 20050000208 A KR20050000208 A KR 20050000208A
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gate
polysilicon
tungsten
semiconductor device
nitride film
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KR1020030040809A
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Korean (ko)
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KR100968420B1 (en
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홍병섭
오재근
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28247—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon passivation or protection of the electrode, e.g. using re-oxidation

Abstract

PURPOSE: A method for removing tungsten residues of a semiconductor device with a tungsten/polysilicon gate is provided to prevent degradation and junction leakage of a gate oxide layer by blocking the outgassing of tungsten before depositing a gate sealing nitride layer and to compensate the thickness of a lost hard mask by depositing additionally a PE(Plasma Enhanced) silicon nitride layer. CONSTITUTION: A gate pattern including a polysilicon layer(2) and a tungsten film(3) is formed on a substrate, and a hard mask(4) is formed on the gate pattern. To compensate the damage of gate edges, a gate bird's beak(6) is formed at the lower edges of the polysilicon layer by selective oxidation. Tungsten residues generated in the selective oxidation are removed by wet etching solutions. A gate sealing nitride layer(7) is then formed on the resultant structure in order to prevent abnormal oxidation of W. A PE-SiN layer(5) is covered on the gate pattern.

Description

텅스텐/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법{Method for removing tungsten contamination in semiconductor device employing tungsten/polysilicon gate}Method for removing tungsten contamination in semiconductor device employing tungsten / polysilicon gate}

본 발명은 저저항 게이트전극인 W/WN/폴리실리콘 전극을 채용하는 0.13㎛ 이하의 기가급 DRAM 반도체소자 특성에서 가장 중요한 특성인 리프레쉬 시간(Refresh time)을 향상시키는 방법에 관한 것으로, 특히 W/WN/폴리실리콘 전극을 사용하는 제품에서 GIDL특성을 확보하기 위하여 반드시 필요한 선택적 산화공정후 후속공정에서 W의 이상산화를 방지하기 위하여 증착되는 게이트 실링 질화막 증착공정 직전에 열이력에 의해 발생하는 W의 아웃개싱(outgassing)을 근본적으로 차단하여 W 오염에 의하여 유발되는 게이트 산화막의 열화와 접합누설을 감소시켜 리프레쉬 특성을 향상시키는 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for improving the refresh time, which is the most important characteristic of a Giga-class DRAM semiconductor device having a low resistance gate electrode of W / WN / polysilicon electrode of 0.13 μm or less, in particular, W / WN / polysilicon electrode. In the products using WN / polysilicon electrode, the W generated by thermal history immediately before the gate sealing nitride film deposition process is deposited to prevent abnormal oxidation of W in the subsequent process after the selective oxidation process which is essential for securing GIDL characteristics. The present invention relates to a method of fundamentally blocking outgassing to reduce deterioration and junction leakage of a gate oxide film caused by W contamination, thereby improving refresh characteristics.

종래의 저저항 게이트전극인 W/WN/폴리실리콘 게이트전극을 채용하는 DRAM 반도체소자의 데이타 보존시간(retention time) 특성 저하의 문제점은 설명하면 다음과 같다. W/WN/폴리실리콘(도2의 참조부호4/3/2)을 사용하는 제품에서 GIDL특성을 확보하기 위하여 반드시 필요한 게이트 버즈비크(도2의 참조부호 6)를 형성하기 위하여 W/Si의 선택적 산화공정을 실시하는데 이 선택적 산화 공정 진행시 W과 H2O의 반응으로 WH2O4라는 W기체가 발생하고 이 W기체에 의하여 선택산화 장비와 웨이퍼의 표면을 오염시켜 이에 의해 게이트 엣지부나 실리콘기판에 W오염을 야기하여 게이트 채널이나 셀 접합영역에 트랩 사이트나 WSix와 같은 결함등이 생성되어 이들을 통한 접합누설이 커져 반도체소자의 리프레쉬 특성을 저하시키는 결과를 가져온다. 현재 0.13㎛ 이하 제품에서의 게이트 이후 공정 절차에서는 이 선택적 산화공정 전후에 W 오염을 제거하기 위하여 황산계 화학용액이나 불산계열 용액으로 후세정 처리를 하여 W을 녹여내는 방법으로 W 오염수치를 2자리수 정도 낮추고 있으나, 오염되지 않은 경우에 비하여 여전히 2자리수 정도 높은 수치를 유지하고 있다(도1 참조). 또한, 후속공정에서 W의 이상산화를 방지하기 위하여 증착되는 게이트 실링 질화막(도2의 참조부호7) 증착공정중에서도 증착전 열이력에 의하여 추가 오염이 진행되고 있으나, 후속 질화막이 바로 증착되므로 오염된 W이 그대로 표면에 잔존하게 되어 후속 고온 열공정시 W에 의한 채널이나 접합에서의 문제를 야기시킬 수 있다.Problems of deterioration of data retention time characteristics of a DRAM semiconductor device employing a W / WN / polysilicon gate electrode, which is a conventional low resistance gate electrode, will be described below. In products that use W / WN / polysilicon (ref. 4/3/2 in Fig. 2), W / Si may be used to form a gate burj beak (ref. 6 in Fig. 2), which is essential for securing GIDL characteristics. In the selective oxidation process, a W gas called WH 2 O 4 is generated by the reaction between W and H 2 O, which contaminates the surface of the selective oxidation equipment and the wafer by the W gas. W contamination occurs on the silicon substrate, and defects such as trap sites and WSix are generated in the gate channel or the cell junction region, resulting in increased junction leakage, thereby lowering the refresh characteristics of the semiconductor device. In the post-gate process process for products below 0.13㎛, the W contamination value is double digitized by post-treatment with sulfuric acid chemical solution or hydrofluoric acid solution to remove W contamination before and after this selective oxidation process. It is lowering the degree, but still maintains a two-digit number higher than the case without contamination (see Fig. 1). Further, during the deposition process of the gate sealing nitride film (reference numeral 7 of FIG. 2) which is deposited to prevent abnormal oxidation of W in the subsequent process, further contamination is progressed by the thermal history before deposition, but the subsequent nitride film is immediately deposited and contaminated. W remains on the surface as it is, and may cause problems in channels or junctions by W during subsequent high temperature thermal processes.

본 발명은 상기 문제점을 해결하기 위한 것으로써, 저저항 게이트전극인 W/WN/폴리실리콘 게이트 식각후 선택 산화 공정 실시 직후에 화학기상증착법(LPCVD)에 의한 게이트 실링 질화막을 증착하기전 오염된 W원소를 황산계열 및 불산계열 화학용액으로 제거한 후, W 아웃개싱(outgassing)이 일어나지 않는 저온의 플라즈마 인핸스드(plasma enhanced) 실리콘질화막(PE-SiN)을 증착하여 패터닝된 W/폴리실리콘 게이트를 감싸서 후속 고온의 LPCVD법에 의한 게이트 실링 질화막 증착전 공정에 의하여 발생되는 W 아웃개싱을 이 플라즈마 인핸스드 실리콘질화막으로 막은 다음, 게이트 실링 질화막을 증착하여 실리콘 표면에 오염되는 W을 근본적으로 차단하는 방법을 제공하느데 그 목적이 있다.The present invention is to solve the above problems, W, W / WN / polysilicon gate etched immediately after the selective oxidation process after the etching of the gate sealing nitride film deposited by chemical vapor deposition (LPCVD) immediately after deposition After removing the element with sulfuric acid and hydrofluoric acid-based chemical solution, deposit a low temperature plasma enhanced silicon nitride film (PE-SiN) that does not cause W outgassing and wrap the patterned W / polysilicon gate. W outgassing generated by the pre-deposition process of the gate-sealing nitride film by the subsequent high temperature LPCVD method is deposited with this plasma-enhanced silicon nitride film, and then the gate-sealing nitride film is deposited to fundamentally block W contaminated on the silicon surface. The purpose is to provide.

도1은 W/폴리실리콘 선택산화후 후세정에 의한 W오염 제거방법에 따른 W오염도를 나타낸 그래프,1 is a graph showing the W pollution degree according to the W pollution removal method by post-cleaning after W / polysilicon selective oxidation,

도2는 종래 기술에 의한 W/폴리실리콘 선택산화후 실링 질화막이 증착된 상태를 나타낸 단면도,2 is a cross-sectional view showing a state in which a sealing nitride film is deposited after W / polysilicon selective oxidation according to the prior art;

도3a 및 도3b는 본 발명에 의한 텅스텐/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법을 나타낸 도면,3A and 3B illustrate a method of removing tungsten contamination of a semiconductor device employing a tungsten / polysilicon gate according to the present invention;

도4는 본 발명을 적용하기 전과 후의 W 프로파일을 나타낸 그래프.4 is a graph showing the W profile before and after applying the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 필드산화막 2 : 게이트 폴리실리콘1: field oxide film 2: gate polysilicon

3 : 게이트 텅스텐 4 : 하드마스크3: gate tungsten 4: hard mask

5 : PE-SiN 6 : 선택산화막(버즈비크)5: PE-SiN 6: Selective Oxide (Buzzbeek)

7 : 게이트 실링 질화막7: gate sealing nitride film

상기 목적을 달성하기 위한 본 발명은, 반도체기판상에 게이트전극 형성을 위한 폴리실리콘과, WN 및 W을 순차적으로 증착하고, 이위에 하드마스크를 형성하는 단계와, 상기 하드마스크 및 게이트전극층을 소정의 게이트 패턴으로 패터닝하는 단계, 상기 패터닝시 식각으로 인하여 받은 게이트 엣지 손상을 복구시켜 주기 위하여 측벽이 드러난 W과 폴리실리콘 및 기판을 선택산화하여 게이트 폴리실리콘 아래 모서리 부분에 게이트 버즈비크를 형성시키는 단계, 상기 선택산화시 W으로 오염된 기판 표면을 황산계열 또는 불산계열 화학용액 또는 황산계열 및 불산계열 화학용액의 조합을 이용하여 제거하는 단계, 후속 공정에서의 W의 이상산화를 방지하기 위하여 상기 패터닝된 게이트구조가 형성된 기판 전면에 게이트 실링 질화막을 형성하는 단계, 상기 패터닝된 게이트 구조를 감싸도록 저온 플라즈마 인핸스드 실리콘질화막을 형성하는 단계, 및 상기 저온 플라즈마 인핸스드 실리콘질화막상에 내산화성이 우수한 저온 화학기상증착법에 의한 실리콘질화막을 형성하는 단계를 포함하여 구성된 것을 특징으로 한다.The present invention for achieving the above object, the step of sequentially depositing polysilicon for forming a gate electrode on the semiconductor substrate, and WN and W, and forming a hard mask thereon, and the predetermined hard mask and gate electrode layer Patterning the gate pattern of the gate, and selectively oxidizing the W and the polysilicon and the substrate having exposed sidewalls to recover the gate edge damage due to the etching during the patterning, thereby forming a gate burj beak at the lower edge of the gate polysilicon Removing the surface of the substrate contaminated with W during the selective oxidation using sulfuric acid-based or hydrofluoric acid-based chemical solution or a combination of sulfuric acid-based and hydrofluoric acid-based chemical solution; and to prevent abnormal oxidation of W in a subsequent process. Forming a gate sealing nitride film on the entire surface of the substrate having the gate structure formed thereon, and Forming a low temperature plasma enhanced silicon nitride film to surround the patterned gate structure, and forming a silicon nitride film by a low temperature chemical vapor deposition method having excellent oxidation resistance on the low temperature plasma enhanced silicon nitride film. It features.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

도3a 및 도3b를 참조하여 본 발명에 의한 텅스텐/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법을 설명하면 다음과 같다.3A and 3B, a method of removing tungsten contamination of a semiconductor device including a tungsten / polysilicon gate according to the present invention will be described below.

먼저, 반도체기판상에 게이트 폴리실리콘(2)/WN/W(3)을 순차적으로 증착한 후, 하드마스크로 사용되는 PE 또는 LP 실리콘질화막(SiN)(4)과 반사방지층(ARC)인 SiON막을 증착한 다음, 워드라인을 형성하기 위하여 포토레지스트를 도포하고 패터닝을 실시하고, ARC SiON과 하드마스크 질화막을 먼저 식각한 다음, 포토레지스트를 스트립하고 후세정을 실시한 후, ARC층과 하드마스크를 배리어로 하여 W/WN/폴리실리콘층들을 순차적으로 식각하여 워드라인을 형성한다. 참조부호 1은 필드산화막을 나타낸다.First, the gate polysilicon (2) / WN / W (3) is sequentially deposited on a semiconductor substrate, and then Si or PE, an LP or LP silicon nitride film (SiN) 4 used as a hard mask, and an antireflection layer (ARC) are used. After the film is deposited, a photoresist is applied and patterned to form a word line, the ARC SiON and the hard mask nitride film are etched first, the photoresist is stripped and post-washed, and then the ARC layer and the hard mask are removed. As a barrier, the W / WN / polysilicon layers are sequentially etched to form word lines. Reference numeral 1 denotes a field oxide film.

이어서 식각으로 인하여 받은 게이트 엣지 손상을 복구시켜 주기 위하여 측벽이 드러난 W과 폴리실리콘 및 기판을 선택적으로 산화하여 게이트 폴리실리콘 아래 모서리 부분에 게이트 버즈비크(6)를 형성시킨다. 이때, 선택 산화공정은 습식 증기(wet vapor) 발생장치가 장착된 RTP(Rapid thermal process)방식의 장비에서 실시하며, 습식 증기(H2O)와 H2가스의 적절한 혼합비율로 챔버안으로 넣어 W은 산화되지 않고 게이트 폴리실리콘과 기판만 선택 산화를 실시한다. 이 선택산화공정은 800~1000℃의 온도범위에서 H2O:H2의 혼합가스 비율을 0.01~1.0의 범위에서 1초~600초의 시간동안 1~100Å 두께로 실시하는 것이 바람직하다.Subsequently, to recover the gate edge damage received by the etching, W side exposed W, polysilicon and the substrate are selectively oxidized to form the gate burj bevy 6 in the lower edge portion of the gate polysilicon. At this time, the selective oxidation process is carried out in a rapid thermal process (RTP) system equipped with a wet vapor generator, and put into the chamber at an appropriate mixing ratio of wet vapor (H 2 O) and H 2 gas. The silver is not oxidized, and only the gate polysilicon and the substrate are subjected to selective oxidation. This selective oxidation step is preferably carried out at a temperature range of 800 to 1000 ° C. with a mixed gas ratio of H 2 O: H 2 at a thickness of 1 to 100 kPa for a time of 1 to 600 seconds in the range of 0.01 to 1.0.

선택산화후에 후속 공정에서의 W 이상산화를 방지하기 위하여 게이트 실링 질화막을 저합 화학기상증착(LPCVD)법으로 30~500Å 두께로 증착한다. 이때, 실링질화막을 증착하기 전에, 선택산화시 습식 증기(H2O)와 W의 반응으로 발생된 W 증기에 의하여 W으로 오염된 기판 표면을 황산계열 또는 불산계열 화학용액으로 제거한다. 황산계열 화학용액으로서 H2Si4:H2O의 비율을 1:4로 혼합한 용액 또는 H2SO4:H2O2를 50:1로 혼합한 용액을 사용할 수 있다. 불산계열 화학용액으로는 희석된 불산(HF)용액 또는 BOE(buffered oxide echant)용액을 사용할 수 있다. 또한, 황산계열과 불산계열의 화학용액을 조합하여 사용하는 것도 가능하다. 상기 게이트 실링 질화막은 PE-SiN/LP-SiN의 이중구조로 형성할 수도 있다.After selective oxidation, a gate sealing nitride film is deposited to a thickness of 30 to 500 kPa by LPCVD to prevent W abnormal oxidation in a subsequent process. At this time, before depositing the sealing nitride film, the substrate surface contaminated with W by the W vapor generated by the reaction of the wet steam (H 2 O) and W during selective oxidation is removed with sulfuric acid or hydrofluoric acid-based chemical solution. As the sulfuric acid-based chemical solution, a solution obtained by mixing a ratio of H 2 Si 4 : H 2 O in a ratio of 1: 4 or a solution in which H 2 SO 4 : H 2 O 2 is mixed in a ratio of 50: 1 can be used. Dilute hydrofluoric acid (HF) or BOE (buffered oxide echant) solutions can be used for the hydrofluoric acid-based chemical solution. It is also possible to use a combination of sulfuric acid and hydrofluoric chemicals. The gate sealing nitride film may be formed in a double structure of PE-SiN / LP-SiN.

이어서 저온 플라즈마 인핸스드 실리콘질화막(5)을 200~550℃에서 30~500Å 두께로 증착하여 패터닝된 게이트 구조를 감싸도록 하여 후속공정에서의 W 아웃개싱을 차단한 다음, 도3b에 나타낸 바와 같이 내산화성이 우수한 화학기상증착법(LPCVD)에 의한 실리콘질화막(7)을 증착하여 후속 공정에서의 W 이상산화를 방지한다. 상기 저온 플라즈마 인핸스드 실리콘질화막(5)은 10-1Torr 이하의 진공분위기에서 증착하는 것이 바람직하다. LPC SAC 공정여유도를 개선하기 위하여 상기 저온 플라즈마 인핸스드 실리콘질화막 증착시의 스텝커버리지를 10%~60%의 좋지 않은 스텝커버리지를 이용하여 증착할 수 있다.Subsequently, a low temperature plasma enhanced silicon nitride film 5 was deposited at 200 to 550 ° C. to a thickness of 30 to 500 mm to cover the patterned gate structure to block outgassing in the subsequent process, and then as shown in FIG. 3B. The silicon nitride film 7 is deposited by chemical vapor deposition (LPCVD) which is excellent in oxidizing property to prevent W abnormal oxidation in a subsequent process. The low temperature plasma enhanced silicon nitride film 5 is preferably deposited in a vacuum atmosphere of 10 −1 Torr or less. In order to improve the LPC SAC process margin, the step coverage during the deposition of the low temperature plasma enhanced silicon nitride film may be deposited using poor step coverage of 10% to 60%.

본 발명에 의한 플라즈마 인핸스드 실리콘질화막을 추가 증착하면 플라즈마 인핸스드 실리콘질화막의 좋지 않은 스텝 커버리지를 이용하여 게이트 식각시 손실된 하드마스크 플라즈마 인핸스드 실리콘질화막의 두께를 보상해 줄 수 있어 후속 LPC SAC공정의 공정여유도를 증대시킬 수 있다.Further deposition of the plasma-enhanced silicon nitride film according to the present invention can compensate for the thickness of the hard-mask plasma-enhanced silicon nitride film lost during gate etching by using the poor step coverage of the plasma-enhanced silicon nitride film. The process margin can be increased.

도4에 본 발명을 적용하기 전과 후의 W 프로파일을 나타내었다. 본 발명을 적용할 경우 W오염도가 1/4수준으로 감소함을 알 수 있다.4 shows the W profile before and after applying the present invention. When applying the present invention it can be seen that the W pollution is reduced to 1/4 level.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 후속 고온의 LPCVD법에 의한 게이트 실링 질화막 증착전 공정에 의하여 발생되는 W 아웃개싱을 막은 후, 게이트 실링 질화막을 증착하여 실리콘 표면에 오염되는 W을 근본적으로 차단하여 W 오염에 의하여 유발되는 게이트 산화막의 열화와 접합누설을 제거함으로써 DRAM 반도체소자의 데이터 보존 능력을 극대화하고 리프레쉬 시간을 향상시켜 소자 특성 및 수율을 증대시킴으로써 원가절감과 이익 극대화에 기여할 수 있다.The present invention prevents the W outgassing caused by the pre-deposition process of the gate sealing nitride film by the subsequent high temperature LPCVD method, and then deposits the gate sealing nitride film to fundamentally block the W contaminated on the silicon surface to be caused by the W contamination. By eliminating gate oxide film degradation and junction leakage, the DRAM semiconductor device can maximize the data preservation capability and improve the refresh time to increase device characteristics and yield, thereby contributing to cost reduction and profit maximization.

또한, 본 발명에 의한 플라즈마 인핸스드 실리콘질화막을 추가 증착하면 플라즈마 인핸스드 실리콘질화막의 좋지 않은 스텝 커버리지를 이용하여 게이트 식각시 손실된 하드마스크 플라즈마 인핸스드 실리콘질화막의 두께를 보상해 줄 수 있어 후속 LPC SAC공정의 공정여유도를 증대시킬 수 있다.In addition, further deposition of the plasma-enhanced silicon nitride film according to the present invention can compensate for the thickness of the hard mask plasma-enhanced silicon nitride film lost during gate etching by using the poor step coverage of the plasma-enhanced silicon nitride film. The process margin of the SAC process can be increased.

Claims (10)

반도체기판상에 게이트전극 형성을 위한 폴리실리콘과, WN 및 W을 순차적으로 증착하고, 이위에 하드마스크를 형성하는 단계,Sequentially depositing polysilicon for forming a gate electrode, WN and W on a semiconductor substrate, and forming a hard mask thereon; 상기 하드마스크 및 게이트전극층을 소정의 게이트 패턴으로 패터닝하는 단계,Patterning the hard mask and the gate electrode layer to a predetermined gate pattern; 상기 패터닝시 식각으로 인하여 받은 게이트 엣지 손상을 복구시켜 주기 위하여 측벽이 드러난 W과 폴리실리콘 및 기판을 선택산화하여 게이트 폴리실리콘 아래 모서리 부분에 게이트 버즈비크를 형성시키는 단계,Forming a gate buzz beak at the bottom edge of the gate polysilicon by selectively oxidizing the W and the polysilicon and the substrate having the sidewalls exposed to recover the gate edge damage received by the etching during the patterning; 상기 선택산화시 W으로 오염된 기판 표면을 황산계열 또는 불산계열 화학용액 또는 황산계열 및 불산계열 화학용액의 조합을 이용하여 제거하는 단계,Removing the surface of the substrate contaminated with W during the selective oxidation using sulfuric acid-based or hydrofluoric acid-based chemical solution or a combination of sulfuric acid-based and hydrofluoric acid-based chemical solution; 후속 공정에서의 W의 이상산화를 방지하기 위하여 상기 패터닝된 게이트구조가 형성된 기판 전면에 게이트 실링 질화막을 형성하는 단계,Forming a gate sealing nitride film on the entire surface of the substrate on which the patterned gate structure is formed to prevent abnormal oxidation of W in a subsequent process; 상기 패터닝된 게이트 구조를 감싸도록 저온 플라즈마 인핸스드 실리콘질화막을 형성하는 단계, 및Forming a low temperature plasma enhanced silicon nitride film to surround the patterned gate structure, and 상기 저온 플라즈마 인핸스드 실리콘질화막상에 내산화성이 우수한 저온 화학기상증착법에 의한 실리콘질화막을 형성하는 단계를 포함하여 구성되는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.A method of removing tungsten contamination in a semiconductor device employing a W / polysilicon gate, comprising forming a silicon nitride film on the low temperature plasma enhanced silicon nitride film by a low temperature chemical vapor deposition method having excellent oxidation resistance. 제1항에 있어서,The method of claim 1, 상기 선택산화 공정은 습식 증기 발생장치가 장착된 RTP방식의 장비를 이용하여 실시하며, 습식 증기(H2O)와 H2가스의 적절한 혼합비율로 챔버안으로 넣어 W은 산화되지 않고 게이트 폴리실리콘과 기판만 선택 산화를 실시하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The selective oxidation process is carried out using a RTP type equipment equipped with a wet steam generator, W into the chamber at a suitable mixing ratio of wet steam (H 2 O) and H 2 gas W is not oxidized and the gate polysilicon and A method for removing tungsten contamination in a semiconductor device employing a W / polysilicon gate, wherein the substrate is subjected to selective oxidation only. 제2항에 있어서,The method of claim 2, 상기 선택산화 공정은 800~1000℃의 온도범위에서 H2O:H2의 혼합가스 비율을 0.01~1.0의 범위에서 1초~600초의 시간동안 1~100Å 두께로 실시하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The selective oxidation process is W / characterized in that the mixed gas ratio of H 2 O: H 2 in the temperature range of 800 ~ 1000 ℃ to a thickness of 1 ~ 100 ~ for a time of 1 second to 600 seconds in the range of 0.01 ~ 1.0 Tungsten decontamination method of semiconductor device employing polysilicon gate. 제1항에 있어서,The method of claim 1, 상기 게이트 실링 질화막은 저합 화학기상증착(LPCVD)법으로 30~500Å 두께로 증착하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The gate sealing nitride film is a tungsten contamination removal method of a semiconductor device employing a W / polysilicon gate, characterized in that deposited by a low-temperature chemical vapor deposition (LPCVD) thickness of 30 ~ 500Å. 제1항에 있어서,The method of claim 1, 상기 게이트 실링 질화막을 PE-SiN/LP-SiN의 이중구조로 형성하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The method of claim 1, wherein the gate sealing nitride film is formed of a double structure of PE-SiN / LP-SiN. 제1항에 있어서,The method of claim 1, 상기 황산계열 화학용액으로서 H2Si4:H2O의 비율을 1:4로 혼합한 용액 또는 H2SO4:H2O2를 50:1로 혼합한 용액을 사용하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.W as a sulfuric acid-based chemical solution, characterized in that a solution of a mixture of H 2 Si 4 : H 2 O ratio of 1: 4 or a mixture of H 2 SO 4 : H 2 O 2 in 50: 1 / Tungsten decontamination method of semiconductor device employing polysilicon gate. 제1항에 있어서,The method of claim 1, 상기 불산계열 화학용액으로는 희석된 불산(HF)용액 또는 BOE(buffered oxide echant)용액을 사용하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The method of removing tungsten contamination of a semiconductor device employing a W / polysilicon gate is characterized by using a dilute hydrofluoric acid (HF) solution or a buffered oxide echant (BOE) solution as the hydrofluoric acid-based chemical solution. 제1항에 있어서,The method of claim 1, 상기 저온 플라즈마 인핸스드 실리콘질화막을 200~550℃에서 30~500Å 두께로 증착하여 형성하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.And removing the low-temperature plasma enhanced silicon nitride layer at a thickness of 30 to 500 mW at 200 to 550 ° C. to remove the tungsten contamination of the semiconductor device using the W / polysilicon gate. 제1항에 있어서,The method of claim 1, 상기 저온 플라즈마 인핸스드 실리콘질화막은 10-1Torr 이하의 진공분위기에서 증착하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.The low temperature plasma enhanced silicon nitride film is deposited in a vacuum atmosphere of 10 -1 Torr or less tungsten decontamination method of a semiconductor device employing a W / polysilicon gate. 제1항에 있어서,The method of claim 1, 상기 저온 플라즈마 인핸스드 실리콘질화막 증착시의 스텝커버리지를 10%~60%의 좋지 않은 스텝커버리지를 이용하여 증착하는 것을 특징으로 하는 W/폴리실리콘 게이트를 채용한 반도체소자의 텅스텐 오염 제거방법.12. A method for removing tungsten contamination in a semiconductor device employing a W / polysilicon gate, wherein the step coverage of the low temperature plasma enhanced silicon nitride film deposition is deposited using poor step coverage of 10% to 60%.
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