KR20120098300A - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

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KR20120098300A
KR20120098300A KR1020110018164A KR20110018164A KR20120098300A KR 20120098300 A KR20120098300 A KR 20120098300A KR 1020110018164 A KR1020110018164 A KR 1020110018164A KR 20110018164 A KR20110018164 A KR 20110018164A KR 20120098300 A KR20120098300 A KR 20120098300A
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film
metal
forming
bit line
semiconductor device
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KR1020110018164A
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Korean (ko)
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이남열
염승진
조직호
홍승희
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에스케이하이닉스 주식회사
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Publication of KR20120098300A publication Critical patent/KR20120098300A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864—Thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02057—Cleaning during device manufacture
    • H01L21/02068—Cleaning during device manufacture during, before or after processing of conductive layers, e.g. polysilicon or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76883—Post-treatment or after-treatment of the conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step

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  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A manufacturing method of a semiconductor device is provided to reduce complex processing stages in a bit line formation process by forming a titanium silicide film and a bit line metal film on a bit line with a damascene structure at a time. CONSTITUTION: An interlayer insulation film(35) is formed on a substrate(31) including a landing plug(34A,34B). A damascene pattern(38) exposing the landing plug is formed by etching the interlayer insulation film. A spacer(39) is formed on both walls of the damascene pattern. A metal film is formed on the surface of the landing plug. The metal layer is transformed into a metal silicide layer(41).

Description

반도체장치 제조방법{METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}Semiconductor device manufacturing method {METHOD FOR FABRICATING SEMICONDUCTOR DEVICE}

본 발명은 반도체장치 제조방법에 관한 것으로, 특히 비트라인(Bitline; BL) 형성 제조방법에 관한 것이다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a bitline (BL).

반도체 장치가 축소화됨에 따라 스택 구조를 갖는 비트라인 형성방법은, 후속 스토리지노드콘택(SNC, Storage Node Contact) 형성시 자기정렬콘택(Self Align Contact) 공정 난이도의 급격한 증가에 의해 자기정렬콘택 패일(Fail) 문제와 공정 마진 감소에 의한 스토리지 노드 콘택 형성시 활성영역과 스토리지 노드 콘택 영역 확보 문제 등의 다양한 심각한 문제를 갖고 있다. As a semiconductor device is reduced in size, a bit line forming method having a stack structure may fail due to a sudden increase in the difficulty of a Self Align Contact process when forming a storage node contact (SNC). Problem and securing the storage node contact area due to the reduction of process margins.

따라서, 최근에는 기존 스킴(Scheme)에 대한 문제를 해결하기 위해 스토리지 노드 콘택을 먼저 형성하고 이후에 비트라인 및 비트라인 콘택을 형성하는 방법이 제시되고 있다. 먼저, 인접한 두 활성영역에 스토리지 노드 콘택을 한꺼번에 형성하고 후속 다마신 구조의 비트라인을 형성하여 두 스토리지 노드 콘택을 분리하고 비트라인 콘택을 형성하는 스킴을 적용함으로써 기존 스킴대비 자기정렬콘택 패일과 스토리지 노드 콘택 영역 확보 및 비트라인 콘택 저항 측면에서 유리한 장점을 갖게 된다. Therefore, recently, in order to solve a problem with an existing scheme, a method of forming a storage node contact first and then forming a bitline and a bitline contact has been proposed. First, by forming a storage node contact in two adjacent active regions at once, and forming a bit line of a subsequent damascene structure to separate the two storage node contacts and forming a bit line contact, a self-aligned contact fail and storage compared to the existing scheme. It has advantages in terms of securing node contact area and bit line contact resistance.

그러나, 스토리지 노드 콘택을 먼저 형성하고, 비트라인 및 비트라인 콘택을 형성하는 공정은 그 공정단계가 많고 복잡한 문제점이 있다. 또한, 다마신구조를 갖는 비트라인을 형성함으로써 반도체 장치가 축소됨에 따라 비트라인 선폭이 감소되어 비트라인 저항과 콘택저항이 급격하게 증가되어 전기적 특성을 열화시키는 문제점을 발생하게 된다. However, the process of forming the storage node contact first and then forming the bit line and the bit line contact has many process steps and has a complicated problem. In addition, by forming a bit line having a damascene structure, as the semiconductor device shrinks, the line width of the bit line decreases, thereby rapidly increasing the bit line resistance and the contact resistance, thereby causing a problem of deteriorating electrical characteristics.

특히, 비트라인 형성시 비트라인 콘택저항 확보를 위해 활성영역과 접하는 부분에 메탈 실리사이드 공정 즉, 티타늄실리사이드(TiSi2)를 적용하고 있으나, 메탈스트립공정을 진행할 경우, 티타늄실리사이드 상부면에 산화막이 형성되어 콘택저항을 열화시키는 문제점을 발생하게 된다.
Particularly, when the bit line is formed, a metal silicide process, that is, titanium silicide (TiSi 2 ), is applied to a portion in contact with the active region to secure the bit line contact resistance. However, when the metal strip process is performed, an oxide film is formed on the upper surface of the titanium silicide. This causes a problem of deteriorating contact resistance.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 저저항 TiN 증착공정을 응용하여 티타늄실리사이드막과 저저항막을 동시에 증착하여 비트라인 저항과 콘택저항을 감소시키는 낮추는 반도체장치 제조방법을 제공하는데 그 목적이 있다. The present invention has been proposed to solve the above problems of the prior art, by applying a low-resistance TiN deposition process to simultaneously deposit a titanium silicide film and a low resistive film to reduce the bit line resistance and contact resistance to a semiconductor device manufacturing method The purpose is to provide.

또한, 비트라인 하부에 형성된 산화막 형성을 원천적으로 제거하여 콘택저항을 더욱 감소시킬 수 있다. In addition, contact resistance may be further reduced by fundamentally removing the oxide film formed under the bit line.

또한, 비트라인 형성 공정 크게 단순화할 수 있는 감소시키는 반도체장치 제조방법을 제공하는데 그 목적이 있다.
Another object of the present invention is to provide a method for manufacturing a semiconductor device, which can be greatly simplified in the bit line forming process.

상기 목적을 달성하기 위한 본 발명의 반도체장치 제조방법은, 랜딩플러그를 구비한 기판 상에 층간절연막을 형성하는 단계; 상기 층간절연막을 식각하여 상기 랜딩플러그를 노출시키는 다마신패턴을 형성하는 단계; 상기 랜딩플러그 표면에 금속막을 형성하는 단계; 상기 금속막을 형성하는 단계에 연속하여 동일챔버에서 금속열처리를 실시하여 금속막을 금속실리사이드막으로 변환시키는 단계; 및 상기 금속실리사이드막으로 변환하는 단계에 연속하여 동일챔버에서 금속질화막을 증착하는 공정과 상기 금속질화막내 불순물을 제거하는 처리공정을 순차적으로 복수회 반복실시하여 다마신패턴을 갭필하는 도전막을 형성하는 단계를 포함하는 것을 특징으로 한다. A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a substrate having a landing plug; Etching the interlayer insulating layer to form a damascene pattern exposing the landing plug; Forming a metal film on a surface of the landing plug; Performing metal heat treatment in the same chamber subsequent to forming the metal film to convert the metal film into a metal silicide film; And sequentially conducting a process of depositing a metal nitride film in the same chamber and a process of removing impurities in the metal nitride film successively a plurality of times in succession to convert to the metal silicide film to form a conductive film gap gap filling the damascene pattern. Characterized in that it comprises a step.

상기 금속질화막은 공간분할 화학기상증착법(SD CVD)을 이용하여 형성하는 것을 특징으로 한다. 상기 공간분할 화학기상증착법(SD CVD)은 고온열처리를 이용하여 TiCl4과 NH3 가스를 반응시켜 형성하는 것을 특징으로 한다. 상기 금속막은 TiCl4과 N2 가스를 이용하여 형성하는 것을 특징으로 한다. 상기 금속질화막내 불순물을 제거하는 처리공정은, 열처리 또는 플라즈마 방식으로 NH3 가스를 사용하여 제거하는 것을 특징으로 한다. 상기 금속막을 형성하기 이전에, 상기 다마시패턴 양측벽에 스페이서를 형성하는 단계; 전세정 공정을 실시하는 단계; 및 상기 랜딩플러그에 이온주입을 실시하는 것을 특징으로 한다. 상기 금속질화막은 티타늄질화막을 포함하는 것을 특징으로 한다.
The metal nitride film is formed using a space-division chemical vapor deposition method (SD CVD). The space-division chemical vapor deposition (SD CVD) is formed by reacting TiCl 4 with NH 3 gas using high temperature heat treatment. The metal film is formed using TiCl 4 and N 2 gas. The treatment step of removing impurities in the metal nitride film is characterized in that the removal using the NH 3 gas in a heat treatment or a plasma method. Forming spacers on both side walls of the damascene pattern before forming the metal layer; Performing a preclean process; And ion implantation into the landing plug. The metal nitride film is characterized in that it comprises a titanium nitride film.

상술한 본 발명의 반도체장치 제조 방법은, 다마신 구조를 갖는 비트라인에 티타늄실리사이드막과 비트라인 금속막을 한번에 형성하여 비트라인 저항과 콘택 저항을 동시에 낮출 수 있으며, 비트라인 형성시 복잡한 공정단계를 감소시킬 수 있는 효과가 있다.In the semiconductor device manufacturing method of the present invention described above, the titanium silicide film and the bit line metal film are formed on the bit line having the damascene structure at the same time, thereby reducing the bit line resistance and the contact resistance at the same time. There is an effect that can be reduced.

또한, 티타늄실리사이드 상부면에 산화막 형성을 원천적으로 차단하여 콘택저항을 더욱 개선 시킬 수 있는 효과가 있다.
In addition, there is an effect that can further improve the contact resistance by blocking the oxide film formation on the upper surface of the titanium silicide.

도 1은 종래기술에 따른 비트라인 하부에 형성된 산화막의 사진도.
도 2는 본발명의 일실시예에 따른 반도체장치 레이아웃 도면.
도 3a 내지 도 3e는 본 발명의 일실시예에 따른 반도체장치 제조방법을 도시한 공정단면도.1 is a photographic view of an oxide film formed under a bit line according to the prior art.
2 is a layout diagram of a semiconductor device according to one embodiment of the present invention;
3A through 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

이하 본 발명이 속하는 기술분야에서 통상의 지식을 가진자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

도 3a 내지 도 3e는 본 발명의 일실시예에 따른 반도체장치 제조방법을 도시한 공정단면도이다.3A through 3E are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.

도 3a에 도시된 바와 같이, 기판(31) 소자분리막(32)을 형성한다. 소자분리막(32)은 잘 알려진 STI(Shallow Trench Isolation) 공정을 이용하여 형성한다. 소자분리막(32)에 의해 활성영역(33)이 정의된다. 활성영역(33)은 비트라인콘택노드와 소토리지노트콘택노드가 정의된다. 활성영역(33)에 매립게이트가 형성된다, 매립게이트(BG)는 활성영역(33)에 트렌치를 형성한 후에 트렌치 일부를 매립하여 형성한다. 매립게이트(BG)는 공지된 방법을 참조하기로 한다. As shown in FIG. 3A, the device isolation film 32 is formed on the substrate 31. The device isolation layer 32 is formed using a well-known shallow trench isolation (STI) process. The active region 33 is defined by the device isolation layer 32. In the active region 33, a bit line contact node and a storage note contact node are defined. A buried gate is formed in the active region 33. The buried gate BG is formed by filling a portion of the trench after forming a trench in the active region 33. The buried gate BG will be referred to a known method.

활성영역(33)의 일부 표면 상에 하드마스크패턴(34)을 형성한다. 이때, 하드마스크패턴(34)은 후속 공정으로 통해 랜딩플러그(34)로 작용하도록 도전막으로 형성한다. 일례로, 하드마스크패턴(34)은 폴리실리콘막으로 형성할 수 있다. 이하, 설명의 편의를 위하여 하드마스크패턴(34)을 '랜딩플러그(34)'로 변경하여 표기하기로 한다. 랜딩플러그(34)는 비트라인콘택을 위한 제1랜딩플러그(34A)와 스토리지노드콘택을 위한 제2랜딩플러그(34B)를 형성한다. 제1,2랜딩플러그(34A, 34B)는 소자분리막(32)에 의해 자기정렬되어 형성될 수 있다. 제1랜딩플러그(34A)는 활성영역(33)의 비트라인콘택노드에 연결되고, 제2랜딩플러그(34B)는 활성영역(33)의 스토리지노드콘택에 연결된다. The hard mask pattern 34 is formed on a portion of the active region 33. At this time, the hard mask pattern 34 is formed of a conductive film to act as the landing plug 34 through a subsequent process. For example, the hard mask pattern 34 may be formed of a polysilicon film. Hereinafter, for convenience of description, the hard mask pattern 34 is changed to 'landing plug 34' and described. The landing plug 34 forms a first landing plug 34A for bit line contact and a second landing plug 34B for storage node contact. The first and second landing plugs 34A and 34B may be formed by self-alignment by the device isolation layer 32. The first landing plug 34A is connected to the bit line contact node of the active region 33, and the second landing plug 34B is connected to the storage node contact of the active region 33.

도 3b에 도시된 바와 같이, 제1,2랜딩플러그(34A, 34B)를 포함한 전면에 층간절연막(35)를 형성한다. 층간절연막(35)을 관통하여 이웃하는 활성영역(33)에 동시에 머지된 스토리지노트콘택플러그(36, Merged SNC)을 형성한다. 머지된 스토리지노드콘택플러그(36)를 형성하기 위해 이웃하는 제2랜딩플러그(34B)를 동시에 오픈시키는 스토리지노드콘택홀(미도시)이 선행될 수 있다. As shown in FIG. 3B, an interlayer insulating film 35 is formed on the entire surface including the first and second landing plugs 34A and 34B. A storage note contact plug 36 (Merged SNC) that is simultaneously merged is formed in the adjacent active region 33 through the interlayer insulating layer 35. A storage node contact hole (not shown) may be preceded to simultaneously open the neighboring second landing plugs 34B to form the merged storage node contact plug 36.

도 3c에 도시된 바와 같이, 스토리지노드콘택플러그(36)를 포함하는 전체구조 상에 다마신마스크(37)를 형성한다. 다마신마스크(37)는 감광막패턴을 포함한다. 다마신마스크(37)는 비트라인(Bit Line) 및 비트라인 콘택(Bit Line Contact) 형성을 위한 다마신패턴(38) 형성시 절연막 및 스토리지노드콘택플러그(36)를 식각하기 위한 식각장벽 역할을 하며, 이를 위해 다마신마스크(37) 절연막 및 스토리지노드콘택플러그(36)에 대하여 식각선택비를 갖는 물질을 형성하는 것이 바람직하다. 예컨대, 다마신마스크(37)는 질화막으로 형성한다.As shown in FIG. 3C, a damascene mask 37 is formed on the entire structure including the storage node contact plug 36. The damascene mask 37 includes a photosensitive film pattern. The damascene mask 37 serves as an etch barrier for etching the insulating film and the storage node contact plug 36 when the damascene pattern 38 for forming the bit line and the bit line contact is formed. To this end, it is preferable to form a material having an etch selectivity with respect to the damascene mask 37 and the storage node contact plug 36. For example, the damascene mask 37 is formed of a nitride film.

다음으로, 다마신마스크(37)를 식각장벽으로 스토리지노드콘택플러그(36) 및 층간절연막(35)을 식각한다. 이에 따라, 비트라인 및 비트라인콘택을 위한 다마신패턴(38)이 형성된다. 다마신패턴(38)에 의해 머지된 스토리지콘택플러그(36)가 개별 스토리지노드콘택플러그로 분리된다. 그리고, 층간절연막(35)이 식각됨에 따라 비트라인콘택에 연결된 제1랜딩플러그(34A)의 표면이 노출된다.Next, the storage node contact plug 36 and the interlayer insulating layer 35 are etched using the damascene mask 37 as an etch barrier. Accordingly, the damascene pattern 38 for the bit line and the bit line contact is formed. The storage contact plugs 36 merged by the damascene pattern 38 are separated into individual storage node contact plugs. As the interlayer insulating layer 35 is etched, the surface of the first landing plug 34A connected to the bit line contact is exposed.

다음으로, 다마신패턴(38)의 양측벽에 스페어서(39)을 형성한다. 스페이서(39)는 절연막으로 형성하는 것이 바람직하며, 예컨대 실리콘산화막(SiO2) 또는 실리콘질화막(SiN)으로 형성한다. Next, spacers 39 are formed on both side walls of the damascene pattern 38. The spacer 39 is preferably formed of an insulating film, for example, a silicon oxide film (SiO 2) or a silicon nitride film (SiN).

스페이서(39)를 형성하기 위해 다마신패턴(38)을 포함하는 전면에 스페이서용 절연막을 형성하고, 스페이서용 절연막은 식각하여 다마신패턴(38) 측벽에만 잔류하도록 식각한다. 또한, 절연막은 보호막을 포함할 수 있다. 보호막은 절연막이 후속 공정에서 손실되는 것을 방지하는 보호막 역할을 수행한다. 절연막(39)에 의해 스토리지노드콘택과 비트라인간의 캐패시턴스를 낮추어 RC 딜레이를 완화하고, 보호막에 의해 절연막(29)이 후속 공정에서 손실되지 않는다. In order to form the spacers 39, a spacer insulating film is formed on the entire surface including the damascene pattern 38, and the spacer insulating film is etched so as to remain only on the sidewall of the damascene pattern 38. In addition, the insulating film may include a protective film. The protective film serves as a protective film to prevent the insulating film from being lost in a subsequent process. The insulating layer 39 lowers the capacitance between the storage node contact and the bit line to alleviate the RC delay, and the protective layer prevents the insulating layer 29 from being lost in subsequent processes.

다음으로, 제1랜딩플러그(34A)의 표면을 노출시키도록 절연막(39)을 식각한다. 분리된 스토리지노드콘택플러그(36) 사이에서는 절연막(39)이 식각되지 않도록 하기 위해 감광막패턴을 이용할 수 있다. 노출된 제1랜딩플러그(34A)의 표면은 비트라인콘택영역이다. 즉, 후속의 다마신비트라인과 제1랜딩플러그(34A)의 콘택을 위한 영역이다. Next, the insulating film 39 is etched to expose the surface of the first landing plug 34A. A photoresist pattern may be used to prevent the insulating layer 39 from being etched between the separated storage node contact plugs 36. The exposed surface of the first landing plug 34A is a bit line contact region. That is, the area for contact between the subsequent damascene bit line and the first landing plug 34A.

다음으로, 비트라인콘택저항을 확보하기 위해 이온주입 공정을 실시한다. 이온주입을 진행하기 전에 다마신패턴(38)의 바닥에 자연산화막(Native Oxide)을 제거하기 위한 전세정(Pre-cleaning) 공정을 먼저 진행하는 것이 바람직하다. 전세정공정은 습식세정과 건식세정을 포함한다. Next, an ion implantation process is performed to secure the bit line contact resistance. Before proceeding with ion implantation, it is preferable to first perform a pre-cleaning process for removing a native oxide on the bottom of the damascene pattern 38. Pre-cleaning processes include wet and dry cleaning.

도 3d에 도시된 바와 같이, 비트라인콘택영역을 포함하는 전면에 티타늄실리사이드막(41)과 티타늄질화막(40)은 연속적으로 동일챔버에서 형성된다. 티타늄실리사이드막(41)과 티타늄질화막(40)은 단일층으로 형성될 수 있다. As shown in FIG. 3D, the titanium silicide film 41 and the titanium nitride film 40 are continuously formed in the same chamber on the entire surface including the bit line contact region. The titanium silicide layer 41 and the titanium nitride layer 40 may be formed as a single layer.

다마신패턴(38)을 포함한 전면에 티타늄막을 형성한다. 연속적으로 동일챔버에서 티타늄막을 급속열처리(RTP)를 실시하여 제1랜딩플러그(34A)에 티타늄실리사이드막(TiSiX)을 형성한다. 티타늄막은 플라즈마공정을 통해 TiCl4와 H2가스를 이용하여 형성한다. 티타늄막은 수 KW의 전력과 TiCl4는 수십sccm 및 H2는 4000sccm 유량을 주입하여 형성할 수 있다. A titanium film is formed on the entire surface including the damascene pattern 38. The titanium film is sequentially subjected to rapid thermal treatment (RTP) in the same chamber to form a titanium silicide film (TiSiX) in the first landing plug 34A. The titanium film is formed using TiCl 4 and H 2 gas through a plasma process. The titanium film may be formed by injecting power of several KW, TiCl 4 by injecting tens of sccm, and H 2 by 4000 sccm.

연속적하여 동일챔버에서 티타늄실리사이드막을 포함한 다마신패턴 내부에 티타늄질화막(40)을 형성한다. 티타늄질화막은 공간분할 화학기상증착법(SD CVD : Space Divided CVD)을 이용하여 형성할 수 있다. 공간분할 화학기상증착법은 TiCl4과 NH3가스를 이용하여 고온열처리를 통하여 실시할 수 있다. TiCl4과 NH3가스를 반응시, TiCl4은 50~400sccm 유량을 유입하고, NH3은 수십~수백sccm 유량을 유입할 수 있으며, 압력은 수백 mtorr~수 torr이다. 고온열처리는 500~700℃ 이상의 온도에서 진행할 수 있다. 퍼지가스는 Ar 또는 He을 이용할 수 있다. The titanium nitride layer 40 is formed in the damascene pattern including the titanium silicide layer in the same chamber in succession. The titanium nitride film may be formed using a space-divided chemical vapor deposition method (SD CVD). Space-division chemical vapor deposition can be carried out by high temperature heat treatment using TiCl 4 and NH 3 gas. When TiCl 4 and NH 3 gas are reacted, TiCl 4 flows 50 to 400 sccm, NH 3 flows to several tens to hundreds of sccm, and the pressure is several hundred mtorr to several torr. High temperature heat treatment can be carried out at a temperature of 500 ~ 700 ℃ or more. The purge gas may use Ar or He.

다음으로, 티타늄질화막에 불순물을 제거하기 위해 또한 열처리 또는 플라즈마 트리트먼트(Treatment)공정을 실시한다. 트리트먼트(Treatment)공정 티타늄질화막의 막질을 개선할 수 있으며, NH3을 동일챔버에 주입함으로써 Cl의 농도를 낮출 수 있다. Next, in order to remove impurities from the titanium nitride film, a heat treatment or plasma treatment process is also performed. Treatment process The film quality of the titanium nitride film can be improved, and the concentration of Cl can be lowered by injecting NH 3 into the same chamber.

본 발명은 티타늄막을 증착하고 공간분할 화학기상증착법(SD CVD : Space Divided CVD)을 이용하여 티타늄질화막(40)을 증착 공정을 복수회 반복실시함으로써, 비트라인을 형성하는 공정단계를 감소시킬 수 있으며. 비트라인 저항과 콘택저항을 동시에 낮출 수 있는 효과가 발생한다. The present invention can reduce the process step of forming a bit line by depositing a titanium film and repeating the deposition process of the titanium nitride film 40 a plurality of times by using a Space Divided CVD (SD CVD). . The effect is to lower the bit line resistance and the contact resistance simultaneously.

도 3e에 도시된 바와 같이, 티타늄질화막을 리세스시켜 다마시패턴(38)을 일부 매립하는 비트라인(40A)을 형성한다. 그리고, 비트라인(40A) 상에 나머지 다마신패턴(38)을 매립하는 실링막(42)을 형성한다. 실링막(42)은 예컨대 텅스텐막으로 형성할 수 있다. 텅스텐막은 화학기상증착법(CVD)을 이용하여 증착한다. 텅스텐막은 SiH4 환원법, B2H6 환원법 또는 H2 환원법을 이용하여 증착한다. 이때, 텅스텐소스는 육불화텅스텐(WF6) 또는 텅스텐헥사카보닐{Tungsten hexacabonyl; W(CO)6}을 이용할 수 있다.As shown in FIG. 3E, the titanium nitride film is recessed to form a bit line 40A which partially fills the damascene pattern 38. Then, the sealing film 42 for filling the remaining damascene pattern 38 is formed on the bit line 40A. The sealing film 42 may be formed of, for example, a tungsten film. The tungsten film is deposited by chemical vapor deposition (CVD). The tungsten film is deposited using the SiH 4 reduction method, the B 2 H 6 reduction method, or the H 2 reduction method. At this time, the tungsten source is tungsten hexafluoride (WF 6 ) or tungsten hexacarbononyl (Tungsten hexacabonyl; W (CO) 6 } can be used.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.
Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

31 : 기판 32 : 소자분리막
33 : 활성영역 34 : 랜딩플러그
35 : 층간절연막 36 : 스토리지노트콘택플러그
37 : 다마신마스크 38 : 다마신패턴
39 : 스페이서 40 : 티타늄질화막
41 : 티타늄실리사이드막 42 : 실링막31 substrate 32 device isolation film
33: active area 34: landing plug
35: interlayer insulating film 36: storage note contact plug
37: damascene mask 38: damascene pattern
39: spacer 40: titanium nitride film
41: titanium silicide film 42: sealing film

Claims (8)

랜딩플러그를 구비한 기판 상에 층간절연막을 형성하는 단계;
상기 층간절연막을 식각하여 상기 랜딩플러그를 노출시키는 다마신패턴을 형성하는 단계;
상기 랜딩플러그 표면에 금속막을 형성하는 단계;
상기 금속막을 형성하는 단계에 연속하여 동일챔버에서 금속열처리를 실시하여 금속막을 금속실리사이드막으로 변환시키는 단계; 및
상기 금속실리사이드막으로 변환하는 단계에 연속하여 동일챔버에서 금속질화막을 증착하는 공정과 상기 금속질화막내 불순물을 제거하는 처리공정을 순차적으로 복수회 반복실시하여 다마신패턴을 갭필하는 도전막을 형성하는 단계
를 포함하는 반도체장치 제조방법.
Forming an interlayer insulating film on a substrate having a landing plug;
Etching the interlayer insulating layer to form a damascene pattern exposing the landing plug;
Forming a metal film on a surface of the landing plug;
Performing metal heat treatment in the same chamber subsequent to forming the metal film to convert the metal film into a metal silicide film; And
Forming a conductive film gap-filling the damascene pattern by successively repeating a process of depositing a metal nitride film in the same chamber and a process of removing impurities in the metal nitride film successively in the same chamber subsequent to converting the metal silicide film;
Semiconductor device manufacturing method comprising a.
제1항에 있어서,
상기 금속질화막은 공간분할 화학기상증착법(SD CVD)을 이용하여 형성하는 반도체장치 제조방법.
The method of claim 1,
The metal nitride film is formed using a space-division chemical vapor deposition method (SD CVD).
제1항에 있어서,
상기 공간분할 화학기상증착법(SD CVD)은 고온열처리를 이용하여 TiCl4과 NH3 가스를 반응시켜 형성하는 반도체장치 제조방법.
The method of claim 1,
The space-division chemical vapor deposition method (SD CVD) is formed by reacting TiCl 4 with NH 3 gas by using a high temperature heat treatment.
제1항에 있어서,
상기 금속막은 TiCl4과 N2 가스를 이용하여 형성하는 반도체장치 제조방법.
The method of claim 1,
And the metal film is formed using TiCl 4 and N 2 gas.
제1항에 있어서,
상기 금속막은 티타늄막을 포함하는 반도체장치 제조방법.
The method of claim 1,
The metal film is a semiconductor device manufacturing method comprising a titanium film.
제1항에 있어서,
상기 금속질화막내 불순물을 제거하는 처리공정은,
열처리 또는 플라즈마 방식으로 NH3 가스를 사용하여 제거하는 반도체장치 제조방법.
The method of claim 1,
The treatment step of removing impurities in the metal nitride film,
A method of manufacturing a semiconductor device, which is removed using NH 3 gas by heat treatment or plasma.
제1항에 있어서,
상기 금속막을 형성하기 이전에,
상기 다마시패턴 양측벽에 스페이서를 형성하는 단계;
전세정 공정을 실시하는 단계; 및
상기 랜딩플러그에 이온주입을 실시하는 단계
를 더 포함하는 반도체장치 제조방법.
The method of claim 1,
Before forming the metal film,
Forming spacers on both side walls of the damascene pattern;
Performing a preclean process; And
Performing ion implantation into the landing plug
A semiconductor device manufacturing method further comprising.
제1항에 있어서,
상기 금속질화막은 티타늄질화막을 포함하는 반도체장치 제조방법.The method of claim 1,
The metal nitride film includes a titanium nitride film.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160073864A (en) * 2014-12-17 2016-06-27 에스케이하이닉스 주식회사 Electronic device and method for fabricating the sam
KR20170024221A (en) * 2015-08-24 2017-03-07 삼성전자주식회사 Method for manufacturing semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160073864A (en) * 2014-12-17 2016-06-27 에스케이하이닉스 주식회사 Electronic device and method for fabricating the sam
KR20170024221A (en) * 2015-08-24 2017-03-07 삼성전자주식회사 Method for manufacturing semiconductor device

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