KR200455170Y1 - TBI tape for semiconductor device and manufacturing method thereof - Google Patents

Abstract

(assignment)

In particular, the electrode of the semiconductor device to be mounted without eliminating the occurrence of a narrow top width or an inadequate bonding defect caused by the inner lead, resulting in any new disadvantages such as a pattern defect, a short circuit defect, or a decrease in insulation reliability. Provided are a TAB tape for a semiconductor device having an inner lead of a fine pattern having a sufficiently wide top width to secure a bond to a pad, and a method of manufacturing the same.

(Solution)

In the TAB tape for semiconductor devices of the present invention, the inner lead 6 and the wiring pattern 5 are patterned by a wet etching process using an etchant containing an inhibitor made of an organic compound or an inorganic compound. It is formed by processing.

Description

TAB tape for semiconductor device and manufacturing method thereof {TAB TAPE FOR SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME}

The present invention provides a TAB tape for a semiconductor device suitable for a chip size package (CSP) or the like corresponding to a microminiature and thinner, for example, a BGA (Ball Grid Array) package. It relates to a tape automated bonding tape (TAB) and a method of manufacturing the same.

BGA type package mounted on a printed wiring board by using solder ball as an external connection terminal as one of the mounting forms that can realize a very small and thin package. There is a structure. In this BGA type package structure, since solder balls can be arranged on the entire flat part surface in one mounting package, electrical connection with a printed wiring board is possible on the whole flat part surface. Accordingly, the BGA type package structure has a pitch between terminals (between leads) as compared with the structure in which outer leads such as QFP (Quad Flat Package) protrude around the package. It is excellent in that it can cope with multiple pinning without narrowing, that is, it can cope with miniaturization and thinning of a package.

In such a BGA type package, a TAB tape that can be thinned while having a suitable mechanical strength and thermal strength is suitably used as a substrate that substantially supports the mechanical structure (material mechanics). As a mounting package using such a TAB tape, CSP, such as a microBGA (trademark of Tessera Technologies Inc.) package, is known, for example.

The micro-BGA package is a so-called tape BGA type CSP, in which a semiconductor chip is attached to a TAB tape with an elastomer (low elastic resin) interposed therebetween. The copper foil (wiring) is provided with the structure connected by the inner lead bent in S shape. In this µBGA package, an elastomer is inserted between a semiconductor chip and a TAB tape to relieve thermal stress between them, thereby preventing occurrence of stress breakdown of solder ball joints, and the like. Furthermore, it is possible to improve the lifetime (durability) of a solder ball joint.

In the tape BGA type CSP, as a means for achieving ultra-miniaturization and thinning, a bonding window is formed on the TAB tape, and the inner lead is bent in an S-shape at this portion. Is connected to an electrode pad on a semiconductor chip.

In a TAB tape used for such a tape BGA type CSP structure or a TAB tape for semiconductor devices for other CSPs, copper foil is generally used on one side of an insulating substrate such as a polyimide substrate. Laminate is made of such a metal conductor foil, but in order to obtain a so-called anchor effect for enhancing the adhesion strength of the joining of both of them, a conductor foil is used. For example, the roughness is deliberately enlarged by roughening the entire surface of the surface bonded to the polyimide substrate in the copper foil by roughening treatment.

In recent years, organic treatment such as silane coupling has been performed to increase the adhesion strength of a conductor foil made of metal and a polyimide substrate made of resin. Document 1).

In particular, in the above-described TAB tape for semiconductor devices, new miniaturization (fine pitching and fine patterning) of wiring patterns and the like has been requested. Various measures have been proposed (Patent Document 2).

Patent Document 1: Japanese Patent Application Laid-Open No. 2000-36547

Patent Document 2: Japanese Patent Application Laid-Open No. 2005-330572

However, when performing a pattern processing by a wet etching process on a conductive foil such as copper foil to form a very fine inner lead or wiring pattern, etching isotropic in a conventional general etching process. As it progresses to the bottom, undercut (also called side etching) occurs, so-called top width in the completed inner lead or wiring pattern (normal surface) Width) becomes narrower than the bottom width (width of the bottom), and there is a problem that it is difficult to secure a sufficient top width for effective bonding, particularly in the inner lead. The narrowness of the saw width due to the undercut tends to become more and more prominent as the miniaturization proceeds, and the finished inner lead 102 as shown schematically in FIG. The cross-sectional shape of the wiring pattern, etc., which is not present, has a width (that is, a saw width) of the surface on the opposite side than the width (that is, the bottom width) of the surface side bonded to one surface of the insulating substrate 101. It may become very small, and may be remarkably sharp, that is, substantially triangular in shape.

In such a shape, especially in the inner lead 102, the connection area with the electrode pads (not shown in the drawing) of the semiconductor device to be mounted is insufficient, and there is a high possibility of causing poor bonding.

In addition, it may be considered that the bottom width of the inner lead or the wiring pattern may be set in advance so as to avoid the occurrence of such a narrow top width or the result of poor bonding. The spacing of so-called (lead space or wiring space) becomes too narrow, and another problem arises in that a large number of pattern defects and short circuit defects occur. In addition, insulation reliability is significantly impaired.

In addition, in the technique proposed in Patent Literature 2, it is possible to reduce the degree of occurrence of the undercut as described above, but it is also difficult or impossible to eliminate the narrowness of the top width, and therefore it is difficult to cope with the new micropatterning. It was difficult.

The present invention has been made in view of such a problem, and an object thereof is to solve the occurrence of a narrow top width or a poor bonding caused by the inner lead, and in particular, to make the top width wider than the bottom width, thereby causing a pattern defect. A semiconductor device having a fine pattern inner lead having a sufficiently wide top width to securely bond to an electrode pad of a semiconductor device to be mounted without causing any new disadvantages such as short circuit failure or deterioration of insulation reliability. The present invention provides a TAB tape for use and a method of manufacturing the same.

The TAB tape for semiconductor devices of this invention pattern-processes the insulating substrate in which the window hole for bonding was formed at least, and the conductor foil joined to one surface of the said insulating substrate. A TAB tape for semiconductor devices having a conductor pattern including at least an inner lead and a wiring pattern formed by patterning, wherein the tape automated bonding tape (TAB) is used. In the said conductor pattern, the inner lead width of the surface opposite to the surface joined to one surface of the said insulated substrate is more than the inner lead width of the surface side joined with the said insulated substrate, It is characterized by the above-mentioned.

Moreover, as a specific aspect, the TAB tape for a semiconductor device of this invention pattern-processes the said conductor foil by the wet etching using the etchant which added the inhibitor, and the said inner lead is made into the TAB tape. It is characterized by consisting of.

The manufacturing method of the TAB tape for semiconductor devices of this invention is the process of forming at least the bonding window hole in an insulating substrate, the process of joining a conductor foil to one surface of the said insulating substrate, and pattern-processing the said conductor foil at least. A method of manufacturing a TAB tape for a semiconductor device comprising a step of forming a conductor pattern including an inner lead and a wiring pattern, wherein the conductor is subjected to a wet etching process using an etchant containing an inhibitor made of at least an organic compound or an inorganic compound. It is characterized by including the process of forming the said inner lead by pattern-processing foil.

According to the present invention, since the conductor foil bonded to one surface of the insulating substrate is patterned by wet etching using an etchant containing an inhibitor, at least an inner lead is formed. Thus, the etchant to which the inhibitor is added The etching by is not isotropically progressed, but rather in a direction substantially perpendicular to the surface of the conductor foil, but rather in a direction in which a so-called reverse taper (normal undercut is used as a forward taper) occurs. Accordingly, according to the present invention, a fine width having a sufficiently wide top width so as to securely bond to the electrode pad of a semiconductor device to be mounted without generating any new disadvantages such as a pattern defect, a short circuit defect, or a decrease in insulation reliability. The inner lead of the pattern can be formed.

EMBODIMENT OF THE INVENTION Hereinafter, the TAB tape for semiconductor devices and its manufacturing method which concern on a present Example are demonstrated with reference to drawings.

The TAB tape (Tape Automated Bonding) tape 10 for semiconductor devices includes an insulating substrate 1 and a conductor pattern 2 as shown in FIG. The main part is composed of

The insulating substrate 1 is a film substrate made of a thin insulating material having a predetermined mechanical strength such as, for example, a polyimide resin film, and is a solder hole mounting via hole. The ball via via (3) and the bonding window hole (4) are drilled at a predetermined position by punching using, for example, a press die. Formed.

The conductor pattern 2 is formed by patterning a conductor foil 11 bonded to one surface of the insulating substrate 1, and at least the wiring pattern 5 and the inner lead. (inner lead) 6 is provided. In addition, although not shown in the drawings, an external connection terminal such as an outer lead set to be connected to an external printed wiring board, for example, may be provided.

Surface roughness of the surface 7 in the portion exposed in the solder ball mounting via hole 3 and the portion exposed in the bonding window hole 4 in the conductor pattern 2; surface roughness is less than the surface roughness of the surface 8 at the portion joined to one surface of the insulating substrate 1. As a result, premature deterioration or shortening of the bonding tool 40 pressurized to one surface of the inner lead 6 exposed from the bonding window hole 4. ) Can be avoided.

In addition, the surface 8 of the portion of the conductor pattern 2 joined to one surface of the insulating substrate 1 is, for example, a silane coupling to increase the adhesion strength of the bonding. Although the organic treatment as described above is carried out, the surface 7 of the portion exposed in the solder ball mounting via hole 3 and the portion exposed in the bonding window hole 4 in the conductor pattern 2 is formed. ), Traces of organic treatment such as silane coupling are completely removed.

The wiring pattern 5 is a so-called wiring body, which is continuous with the inner lead 6. The inner lead 6 is formed to span the window hole 4 for bonding, and has a notch 9 for cutting, and as shown in FIG. It is pressurized by the bonding tool 40 to the terminal 31 for connection of the semiconductor chip 30 mounted on the TAB tape 10, and in the notch part 9; By cutting | disconnecting, the surface side (what is called a bottom surface) joined to one surface of the insulating board 1 in this inner lead 6; Subsequently, this is called the lower surface B. It is set so as to be connected (joined) to the surface on the opposite side (the so-called top surface; simplified and referred to as the top surface A).

More specifically, the inner lead 6 extracts and enlarges its cross-sectional shape in FIG. 2 so that the left and right corner portions (so-called corner portions) on the lower surface (B) side are locally located. It is formed in the same cross-sectional shape as beveled and cut out, and the width of the upper surface A (hereinafter referred to as the top width WA) is the width of the lower surface B. (Hereafter, this is referred to as bottom width WB).

It has a cross-sectional shape such that both left and right sides rise substantially vertically, or a cross-sectional shape having a wider top width WA than the bottom width WB, such as an inverse taper. The inner lead 6 or the wiring pattern 5 is formed of a copper foil by a wet etching process using an etchant added with an inhibitor made of an organic compound or an inorganic compound. It is realized by patterning the conductor foil 11 such as).

In addition, the inner lead 6 is provided with an insulating substrate 1 other than the inner lead 6 by performing a smoothing treatment by chemical polishing on the lower surface B. FIG. It is thinner than the thickness of the surface 8 such as the portion of the wiring pattern 5 joined to the surface. However, the thickness is 10 micrometers or more. This is because when the thickness is less than 10 µm, there is a high possibility that deformation, damage, or the like occurs in the inner lead 6.

In addition, in this inner lead 6, the surface roughness of the gloss surface of the conductor foil 11 is maintained in the surface of the upper surface A as it is. That is, the surface roughness of the upper surface A is very smooth. Thereby, the upper surface A of the inner lead 6 can be reliably connected to the electrode pad (connection pad) 31 of the semiconductor chip (semiconductor device) 30.

The semiconductor chip 30 is attached to the TAB tape 10 for semiconductor devices having such a structure with an elastomer 20 therebetween. Then, by pressing the inner lead 6 in the direction of the electrode pad 31 of the semiconductor chip 30 by using the bonding tool 40, the inner lead 6 is cut at the notch portion 9 and S It is bent in a shape and attached to the electrode pad 31 to be joined. Although not shown in the drawings, the CSP formed by using the TAB tape 10 for semiconductor devices is exposed to the exposed portion of the solder ball mounting via hole 3 in the conductor pattern 2. For example, the solder ball for connecting to the terminal for a connection of a printed wiring board, etc. is joined.

This TAB tape 10 for semiconductor devices is manufactured by the following manufacturing method.

First, as shown in Fig. 4 (a), for example, an insulating substrate 1 such as a polyimide resin film substrate with an adhesive (not shown in the drawing) is prepared. do.

The insulating substrate 1 is punched out using, for example, a press die or the like to form a solder ball mounting via hole 3, a bonding window hole 4, and a conveying hole 15 (FIG. 4). (b)).

Subsequently, the conductor foil 11 is bonded to one surface of the insulating substrate 1 (Fig. 4 (c)). At this time, the whole surface of one side of the conductor foil 11 bonded to the insulating substrate 1 is subjected to organic treatment such as roughening treatment and silane coupling to enhance the adhesiveness in advance. (One side of this conductor foil 11 is called a rough surface below).

Then, chemical polishing treatment is performed by spraying a chemical liquid for chemical polishing treatment on the rough surface (Fig. 4 (d)).

By the chemical polishing treatment, the portion exposed from the solder ball mounting via hole 3 and the bonding window hole 4 in the conductor foil 11 (that is, the conductor pattern 2 after pattern processing; The surface 7 (the lower surface B of the inner lead 6) in the exposed part is selectively subjected to chemical polishing only, and the surface roughness on the surface 7 is made of conductor foil ( It becomes less than surface roughness in the surface 8 of the part joined to one surface of the insulating substrate 1 in 11). In addition, the trace of the organic treatment in the surface layer portion of the surface 7 of the conductor foil 11, in other words, the surface layer portion subjected to the organic treatment of the surface 7 is completely removed. As the chemical liquid for chemical polishing treatment, for example, chemical polishing liquids such as persulfate and persulfate can be suitably used.

Here, the specific surface roughness of the surface 7 corresponds to various conditions such as the chemical polishing treatment agent used in this step and the rough state of the conductor foil 11 before the chemical polishing step is performed in this step. It can be adjusted by appropriately controlling the length and length of the chemical polishing treatment time.

Subsequently, the dry film resist (or liquid photoresist is also possible) 12 is processed into a desired resist pattern by a photolithography method. After the so-called back coating (13) is performed (Fig. 4 (e)), the resist pattern is used as an etching resist and an evaporator containing an organic or inorganic compound is added. The pattern processing is performed on the conductor foil 11 by a wet etching process using a cloth to form the conductor pattern 2 made of the wiring pattern 5, the inner lead 6, and the like (Fig. 4 (f)).

In this process, the inner lead 6 or the wiring pattern having a cross-sectional shape equal to or wider than the width of the upper surface A, that is, the top width WA, that is, the width of the lower surface B, that is, the bottom width WB 5) is formed.

After that, the gold plating 14 for joining the semiconductor chip 30 or the solder ball (not shown in the drawing) is applied to approximately the entire surface of the surface where the conductor pattern 2 is exposed. The principal part of this TAB tape 10 for semiconductor devices is completed (FIG. 4 (g)).

Next, the operation of the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment will be described.

In the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment, the conductor foil 11 bonded to one surface of the insulating substrate 1 is pattern-processed by a wet etching process using an etchant added with an inhibitor. As a result, the conductive pattern 2 including the inner lead 6 and the wiring pattern 5 is formed, so that etching with an etchant added with the inhibitor is isotropic as in the case of the prior art. Rather than advancing to the surface of the conductor foil 11, it proceeds in a direction substantially perpendicular to the surface of the conductor foil 11, but rather in a direction in which a so-called reverse taper (normal undercut is used as a forward taper) occurs. Accordingly, according to the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment, the semiconductor to be mounted without causing any new disadvantages such as pattern defects, short circuit defects, or deterioration of insulation reliability. Inner leads of a fine pattern (fine pattern) having a sufficiently wide top width WA can be formed so as to securely bond to the electrode pads 31 of the apparatus 30.

In other words, the inventors of the present invention have carried out experiments, considerations, and the like for forming the inner lead 6 having a fine pattern by a wet etching process using various etchant in implementing the present invention. In the case of forming a conductor pattern 2 such as an inner lead 6 or a wiring pattern 5 by pattern-processing the conductor foil 11 bonded to one surface of the sheet) by a wet etching process, a conventional general etchant By using an etchant formed by adding an inhibitor, rather than using a part of the inner lead 6 which is set to a particularly fine pattern width and pattern pitch, and requires very precise machining In the pattern forming in which the bottom width WB and the top width WA are equal or rather, the top width WA becomes wider than the bottom width WB. It confirmed that it became possible. And based on this new knowledge, it came to complete this invention.

If the inhibitor is added to the etching solution here, it is also considered that the etching speed is lowered, and further, the throughput in the pattern processing process may be reduced. In practice, however, this drop in throughput is not a problem enough to cause substantial drawbacks. In the field of TAB tapes for semiconductor devices, to which the present invention is particularly applied, the miniaturization or ultra miniaturization of various conductor patterns 2 including the wiring patterns 5 proceeds. As a result, the thickness of the copper foil to be subjected to pattern processing is very thin, and the space between the wirings is also miniaturized. Therefore, the portion of the portion to be dissolved and removed in the etching process is removed. Quantity tends to decrease more and more. For this reason, even when pattern processing is performed by the wet etching process using the etching liquid which added the inhibitor, the throughput does not fall so that it may become a practical problem. In other words, when the micropattern processing on the TAB tape for semiconductor devices is carried out using a general etching solution according to the prior art, the etching time may be slightly shorter than in the case of the present invention. As a result, a large amount of insulation failure occurs, and the yield in the pattern processing step is significantly lowered. Further, the overall manufacturing process must be retried, resulting in a significant delay in the overall manufacturing process. However, according to the present invention, it is possible to avoid the occurrence of etching defects, insulation defects, etc. of the wiring pattern 5 as described above, and there is also a fear of substantial decrease in throughput in the pattern processing step. In reality, according to the present invention It can be said that pattern processing improves throughput overall.

Here, as said etchant, for example, a mixture of cupric chloride and hydrochloric acid or a mixture of ferric chloride and hydrochloric acid is used as a base. The etching liquid prepared by adding the inhibitor which consists of an organic compound or an inorganic compound to this can be used. Further, by adding a surfactant, the inflow of the etching solution can be made good even in the space between the narrow patterns due to the activity of the surfactant. As a result, the fine wiring pattern or the ultra fine wiring pattern can be reliably ensured. The action which can be formed can be made more effective.

However, when the pattern processing is performed by the wet etching process using the etching solution as described above, the cross-sectional shape of the fine pattern such as the inner lead 6 formed thereby is as shown in FIG. The left and right edges on the) side tend to be beveled out locally. When the pattern processing is performed by the wet etching process using the etching solution as described above, the movement state of the etching solution and the behavior of the inhibitor in the etching solution mainly work in the vicinity of the lower surface B, It is considered that the left and right corner portions on the lower surface B side are beveled and cut out locally so that the apparent bottom width WB is reduced. However, since the decrease in the bottom width WB due to this cut out is numerically slight, there is no fear that a substantial disadvantage in the inner lead 6 will occur.

In the wiring pattern 5 having a larger pattern width and pattern pitch than the inner lead 6, it is easy to be cut out in a beveled shape in the lower surface B as described above, but such a pattern width However, when the pattern pitch is large, the allowable tolerance of the pattern width also becomes large, so that it does not become a problem enough to cause substantial defects. Therefore, when the conductor foil 11 is pattern-processed by the wet etching process using the etching liquid which concerns on the present Example as mentioned above, even if it forms not only the inner lead 6 but also the wiring pattern 5, when a substantial disadvantage arises, none. On the contrary, by forming the wiring pattern 5 using the etching solution according to the present embodiment, the narrowness of the top width in the wiring pattern 5 due to side etching can be eliminated, and the lead Since the space between the bottoms can be widened by the above cutting, the merit of improving the electrical reliability can be obtained.

In addition, according to the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment, after the conductor foil 11 subjected to the roughening treatment or the organic treatment is bonded to one surface of the insulating substrate 1, the conductor foil ( In the surface subjected to the roughening treatment or the organic treatment of 11), the surface 7 of the portion exposed from the solder ball mounting via hole 3 and the portion exposed from the bonding window hole 4 is selectively ( Only a portion thereof) is subjected to a chemical polishing treatment to the portions exposed from the solder ball mounting via holes 3 and the inner lead 6 in the wiring pattern 5 formed by patterning the conductor foil 11. The surface roughness of the surface 7 at the portion exposed by the bonding window hole 4 in the bonding pattern is applied to the conductor pattern 2 (mainly the wiring pattern 5) formed by patterning the conductor foil 11. Insulated substrate Since the surface roughness of the surface 8 at the portion joined to one side of (1) was made to be less, and thereby the traces of organic treatment were completely removed, it was exposed in the solder ball mounting via hole 3. The solder ball can be securely bonded to the surface 7 of the conductor pattern 2 in the part where it is, so that generation of a bonding failure such as dropping of the solder ball can be eliminated. In addition, it prevents premature deterioration or shortening of the tip of the bonding tool 40 pressed against the surface 7 of the portion exposed by the bonding window hole 4 in the inner lead 6. can do.

That is, in the prior art, in order to ensure the favorable adhesiveness of the conductor foil 11 and the insulating substrate 1, the roughening process is given to the whole surface of the side joined with the insulating substrate 1 in the conductor foil 11. This surface was intentionally roughened. In recent years, the organic foil, such as silane coupling, is applied to the entire surface of the conductor foil 11 to be bonded to the insulating substrate 1 so that the adhesion between the conductor foil 11 and the insulating substrate 1 can be improved. To secure it. This is because if the adhesion is insufficient, for example, a fatal defect such that the inner lead 6 peels off from the insulating substrate 1 may occur when bonding the inner lead.

However, the surface of the conductor foil 11 subjected to the roughening treatment and the organic treatment in this way is exposed at the portion of the solder ball mounting via hole 3 and the portion of the bonding window hole 4. That is, the surface 7 of the part to which the solder ball in the wiring pattern 5 formed by pattern-processing the conductor foil 11, and the part to which the bonding tool 40 in the inner lead 6 is pressurized, In the prior art, the surface roughly intentionally roughened by the roughening treatment or the surface treated with organic treatment. For this reason, abrasion of the bonding tool 40 is intensified about the part which the bonding tool 40 in the inner lead 6 presses, and the solder ball in the wiring pattern 5 is joined. As for the parts, in recent years, it is difficult to reliably join the solder balls with the miniaturization of the solder balls and the solder ball mounting via holes 3, so that the solder balls may be severely dropped.

However, according to the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment, a portion exposed in the solder ball mounting via hole 3 on the surface where the conductor foil 11 is roughened or organically treated, and Since the chemical polishing treatment is performed on the surface 7 of the portion exposed in the bonding window hole 4 (only in that portion), the portion exposed in the solder ball mounting via hole 3 is removed. The solder balls can be reliably bonded to the surface 7 of the conductor pattern 2 to eliminate the occurrence of bonding defects such as dropping of the solder balls, and at the same time, bonding window holes 4 in the inner lead 6. It is possible to avoid premature deterioration or shortening of the distal end portion of the bonding tool 40 pressed against the surface 7 of the portion exposed to the cross-section.

As described above, according to the TAB tape for semiconductor devices and the manufacturing method thereof according to the present embodiment, the saw width (WA) in the inner lead 6 due to side etching at the time of pattern processing by the wet etching process is obtained. ) Is sufficiently wide so that the top width WA is larger than or equal to the bottom width WB so as to prevent the narrowness of the semiconductor chip and to securely bond the electrode pad 31 of the semiconductor chip 30 to be mounted. ), The inner lead 6 of the fine pattern can be formed.

In addition, the surface roughness of the surface 7 in the portion exposed in the solder ball mounting via hole 3 and the portion exposed in the bonding window hole 4 in the conductor pattern 2 is obtained. Since the surface roughness of the surface 8 at the portion joined to one surface of the insulating substrate 1 in the surface is lower than the surface roughness, the conductor pattern at the portion exposed to the solder ball mounting via hole 3 is provided. Premature deterioration and shortening of the bonding tool 40 which can be reliably bonded to the surface 7 of (2) and is pressed against one surface of the inner lead 6 exposed by the bonding window hole 4 can be prevented. Can be avoided.

Moreover, according to the manufacturing method of the TAB tape for semiconductor devices which concerns on a present Example, the part exposed by the solder ball mounting via hole 3 in the conductor foil 11, and the part exposed by the bonding window hole 4 are shown. The surface 7 of the surface is selectively subjected to chemical polishing, and the surface roughness of these surfaces 7 is bonded to one surface of the insulating substrate 1 in the conductor foil 11. In order to make it less than the surface roughness of (8), not only the roughening process but the organic process, such as a silane coupling, is performed to the whole surface joined to one side of the insulating substrate 1 in the conductor foil 11, Also in this case, the surface layer part in which the trace of the organic treatment in the surface 7 remains can be removed reliably. As a result, a solder ball can be reliably bonded to the surface 7 of the conductor foil 11 of the part exposed by the solder ball mounting via hole 3, and the generation of a bonding defect such as solder ball dropout can be eliminated.

In the chemical polishing treatment step, it is more preferable that the chemical polishing agent or the like does not directly contact the polished surface of the conductor foil 11. This is because when the chemical polishing liquid or the like comes into contact with the polished surface of the conductor foil 11, the surface layer portion of the portion is chemically etched, and the surface roughness does not become constant on the polished surface of the conductor foil 11. Because. This is because non-negligible nonuniformity occurs in the thickness of the conductor pattern 2 formed by patterning the conductor foil 11 beyond the tolerance range. In order to avoid that surface roughness does not become constant in this way, the whole gloss surface of the conductor foil 11 is carried out at the process transitioned to the process shown by (c) from the process shown by FIG.4 (b). It is effective to apply a chemical polishing process after attaching a mask layer such as, for example, a mask tape so as to cover the film. However, the mask layer, such as this mask tape, should be removed after the chemical polishing process is completed. However, if the adhesive marks or partial residues of the mask tape are peeled off when this peels off, this becomes a factor, for example, the conductor pattern (2). There is a possibility that a serious defect as a product of the shape defect, i.e., the product of the TAB tape 10 for a semiconductor device, may occur. Here, it is preferable to use the dry film resist 12 as a mask layer like a mask tape. In other words, the dry film resist 12 is laminated on the entire gloss surface of the conductor foil 11 before the chemical polishing treatment so as to completely cover the gloss surface of the conductor foil 11. In this state, the chemical polishing treatment can be performed so that the chemical polishing chemical liquid does not come into contact with the glossy surface of the conductor foil 11. After this chemical polishing treatment step, the dry film resist 12 serves as its original role and becomes a resist pattern by exposure and development of a desired pattern, and the conductor foil is formed by an etching method using this as an etching resist. (11) is pattern-processed, and the resist pattern which becomes unnecessary after that is peeled reliably and simply by the peeling process similar to the manufacturing method of a general TAB tape. Since the dry film resist 12 is originally set to be peeled off after use and should be used in the pattern processing step of the conductor foil 11, the dry film resist 12 is used as a mask layer, so that the mask is particularly masked. This can be done without the addition of a cumbersome process of laminating a mask layer, such as a tape, or removing it after the end of chemical polishing, paying attention to adhesive marks or partial residues.

In the above embodiment, the case where a dry film resist or a liquid resist is used as the mask layer has been described, but the present invention is not limited thereto. It goes without saying that besides these, it is also possible to use a mask tape, for example. In this case, however, the addition of the lamination step, the peeling step, and the like of the mask tape is necessary in place of (or separately from) the laminating step and the peeling step of the dry film resist described above.

In addition, in the above embodiment, the TAB tape 10 for semiconductor devices has been described as having a film via structure such as that used for a CB of μBGA type, but a CSP of a μBGA type other than a film via structure or a CSP other than a μBGA type It goes without saying that the present invention can also be applied to those used in the present invention.

1 is a diagram showing the main structure of a TAB tape for a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an enlarged view of the cross-sectional shape of the inner lead in the TAB tape for semiconductor devices according to the embodiment of the present invention shown in FIG.

FIG. 3 is a diagram showing an inner lead bonding process of a BGA package using the TAB tape for semiconductor devices shown in FIG.

Fig. 4 is a diagram showing in time series the main steps in the method for manufacturing a TAB tape for semiconductor devices according to the embodiment of the present invention.

Fig. 5 is a diagram showing a remarkable example of a defect in the cross-sectional shape of the inner lead in the conventional TAB tape for semiconductor devices.

* Description of the symbols for the main parts of the drawings *

1 Insulation Substrate 2 Conductor Pattern

3: Solder ball mounting via hole 4: Bonding window hole

5: wiring pattern 6: inner lead

9: notch part 10: TAB tape for semiconductor devices

11: conductor foil 12: dry film resist

30 semiconductor chip 40 bonding tool

Claims (9)

Inner lead formed by pattern-processing an insulating substrate having a bonding window hole formed therein and a conductor foil bonded to one surface of the insulating substrate. ) A TAB tape for semiconductor devices having a conductor pattern including a wiring pattern and a wiring pattern, Inner conductor width of the surface opposite to the surface bonded to one surface of the said insulating substrate in the said conductor pattern is more than the inner lead width of the surface side joined with the said insulating substrate , The inner lead is formed in a cross-sectional shape in which both left and right corner portions on the side of the surface bonded to one surface of the insulating substrate are beveled. TAB tape for semiconductor devices characterized by the above-mentioned. delete The method according to claim 1, The inner lead is set so that the surface opposite to the surface side bonded to one surface of the insulating substrate is connected to the electrode pad of the semiconductor device mounted on the TAB tape for semiconductor device. TAB tape for semiconductor devices characterized by the above-mentioned. delete The method according to claim 1, The surface roughness of the surface at the portion exposed by the bonding window hole at the surface side where the inner lead is bonded to the insulating substrate is different in the conductor pattern than the exposed portion. Less than the surface roughness of the portion bonded to one side of the insulating substrate TAB tape for semiconductor devices characterized by the above-mentioned. The method according to claim 1, The inner lead is provided so that the surface of the surface side bonded to one surface of the insulating substrate is exposed at the bonding window hole, and the inner lead is exposed at the portion of the bonding window hole at the bonded surface side. The surface roughness of the surface opposite to the surface side bonded to one side of the said insulating substrate is smaller than the surface roughness of the surface TAB tape for semiconductor devices characterized by the above-mentioned. The method according to claim 1, The thickness of the portion of the inner lead provided so as to be exposed in the bonding window hole on the surface on the surface side bonded to one surface of the insulating substrate is the insulating property in the conductor pattern other than the exposed portion. It is less than the thickness of the part joined to one side of a board | substrate, and it is 10 micrometers or more TAB tape for semiconductor devices characterized by the above-mentioned. delete delete

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