KR20040103992A - Method and apparatus driving of plasma display panel - Google Patents

Abstract

PURPOSE: A method and an apparatus for driving a plasma display panel are provided to maintain the wall charge so as to generate the SE address discharge during the SE address period. CONSTITUTION: A method for driving a plasma display panel includes the steps of: holding the wall charge in the corresponding discharge cells by supplying the wall charge holding voltage to the sustain electrode of the discharge cells before the corresponding discharge cell is scanned; and supplying a base voltage higher than the wall charge holding voltage to the sustain electrode if the corresponding discharge cell becomes the scan order.

Description

Method and apparatus for driving plasma display panel {METHOD AND APPARATUS DRIVING OF PLASMA DISPLAY PANEL}

The present invention relates to a method and apparatus for driving a plasma display panel, and more particularly, to a method and apparatus for driving a plasma display panel which can prevent misdischarge in a selective erasure subfield.

Recently, plasma display panels (hereinafter referred to as PDPs), which are easy to manufacture large panels, have attracted attention as flat panel display devices. The PDP typically displays an image by adjusting the gas discharge period of each of the pixels in accordance with digital video data. As such a PDP, an AC type PDP having three electrodes and driven by an AC voltage is typical.

1 is an enlarged view of one discharge cell constituting a conventional AC PDP.

The discharge cell 30 shown in FIG. 1 includes an upper plate having sustain electrode pairs 12Y and 12Z, an upper dielectric layer 14 and a protective film 16 sequentially formed on the upper substrate 10, and the lower substrate 18. As shown in FIG. A lower plate having a data electrode 20X, a lower dielectric layer 22, a partition wall 24, and a phosphor layer 26 sequentially formed thereon is provided.

Each of the sustain electrode pairs 12Y and 12Z is composed of a transparent electrode and a metal electrode for compensating for the high resistance of the transparent electrode. The sustain electrode pairs 12Y and 12Z are separated into the scan electrode 12Y and the sustain electrode 12Z. The scan electrode 12Y mainly supplies a scan signal for address discharge and a sustain signal for sustain discharge, and the sustain electrode 12Z mainly supplies a sustain signal. The data electrode 20X is formed to cross the sustain electrode pairs 12Y and 12Z. This data electrode 20X supplies a data signal for address discharge.

Charges generated by discharge are accumulated in the upper dielectric layer 14 and the lower dielectric layer 22. The protective film 16 prevents damage to the upper dielectric layer 14 due to sputtering during discharge and increases the emission efficiency of secondary electrons. The dielectric layers 14 and 22 and the protective layer 16 may lower the discharge voltage applied from the outside.

The partition wall 24 provides a discharge space together with the upper and lower substrates 10 and 18. The partition wall 24 is formed in parallel with the data electrode 20X to prevent ultraviolet rays generated by the gas discharge from leaking into adjacent cells. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24 to generate red, green or blue visible light. The discharge space is filled with an inert gas such as He, Ne, Ar, Xe, Kr for gas discharge, a discharge gas having a combination thereof, or an excimer gas capable of generating ultraviolet rays by discharge.

The discharge cell of this structure is selected as counter discharge by the data electrode 20X and the scan electrode 12Y, and then sustains the discharge by surface discharge by the sustain electrode pairs 12Y and 12Z. Accordingly, in the discharge cells, the fluorescent material 26 emits light by ultraviolet rays generated during the sustain discharge, so that visible light is emitted. In this case, the discharge cell adjusts the sustain discharge period, that is, the number of sustain discharges according to the video data, thereby implementing gray scale for displaying an image. In addition, a color of one pixel is realized by a combination of three discharge cells coated with red, green, and blue phosphors 26, respectively.

As a driving method of the PDP in which the discharge cells are arranged in a matrix form, an ADS (Address and Display Separation) driving method for driving the PDP in the address period and the display period, that is, the sustain period, is typical. In the ADS driving method, one frame is divided into a plurality of subfields corresponding to each bit of video data, and each of the subfields is divided into a reset period, an address period, and a sustain period. Each of these subfields has the same reset period (RPD) and address period (APD) and gives different weights to the sustain period (SPD). Accordingly, the PDP expresses a gray level corresponding to the video data in a combination of sustain periods in which discharge is maintained in accordance with the video data.

The PDP driving method is roughly classified into a selective write driving method and a selective erase driving method according to the address method. Here, in the selective write driving method, all the discharge cells are turned off in the reset period, and then the discharge cells are selected and turned on by the address discharge in the address period, thereby turning on the walls for sustain discharge. Allow sufficient charge to form. Subsequently, an image is displayed by maintaining the discharge in the discharge cells in which the wall charge is formed in the sustain period. This selective write driving method requires an address pulse having a pulse width of about 3 GPa or more in order to form a sufficient wall charge by the address discharge, and thus has a disadvantage in that high-speed driving is difficult.

In the selective erase driving method, all of the discharge cells are turned on with write discharge in the reset period, and then the discharge cells are selected and turned off with the address discharge in the address period. Subsequently, an image is displayed by sustaining discharge cells not selected as the address discharge in the sustain period. This selective erase driving method eliminates wall charges due to address discharge and thus requires an address pulse having a pulse width of about 1 ms, so that high-speed driving is possible, while turning on all discharge cells in a reset period. There is a disadvantage in that the contrast ratio is low due to the occurrence of unnecessary light.

Accordingly, the present applicant uses a combination of Selective Writing (SW) and Selective Erasing (SE) in one frame as shown in FIG. 3 in Korean Patent Application No. 10-2000-0012669. A driving method having high contrast and advantageous for high speed driving has been proposed.

Referring to FIG. 3, the SWSE driving method divides one frame into first to sixth subfields SF1 to SF6 of the SW driving method and seventh to twelfth subfields SF7 to SF12 of the SE driving method. To drive.

The first subfield SF1 of the SW driving method includes an erasing period EPD for reliably erasing wall charges, a reset period RPD for initializing all discharge cells, and a SW address for selecting and turning on discharge cells. The period SWAPD is divided into a sustain period SPD for sustain discharge of the discharge cells selected by the address discharge, and an erase period EPD (not shown) for erasing the discharge. Each of the second to fifth subfields SF2 to SF5 is divided into a reset period RPD, a SW address period SWAPD, a sustain period SPD, and an erase period EPD (not shown). The sixth subfield SF6 is divided into a SW address period SWAPD and a sustain period SPD, and does not require an erase period EPD (not shown) for subsequent SE driving. In the first to sixth subfields SF1 to SF6, the sustain period SPD is increased to have a weight of 2 ⁿ (n = 0,1,2,3,4,5) in each subfield.

The seventh to twelfth subfields SF7 to SF12 to which the SE driving method is applied are configured to sustain discharge the SE address period SEAPD for selecting and turning off the discharge cells by the address discharge and the discharge cells not selected by the address discharge. It is divided into the sustain period SPD. In the seventh to twelfth subfields SF7 to SF12, the sustain period SPD has the same weight. For example, the sustain period (SPD) of the seventh to twelfth sub-field (SF6 SF7 to) have the same brightness weight ⁽²⁵⁾ and the sixth sub-field (SF6). The previous subfield is necessarily turned on when the unnecessary discharge cells are turned off in the address period of each of the seventh to twelfth subfields SF7 to SF12. Accordingly, the seventh to twelfth subfields SF7 to SF12 do not require a separate front writing period and an erasing period while being driven in the SE method.

4 shows PDP driving waveforms in the SW subfields WSF1 and WSF2 and the SE subfields ESF1 and ESF2.

Referring to FIG. 4, the rising ramp waveform RRP and the falling ramp waveform FRP are supplied to the scan electrode Y in the reset period RPD of each of the SW subfields WSF1 and WSF2 so that all discharge cells are uniform. The wall charge is initialized to the remaining state. At this time, the sustain electrode Z is supplied with a positive bias voltage DCSC synchronized with the falling ramp waveform FRP. Then, in the address period SWAPD of each of the SW subfields WSF1 and WSF2, a negative SW scan pulse SWSP is supplied to the scan electrode Y sequentially in a line order, and in synchronization therewith, a positive SW data pulse ( The SWDP discharge is generated by supplying the SWDP to the data electrode X. In this SW address period SWSPD, the bias voltage DCSC in the reset period RPD is maintained in the sustain electrode Z. Subsequently, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode Y and the sustain electrode Z in the sustain period SPD of each of the SW subfields WSF1 and WSF2, thereby discharging the SW address. Sustain discharge is generated in the discharge cells selected by. Then, the narrow erase pulse EP is supplied to the sustain electrode Z in the erasing period EPD of the SW subfield WSF1 so that the wall charge is erased and the discharge is stopped. In the last SW subfield WSF2, an additional erasing period EPD is not required for the next SE subfield ESF1.

Subsequently, in the SE address period SEAPD of each of the SE subfields ESF1 and ESF2, a negative SE scan pulse SESP is supplied sequentially to the scan electrode Y in line with the data electrode X in synchronization therewith. The SE address discharge is generated by supplying the SE data pulse SEDP having a positive polarity. This SE address discharge turns off the discharge cells that do not need to be discharged later. Then, Y and Z sustain pulses SUSPy and SUSPz are alternately supplied to the scan electrode Y and the sustain electrode Z in the sustain period SPD of each of the SE subfields ESF1 and ESF2. Sustain discharge occurs in discharge cells that are not turned off by the discharge.

As such, the SE subfields ESF1 to ESF2 are driven in such a manner that the wall charges of the discharge cells in which the sustain discharge has occurred in the previous field are removed by the SE address discharge without requiring a separate reset period. Voltages between the electrodes required for the SE address discharge are as shown in FIG. 4.

Referring to FIG. 4, in the address period SEAPD of the SE subfield, a constant voltage, for example, a ground voltage (0V) is supplied to the sustain electrode Z, and a negative polarity is supplied to the scan electrode Y at the time of the SE address discharge. The scan pulse SESP is supplied to the data electrode X with a positive data pulse. In other words, as shown in FIG. 5A, the sustain discharge in the previous subfield causes V at the scan electrode Y in a state where a large amount of wall charges are accumulated around the scan electrode Y and the sustain electrode Z. FIG. The scan pulse SESP, which falls to the voltage of -Ve, is supplied, and the data pulse of Va voltage is supplied to the data electrode X. Accordingly, in the discharge cell, the SE address discharge is generated by being added to the difference voltage Va + Ve between the data pulse voltage Va and the scan pulse SESP voltage −Ve and the wall voltage caused by the wall charge. do. As a result of the SE address discharge, wall charges accumulated around the scan electrode Y and the sustain electrode Z are mostly erased as shown in FIG. 5B. Since the state in which most of the wall charges are erased is maintained in the next sustain period SPD as shown in FIG. 5C, even when the sustain pulses SUSPy and SUSUPz are supplied to the scan electrode Y and the sustain electrode Z, the sustain is maintained. Discharge does not occur.

However, in the above-described address period SEAPD of the SE subfield, since the SE address discharge proceeds in line order, the address discharge timing of each of the discharge cells is changed for each line. For this reason, the discharge cells with a later address discharge time must maintain the state before the address discharge, that is, the state where the wall charges are formed by the sustain discharge of the previous subfield than the discharge cells before the address discharge time. However, as the voltage applied to the discharge cell is kept constant, the wall charges formed by the sustain discharge of the previous subfield gradually disappear as shown in FIGS. 6A and 6B. Accordingly, in discharge cells having a late address discharge time, the wall charge loss amount becomes larger than the discharge cells with the previous address discharge time, thereby increasing the probability that the address discharge will not occur. Furthermore, as the resolution of the PDP increases and the technology is developed from dual scan to single scan, as described above, there is a greater probability that the address discharge does not occur in the discharge cells having the late address discharge time, and thus the wall charge in the SE address period is increased. How to maintain is growing in importance.

Accordingly, it is an object of the present invention to provide a PDP driving method and apparatus capable of maintaining wall charges so that a reliable SE address discharge can occur in an SE address period.

1 is a perspective view showing a discharge cell of a conventional three-electrode alternating current plasma display panel.

2 is a frame diagram illustrating a conventional selective write and selective erase driving method.

3 is a driving waveform diagram of a selective write subfield and a selective erase subfield of a portion of the subfields shown in FIG. 2;

FIG. 4 illustrates driving waveforms of the selective erasing subfield illustrated in FIG. 3 in detail.

5A through 5C are sectional views showing wall charge states according to driving waveforms of the selective erasing subfield shown in FIG.

6A and 6B illustrate wall charge dissipation in a selective erase address period.

7 is a driving waveform diagram of a discharge cell to which a plasma display panel driving method according to an exemplary embodiment of the present invention is applied.

8 is a driving waveform diagram of a plurality of discharge cells to which a plasma display panel driving method according to an exemplary embodiment of the present invention is applied.

9 is a layout view of electrodes of a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 10 is a drive waveform diagram supplied to the plasma display panel shown in FIG. 9; FIG.

FIG. 11 is a sustain drive circuit diagram for driving the sustain electrode lines of the plasma display panel shown in FIG. 9;

FIG. 12 is a drive timing diagram of the sustain drive circuit shown in FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, Y: scan electrode

12Z, Z: Sustain electrode 14: Upper dielectric

16: protective film 18: lower substrate

20X: data electrode 22: lower dielectric

24: partition 26: phosphor

In order to achieve the above objects, the driving method of the PDP according to the present invention selects and scans the discharge cells in the address period to erase the wall charges in the previous state, and the discharge is maintained in the discharge cells in which the wall charges are not erased in the sustain period. A method of driving a PDP, the address period comprising: supplying a wall charge holding voltage to a sustain electrode of the discharge cell until the corresponding discharge cell is scanned to hold the wall charges in the discharge cell; And supplying a base voltage higher than the wall charge holding voltage to the sustain electrode when the corresponding discharge cells are in the scanning order.

A voltage lower than the ground voltage may be supplied to the wall charge holding voltage.

The ground voltage is supplied to the base voltage.

The base voltage is maintained until the scan of the remaining discharge cells is completed.

In the supplying of the wall charge holding voltage, the discharge cells and the sustain electrode line are divided into a plurality of blocks, and the wall charge holding voltage is supplied until the scan of the corresponding discharge cell block is started in units of the sustain electrode block. Characterized in that it comprises a step.

The supplying of the base voltage may include supplying the base voltage to the corresponding sustain electrode block when the corresponding discharge cell block is in the scanning order.

The PDP driving apparatus according to the present invention is a driving apparatus of a PDP which selects and scans discharge cells in an address period to erase wall charges in a previous state and maintains discharge in discharge cells in which wall charges are not erased in a sustain period. Until the corresponding discharge cell is scanned in the address period, the wall charge holding voltage is supplied to the sustain electrode of the discharge cell to hold the wall charges in the discharge cell, and when the discharge cell is in the scanning order, the sustain electrode It characterized in that it comprises a sustain driver for supplying a base voltage higher than the wall charge holding voltage.

The sustain driver is configured to supply a voltage lower than the ground voltage to the wall charge holding voltage.

The sustain driver supplies a ground voltage to the base voltage.

The sustain driver may supply the base voltage to the sustain electrode until the scan of the remaining discharge cells is completed.

The sustain electrode line is divided into a plurality of blocks together with the discharge cells in the PDP, and the sustain driver supplies the wall charge holding voltage until scanning of the corresponding discharge cell block is started in the sustain electrode block unit. It features.

The sustain driver supplies the base voltage to the sustain electrode block when the discharge cell block is scanned.

The sustain driver may include a wall charge holding voltage supply switch for supplying the wall charge holding voltage to the sustain electrode block until the discharge cell block is scanned; And a base voltage supply switch for supplying the base voltage to the sustain electrode block when the discharge cell block is scanned in the scan order.

The sustain driving unit may further include an energy recovery circuit for generating a sustain pulse for supplying the sustain electrode line by an energy recovery method in the sustain period.

The base voltage supply switch is connected to the base voltage supply via an output node of the energy recovery circuit, and allows the plurality of sustain electrode line blocks to be commonly connected to the output node of the energy recovery circuit in the sustain period. It is characterized by.

Other objects and features of the present invention in addition to the above object will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 7 to 12.

FIG. 7 illustrates driving waveforms according to the PDP driving method according to the first embodiment of the present invention. In particular, FIG. 7 illustrates driving waveforms supplied to corresponding discharge cells in the SE subfield.

Referring to FIG. 7, in the period T0 from the address period SEAPD of the SE subfield to before the corresponding discharge cells are in the scanning order, the wall charge holding voltage on the sustain electrode Z, For example, a negative voltage (-Vz) lower than the ground voltage is supplied. This is because the discharge cell must maintain the wall charge state formed in the previous subfield as much as possible before the SE address discharge occurs for the stable SE address discharge. In other words, the discharge cells are sustain discharges using the sustain pulses SUSPy and SUSPz in the previous subfield sustain period SPD until the SE address discharge occurs, and thus the negative electrode (-) is negative on the scan electrode Y side. This is because the wall charge must maintain the state in which the positive wall charge is formed on the sustain electrode Z side as much as possible. Accordingly, the wall charge holding voltage (-Vz) is applied to the sustain electrode Z side until the scan pulse SESP is supplied to the corresponding discharge cell, and the positive wall positive charge formed on the sustain electrode Z side is applied. Will be held. Therefore, the amount of loss of the positive wall charges formed on the sustain electrode Z side is reduced, and correspondingly, the amount of loss of the negative wall charges on the scan electrode Y side to be directly used for the SE address discharge is also reduced. Will decrease. Thus, the PDP driving method according to the present invention applies the wall charge holding voltage (-Vz) to the sustain electrode (Z) until the discharge cell is scanned, thereby minimizing the wall charge loss, and is used to discharge the SE address inside the discharge cell. There will be enough wall charges to be present.

When the scan pulse SESP and the data pulse are supplied to the corresponding discharge cell, the wall voltage due to the wall voltage due to the wall voltage and the difference voltage between the pulses is added, and the SE address discharge is stably generated, so that the wall charges are mostly erased. In this case, in order to more stably generate SE address discharges and to prevent unnecessary wall charges from being formed, the remaining discharge cells from the time when the scan pulse SESP is applied to the sustain electrode Z of the corresponding discharge cell. A voltage higher than the wall charge holding voltage (-Vz), that is, a ground voltage is supplied to the point where the scan of the field is completed. The corresponding discharge cell whose wall charges are erased by the SE address discharge no longer causes sustain discharge in the subsequent sustain period SPD.

As described above, the PDP driving method according to the present invention applies the wall charge holding voltage (-Vz) to the sustain electrode Z until the corresponding discharge cell is scanned in order to minimize the wall charge loss in the address period SEAPD. In the remaining address period, a ground voltage higher than the wall charge holding voltage (-Vz) is supplied to the sustain electrode Z for stable address discharge. Accordingly, the period in which the wall charge holding voltage (-Vz) is supplied to the sustain electrode Z, that is, the wall charge holding period is changed according to the order in which the corresponding discharge cells are scanned as shown in FIG. 8.

Referring to FIG. 8, the sustain electrode Z2 of the second discharge cell is supplied to the sustain electrode Z1 of the first discharge cell for a period T1 until the first scan pulse SESP1 is supplied to the sustain period Z1 of the address period SEAPD. During the T2 period before the second scan pulse SESP2 is supplied, and during the T3 period before the third scan pulse SESP3 is supplied to the sustain electrode Z3 of the third discharge cell. Will supply (-Vz). The ground voltage is supplied to each of the sustain electrodes Z1 to Z3 of the first to third discharge cells in the remaining address periods except for the period in which the wall charge holding voltage (-Vz) is supplied.

However, in order to have different wall charge holding periods according to the scanning order, the sustain electrodes Z must be driven separately. In this case, since the burden on the sustain driving circuit becomes large, it is preferable to drive the sustain electrodes Z by dividing them into a plurality of blocks. For example, as shown in FIG. 9, the sustain electrode Z is divided into an upper sustain electrode block Ztop included in the upper block of the PDP and a lower sustain electrode block Zbot included in the lower block. In other words, the PDP shown in FIG. 9 includes the first to nth scan electrode lines Y1 to Yn independently formed for each scan line, and the upper sustain electrode block commonly connected to each other while being included in the scan line of the upper block. Ztop and a lower sustain electrode block Zbot commonly included in the scan line of the lower block and connected in common.

As shown in FIG. 10, a ground voltage is supplied to the upper sustain electrode block Ztop shown in FIG. 9 in the address period SEAPD of the SE subfield. The lower sustain electrode block Zbpt is supplied with a wall charge holding voltage (-Vz) in a period Ttop in which the upper block is scanned, and a ground voltage in a period in which the lower block is scanned. Accordingly, the discharge cells included in the scan line of the lower block may generate stable SE address discharges by reducing the wall charge loss amount due to the wall charge holding voltage (-Vz) even if the scanning order is later than that of the upper block.

FIG. 11 illustrates a sustain driving circuit for driving the upper sustain electrode block Ztop and the lower sustain electrode block Zbot shown in FIG. 10 in detail. FIG. 12 shows the driving of the sustain driving circuit shown in FIG. It is a waveform diagram.

The sustain driving circuit shown in FIG. 11 includes first to fourth switches S1 to S4, first and second diodes D1 and D2, capacitors C, and an inductor to generate a Z sustain pulse SUSPz. An energy recovery circuit comprising (L); A wall charge holding switch for supplying the wall charge holding voltage -Vz to the lower sustain electrode block Zbot, that is, a sixth switch S6; The upper sustain electrode lock (Ztop) and the lower sustain electrode block (Zbot) are electrically separated when the wall charge holding voltage (-Vz) is supplied, and the upper and lower sustain electrode blocks (Ztop, Zbot) are connected in common when the ground voltage is supplied. A ground voltage supply switch, that is, a fifth switch S5 is provided.

First, the fourth switch S4 is turned on in the period Ttop in which the scan pulse SESPtop is supplied to the discharge cells of the upper block during the address period SEAPD of the SE subfield, and the control signal shown in FIG. 12 is turned on. Accordingly, the fifth switch S5 is turned off and the sixth switch S6 is turned on. Accordingly, the ground voltage from the ground voltage source is transmitted to the upper sustain electrode block Ztop via the fourth switch S4 turned on, and the ground voltage from the lower sustain electrode block Zbot is turned on via the sixth switch S6 turned on. The wall charge holding voltage (-Vz) is supplied. Accordingly, the discharge cells included in the upper block selectively cause stable SE address discharge to cause wall charges to be erased. At this time, the discharge cells included in the lower block minimize the wall charge loss by holding the wall charges by the wall charge holding voltage (-Vz).

In the period Tbot in which the scan pulse SESPbot is supplied to the discharge cells of the lower block during the address period SEAPD of the SE subfield, the fourth switch S4 is shown in FIG. 12 while being turned on. According to the control signal, the fifth switch S5 is turned on and the sixth switch S6 is turned off. Accordingly, the ground voltage is commonly supplied to the upper and lower sustain electrode blocks Ztop and Zbot via the turned-on fourth switch S4. Accordingly, the discharge cells included in the lower block selectively generate stable SE address discharges so that the wall charges are erased.

Subsequently, in the sustain period SPD of the SE subfield, the energy recovery circuit supplies the Z sustain pulse SUSPz, and according to the control signal shown in FIG. 12, the fifth switch S5 is turned on and the sixth switch ( S6) is turned off. Accordingly, the Z sustain pulse SUSPz supplied from the energy recovery circuit is commonly supplied to the upper and lower sustain electrode blocks Ztop and Zbot. Accordingly, sustain discharge occurs in discharge cells in which wall charges are not erased due to the SE address discharge.

As described above, the PDP driving method and apparatus according to the present invention divides the sustain electrode line into a plurality of blocks and supplies the wall charge holding voltage for each block in the SE address period, thereby reducing the amount of wall charge loss to be used for the SE address discharge. Can be reduced. Accordingly, the PDP driving method and apparatus according to the present invention can cause a stable SE address discharge even if the resolution is increased.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (15)

A method of driving a plasma display panel which selects while scanning discharge cells in an address period to erase wall charges in a previous state and maintains discharge in discharge cells in which wall charges are not erased in a sustain period. The address period is Supplying the wall charge holding voltage to the sustain electrode of the discharge cell until the corresponding discharge cell is scanned to hold the wall charges in the discharge cell; And supplying a base voltage higher than the wall charge holding voltage to the sustain electrode when the corresponding discharge cells are in the scanning order. The method of claim 1, And supplying a voltage lower than a ground voltage to the sustain electrode as the wall charge holding voltage. The method of claim 1, And supplying a ground voltage to the sustain electrode at the base voltage. The method of claim 1, And maintaining the base voltage at the sustain electrode until the scan of the remaining discharge cells is completed. The method of claim 1, Supplying a wall charge holding voltage to the sustain electrode And dividing the discharge cells and the sustain electrode into a plurality of blocks, and supplying the wall charge holding voltage until scanning of the corresponding discharge cell block is started in units of the sustain electrode block. How to drive the panel. The method of claim 5, wherein Supplying a base voltage to the sustain electrode And supplying the base voltage to the sustain electrode block when the discharge cell block is in the scanning order. A driving apparatus of a plasma display panel which selects while scanning discharge cells of a plasma display panel in an address period to erase wall charges in a previous state and maintains discharge in discharge cells in which wall charges are not erased in a sustain period. Until the discharge cell is scanned in the address period, the wall charge holding voltage is supplied to the sustain electrode of the discharge cell to hold the wall charges in the discharge cell, and when the discharge cell is in the scanning order, the sustain electrode is supplied to the sustain electrode. And a sustain driver for supplying a base voltage higher than the wall charge holding voltage. The method of claim 7, wherein And the sustain driver is configured to supply a voltage lower than a ground voltage to the sustain electrode as the wall charge holding voltage. The method of claim 7, wherein And the sustain driver supplies the ground voltage to the sustain electrode as the base voltage. The method of claim 7, wherein And the sustain driver supplies the base voltage to the sustain electrode until the scan of the remaining discharge cells is completed. The method of claim 7, wherein In the plasma display panel, the sustain electrode is divided into a plurality of blocks together with the discharge cells. And the sustain driver supplies the wall charge holding voltage to the sustain electrode block until scanning of the corresponding discharge cell block is started in the unit of the sustain electrode block. The method of claim 10, The sustain drive unit And the base voltage is supplied to the sustain electrode block when the discharge cell block is scanned in the scan order. The method of claim 10, The sustain drive unit A wall charge holding voltage supply switch for supplying the wall charge holding voltage to the sustain electrode block until the discharge cell block is scanned; And a base voltage supply switch for supplying the base voltage to the sustain electrode block when the discharge cell block is scanned in the scan order. The method of claim 10, The sustain drive unit And an energy recovery circuit for generating a sustain pulse for supplying the sustain electrode in the sustain period by using an energy recovery method. The method of claim 10, The base voltage supply switch Connected to the base voltage supply source via an output node of the energy recovery circuit, And the plurality of sustain electrode blocks are commonly connected to an output node of the energy recovery circuit in the sustain period.