KR20040098952A - Method for forming a silicon rich oxide in a semiconductor metal line procedure - Google Patents

Abstract

PURPOSE: A method for forming an oxide layer in a semiconductor metal interconnection process is provided to reduce capacitance between upper and lower metal layers by avoiding diffusion of F radicals even when the silicon content is low and decreasing permittivity of an SRO(silicon rich oxide) layer. CONSTITUTION: A metal interconnection layer(202) is formed on an interlayer dielectric(200) including a contact hole. An FSG(fluoro silicate glass)(204) is formed on the metal interconnection layer to insulate the metal interconnection layers. An SRO layer(206a,206b,206c) is deposited on the FSG.

Description

Oxide film formation method in semiconductor metal wiring process {METHOD FOR FORMING A SILICON RICH OXIDE IN A SEMICONDUCTOR METAL LINE PROCEDURE}

The present invention relates to a technology for forming a silicon rich oxide (SRO) film in a semiconductor metal wiring process, and more particularly, to a method for forming an oxide film in a semiconductor metal wiring process suitable for preventing F diffusion from fluoro-silicate glass (FSG). will be.

1 is a view for explaining a conventional typical oxide film formation process.

As shown, in the state where the metal wiring layer 102 electrically connected to the contact hole is formed on the interlayer insulating film 100 on which contact holes such as a contact or via are formed, a high density plasma (HDP: High Density) The FSG 104 is deposited using a plasma method.

At this time, the FSG 104 is the main element used to fill the gap as the line width between the metal wiring is extremely narrow, the dielectric constant is set to be lower than 4.3, the dielectric constant of general USG (Undoped Silicate Glass) as 3.7, There is an advantage that the capacitance between metals can be lowered.

Meanwhile, the FSG 104 is thickly deposited at 14000 kPa and then chemical mechanical polishing (CMP) is performed for planarization.

The FSG 104 thus formed is quite unstable because of its large ionization rate at the Si—O—F bond, which causes the F group to easily escape from the bond. Thus released F ions are small in size can easily penetrate the general oxide (USG).

In order to prevent diffusion of the F group, an SRO 106, which is an oxide containing a large amount of silicon, is used, and the F group is trapped using an unbonded silicon atom inside the SRO 106.

In the prior art completed as described above, the following disadvantages are included.

1. In order to more reliably prevent diffusion of the F group, it is necessary to increase the Si content (%). In this case, the capacitance between the upper and lower metal layers increases due to the high dielectric constant of the SRO 106.

2. In the case of the non-bonded silicon of the SRO (106) forms a trap charge (charge) inside the SRO (106), which causes a leakage current if this phenomenon is intensified.

3. As a result, local process conditions in the wafer may change or shorten the life of the device.

Accordingly, the present applicant has confirmed that the above-described F group is mainly present at the interlayer interface, and if a plurality of such interfaces are formed, the F group can be prevented more efficiently while lowering the silicon ratio of the SRO 106. I thought it was.

Accordingly, an object of the present invention is to provide a method for forming an oxide film in a semiconductor metal wiring step in which SRO is formed in a stack to reliably prevent diffusion of F groups.

According to a preferred embodiment of the present invention for achieving this object, forming a metal wiring layer on the interlayer insulating film including a contact hole; Forming an FSG on the metal wiring layer for insulation between the metal wirings; Provided is an oxide film formation method in a semiconductor metal wiring process comprising depositing SRO on top of an FSG.

1 is a cross-sectional view illustrating a conventional typical oxide film formation process;

2 is a cross-sectional view illustrating a process of forming an oxide film according to a preferred embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 2 is a view for explaining an oxide film forming process in a semiconductor metal wiring process according to a preferred embodiment of the present invention. The SRO 206 is formed by stacking to form multiple interfaces and lowers the silicon ratio. do.

As shown, first, a metal film is deposited on the interlayer insulating film 200 on which contact holes such as contacts or vias are formed. The metal film is patterned by a lithography process to form a metal wiring layer 202 electrically connected to the contact hole.

In order to insulate the wiring between the metal wiring layer 202, the FSG 204 is deposited on the entire upper surface of the metal wiring layer 202 by using a high density plasma method or the like. At this time, the deposition of the FSG 204 is preferably deposited at a thickness of 14000 kPa or more and then planarized by a chemical mechanical polishing process or the like.

Here, the FSG 204 is a main element used to fill the gaps between the metal wires as the line width between the metal wires becomes extremely narrow. The dielectric constant of the FSG 204 is set to about 3.7, which is lower than that of the general USG dielectric constant of 4.3. There is an advantage that can be lowered.

A SRO 206a, 206b, 206c layer is then deposited on top of the deposited FSG 204 in a stack according to this embodiment. At this time, unlike the prior art by forming the SRO layer in a stacked structure, the F group diffused from the SRO 206a can be trapped in the SRO 206b, and the remaining F group diffused from the SRO 206b can be trapped in the SRO 206c. As can be seen, it is possible to more reliably trap the diffusion of the F group. That is, unlike the prior art, the F group spreading from the FSG 204 to the SROs 206a, 206b, and 206c is trapped at each interface of the SROs 206a, 206b, and 206c.

In this embodiment, the SRO 206a, 206b, 206c layer is limited to three depositions, but the number of depositions is not necessarily limited, and may be implemented two or more times as necessary. Do.

On the other hand, in the deposition of the SRO 206a, 206b and 206c layers three times in a stack according to the present embodiment, the F group diffused from the FSG 204 is provided at each interface of the SRO 206a, 206b and 206c. Since the silicon ratio of SRO 206a, 206b, 206c can be set as low as 1.48 Reflective Index (RI), it is lower than the silicon ratio (1.5 RI) of SRO that is conventionally deposited once. You will see.

Therefore, the present invention can reduce the dielectric constant of the SRO by preventing the diffusion of the F group even at a low Si content (%) to reduce the capacitance between the upper and lower metal layers. In addition, it is possible to cut off the leakage current by reducing the internal charge amount of the SRO, which has the effect that it is possible to operate a stable device.

As mentioned above, although this invention was demonstrated concretely based on the Example, this invention is not limited to this Example, Of course, various deformation | transformation is possible without departing from the summary of a Claim mentioned later.

Claims (4)

Forming a metal wiring layer on the interlayer insulating film including a contact hole; Forming an FSG for insulation between the metal wires on the metal wire layer; Depositing SRO on top of the FSG An oxide film forming method in a semiconductor metal wiring process comprising a. The method of claim 1, wherein the forming of the FSG, Depositing the FSG thickly on the metal wiring layer; Planarizing the thick deposited FSG by a chemical mechanical polishing process An oxide film forming method in a semiconductor metal wiring process comprising a. The method of claim 1 or 2, wherein the SRO is deposited in a stack of at least two or more times at a low silicon ratio. 4. The method of forming an oxide film in a semiconductor metal wiring process according to claim 3, wherein the silicon ratio of said SRO is 1.48 RI.