KR20040098559A - Process for polishing a semiconductor wafer - Google Patents

Abstract

PURPOSE: A method for polishing a semiconductor wafer is provided to improve nanotopology and satisfy increasing requirements for an electronic component by simultaneously polishing both surfaces of a semiconductor wafer. CONSTITUTION: While polishing liquid is supplied, the front and back surfaces of a semiconductor wafer are simultaneously polished between two rotating polishing plates covered with polishing cloth. The polishing cloth of a lower polishing plate has a flat surface, and the polishing cloth of the upper polishing plate has a surface on which a channel is formed. The semiconductor wafer is placed on a cutout of a carrier plate and is received in a prescribed geometrical path. The front surface of the semiconductor wafer comes in contact with the polishing cloth of the lower polishing plate in a polishing process. The back surface of the semiconductor wafer comes in contact with the polishing cloth of the upper polishing plate in the polishing process.

Description

Polishing method for semiconductor wafers {PROCESS FOR POLISHING A SEMICONDUCTOR WAFER}

The present invention is directed to a method of polishing a semiconductor wafer that provides improved nanotopology of the polished semiconductor wafer. This type of semiconductor wafer is suitable for the semiconductor industry, in particular for the manufacture of electronic components.

The semiconductor wafer to be used particularly suitably for the manufacture of electronic components having a line width of 0.10 μm or less should have various characteristics, and one of the particularly important characteristics is the so-called semiconductor topology of the semiconductor wafer.

The term "nanotopology" or "nanotopography", as defined by SEMI (Semiconductor Equipments and Materials International), is in the spatial wavelength range of 0.2-20 mm (lateral correlation length) and " Within the quality zone "(fixed quality area (FQA): surface area where the characteristics required for product specifications are to be met), which means a planarization deviation of the entire wafer front face. Nanotopologies are measured through full scanning of the entire wafer surface and overlapping with different sized measurement fields.

All height variations (from maximum to lowest) of the surface appearing in these measurement fields should not exceed the maximum required for the entire wafer. The size of the measurement field depends on the specification and is defined, for example, by 2 × 2 mm 2, 5 × 5 mm 2 and 10 × 10 mm 2.

In general, the final nanotopology of a semiconductor wafer is produced by a polishing process. In order to improve the planarity of semiconductor wafers, devices and methods for simultaneously polishing the front and back surfaces of semiconductor wafers have become available and have been further developed.

For example, this so-called double sided polishing is described in US Pat. No. 3,691,694. According to the embodiment of double-side polishing described in the patent document (EP 208315 B1), a semiconductor wafer in a carrier plate made of a metal or plastic material having an appropriate size cutout is applied with a polishing cloth on a path predetermined by a device and a process parameter. It is moved and polished in the presence of the polishing liquid between two covered rotary polishing plates (in the expert literature, the carrier plate is also called a template).

By way of example, as described in patent document DE 10004578 C1, the double-side polishing process is performed using a polishing cloth made of homogeneous porous foam having a hardness of 60 to 90 (Shore A). This document also discloses that the abrasive cloth attached to the upper abrasive plate has a network of channels, and that the abrasive cloth attached to the bottom abrasive plate has a flat surface without such texture. This method is first to ensure a homogeneous distribution of the abrasive used in polishing, and secondly to prevent the semiconductor wafer from sticking to the upper polishing cloth when lifting the upper abrasive plate after polishing.

In double side polishing, the semiconductor wafer is placed in the cutout of the carrier plate so that the back side of the semiconductor wafer can be located on the lower polishing plate. Therefore, during polishing, the back surface of the semiconductor wafer is polished by a grainless polishing cloth attached to the lower polishing plate, and the front surface of the semiconductor wafer is polished by a grained polishing cloth attached to the upper polishing plate.

The front surface of a semiconductor wafer is a surface considered for the manufacture of electronic components. After the polishing step, the semiconductor wafer is generally placed in an agueous bath, for example with the aid of a vacuum suction device.

The above method by the conventional method cannot satisfy the continually increasing demand imposed on the nanotopology of semiconductor wafers subjected to double side polishing for the next generation of electronic parts. Therefore, an object of the present invention is to provide a method for producing a semiconductor wafer having an improved nanotopology so as to satisfy the requirements imposed on the manufacturing of particularly required electronic components.

A subject matter of the present invention is a method of simultaneously polishing the front and rear surfaces of a semiconductor wafer between two rotating polishing plates covered with polishing cloth while supplying polishing liquid, wherein the polishing cloth of the lower polishing plate is Has a flat surface, the abrasive cloth of the upper abrasive plate of the abrasive plate has a surface on which a channel is formed, the semiconductor wafer is placed in a cutout of the carrier plate, and received on a prescribed geometric path, The front surface of the semiconductor wafer is in contact with the polishing cloth of the lower polishing plate when polishing, and the back surface of the semiconductor wafer is in contact with the polishing cloth of the upper polishing plate when polishing.

The starting products of the process are separated from semiconductor wafers separated from known methods, for example silicon single crystals cut to a constant length and circularly processed by grinding, the front and / or back sides of which are subjected to the grinding or lapping step. It is a semiconductor wafer processed by. In addition, the edges of the semiconductor wafer can be rounded at the appropriate point in the process sequence by a grinding wheel with an appropriate profile. Moreover, the surface of a semiconductor wafer may be etched after a grinding process.

According to the present invention, in order to prepare for double-side polishing, the front surface of the semiconductor wafer is placed in the cutout of the carrier plate so that it can be located in the polishing cloth of the lower polishing plate. Therefore, during double side polishing, the front surface of the semiconductor wafer is in contact with the flat polishing cloth of the lower polishing plate, while the rear surface of the semiconductor wafer is in contact with the textured abrasive cloth of the upper polishing plate. Otherwise, double side polishing is performed in a manner familiar to those skilled in the art.

The final product of the process is a semiconductor wafer with remarkably improved nanotopology, where both sides are polished.

The method according to the invention can in principle be used to produce a wafer-shaped body made of a material which can be processed by the chemical-mechanical double-sided polishing method used. Although later processing of the material is mostly done in the semiconductor industry, such types of materials, including but not limited to, silicon, silicon-germanium, silicon dioxide, silicon nitride, gallium arsenide and other III-V It includes a semiconductor. For example, silicon in single crystal form crystallized by the Czochralski method or the float zone traction process is preferable. Particular preference is given to silicon having a (100), (110) or (111) crystal orientation.

The method is particularly suitable for the manufacture of semiconductor wafers having diameters of 200 mm, 300 mm, 400 mm and 450 mm and having a thickness of several hundreds of micrometers to several centimeters, preferably of 450 to 1200 micrometers. The semiconductor wafer may be used directly as a starting material for the manufacture of a semiconductor component, or after the final polishing process has been carried out in accordance with conventional methods, and / or on the front of the wafer with a layer such as a back seal layer or silicon or other suitable semiconductor material. After the epitaxial coating is used and / or adjusted by heat treatment, it is supplied to its intended use.

Next, the method will be described based on the production example of the silicon wafer.

In principle, directly according to the invention a silicon wafer having a sawn using an annular sawing process or a wire sawing process and a region having a crystal lattice damaged to a depth of 10-40 μm depending on the diameter and shape of the sawing process are directly It is possible to process by the double-sided polishing method. However, it is desirable to circularly process a sharply sectioned, mechanically sensitive wafer edge with a grinding disc with an appropriate profile prior to double side polishing. Furthermore, in order to improve the geometry and to partially remove the damaged crystal layer, it is possible to carry out mechanical wear processes such as lapping or polishing on the peninsula wafer to reduce the amount of material removed in the polishing process according to the present invention. Do. In order to remove crystalline regions at the edges and wafer surfaces that are inevitably damaged in the mechanical treatment process and to remove all impurities that may be present, for example, metal impurities remaining in the damaged part, an etching process is performed at this point. Can lead. This etching process is carried out as a wet chemical treatment of the silicon wafer in an alkaline or acidic etching mixture, or as a plasma treatment.

For example, as described in the IBM technical report (TR 22.2342), a polishing process according to the present invention can be carried out using a commercially available double-sided polishing machine of appropriate size. The polishing machine consists essentially of a lower abrasive plate freely rotating in the horizontal plane and an upper abrasive plate freely rotating in the horizontal plane, these two plates being covered with a polishing cloth, when the polishing liquid of the appropriate chemical composition is continuously supplied. Material removal polishing on both sides of the silicon wafer).

It is possible to grind only one working cone wafer. However, in general, because of the cost, a large number of silicon wafers are polished simultaneously, the number of which depends on the structure of the polisher. The silicon wafer is held on a geometric path defined by the machine and process parameters upon polishing through a carrier plate with a cutout of sufficient size to accommodate the silicon wafer. The carrier plate is contacted with the grinder via a rotating inner pin or tooth ring and generally opposite outer outer pin or tooth ring, for example by pin gearing or involute gearing, resulting in two grinding The rotation is set between the plates.

Examples of parameters that affect the path of the silicon wafer to the upper and lower abrasive plates during polishing include the dimensions of the abrasive plate, the structure of the carrier plate, and the rotational speeds of the upper, lower abrasive plates and carrier plates. In all cases when there is one silicon wafer in the center of the carrier plate, the silicon wafer is circularly moved around the center of the polishing machine.

When a plurality of silicon wafers are arranged eccentrically on the carrier plate, the rotation of the carrier plate about its own axis constitutes a hypocycloidal path. Hypocyclosided pathways are preferred for the polishing process according to the present invention. Particular preference is given to the simultaneous use of four to six carrier plates carrying at least three silicon wafers each arranged at regular intervals in the circular path.

In principle, the carrier plate used in the process of the present invention can be made of any material which is mechanically sufficiently stable against mechanical loads generated by driving, in particular compression and tensile loads. Moreover, the material should not be significantly invaded chemically and mechanically by the polishing liquid and the polishing cloth to ensure sufficient service life of the carrier plate and also to prevent contamination of the polished silicon wafer. In addition, the material should be suitable for the production of high-planar, stress-free and undulation-free carrier plates having a predetermined thickness and shape.

In principle, the carrier plate can be made of metal, plastic, fibre-reinforced plastic or plastic coated metal, for example. Carrier plates made of steel or fiber reinforced plastic are preferred. Carrier plates made of stainless chromium steel are particularly preferred.

The carrier plate has one or more cutouts that are preferably circular to accommodate one or more silicon wafers. To ensure that the semiconductor wafer is free to move on the rotating carrier plate, the cutout should have a diameter slightly larger than the silicon wafer being polished. It is preferable that the diameter is as large as 0.1 mm to 2 mm, and particularly preferably as large as 0.3 to 1.3 mm. In order to prevent damage from the inner edge of the cutout of the carrier plate to the edge of the wafer during polishing, the inner surface of the cutout has a plastic lining of the same thickness as the carrier plate, as proposed in the patent document (EP 208315 B1). It is convenient and desirable.

The carrier plate for the polishing process according to the present invention preferably has a thickness of 400 to 1200 µm, depending on the final thickness of the polishing silicon wafer, as described in patent document (DE 19905737 A1). The amount of silicon removed by the polishing process is in the range of 5 to 100 µm, preferably in the range of 10 to 60 µm, particularly preferably in the range of 20 to 50 µm.

Within the scope of the content described with respect to the orientation of the semiconductor wafer with the front surface facing downward, the double-side polishing step is preferably carried out by methods known to those skilled in the art. Polishing cloths having a wide range of properties are commercially available, and polishing is preferably carried out using commercially available polyurethane polishing cloths having a hardness (Shore A) of 40 to 120. Particular preference is given to polyurethane polishing cloths made of polyurethane fibers in the range of Shore A of 60 to 90.

When polishing a silicon wafer, it preferably contains 1 to 10% by weight of SiO ₂ in water, particularly preferably 1 to 5% by weight, preferably 9 to 12 pH, particularly preferably 10 to 11 It is recommended to continuously supply the polishing liquid having a pH, and the polishing pressure is preferably 0.05 to 0.5 bar, particularly preferably 0.1 to 0.3 bar. The removal rate of silicon is preferably 0.1 to 1.5 m / min, particularly preferably 0.4 to 0.9 m / min.

When unloading the abrasive semiconductor wafer from the lower abrasive plate, it is desirable to insert the semiconductor wafer into a standard process rack that further treats its surface in the correct orientation in the next processing step. When the rack into which the semiconductor wafer is inserted is arranged to be rotated by 180 ° as compared with the conventional double-sided polishing in which the front surface is facing upward, the need to turn the semiconductor wafer 180 ° can be eliminated. This action can equally well be done for both manual unloading or automatic unloading by robot. Such measures can also be considered when loading the lower abrasive plate having the semiconductor wafer.

The abrasive semiconductor wafer is removed from the lower abrasive plate manually or by an automatic removal device, in which case it is preferable to use vacuum suction means. Suitable vacuum suction means are described in the patent literature (DE 19958077 A1, page 6, lines 23-30).

The semiconductor wafer is preferably transferred to the liquid, preferably to the water bath, immediately after removal. In this way, it is possible to effectively prevent drying of the abrasive and to prevent imprint of the vacuum suction device, generally the removal device.

After polishing, all the adhered polishing liquid is washed away from the semiconductor wafer and the wafer is dried.

Depending on the subsequent use, the front surface of the semiconductor wafer needs to be subjected to final polishing according to the prior art using a soft polishing cloth under the aid of an alkali polishing liquid based on SiO ₂ , for example.

EXAMPLE

A commercially available double-sided grinder manufactured by Peter Wolters, Rendersburg City, Germany, type Ac2000P ² was used in the examples and comparative examples. The polishing machine can simultaneously polish 30 silicon wafers with a diameter of 200 mm per batch. Placed at regular intervals in the circular path, six carrier cutouts lined with polyvinylidene fluoride (inner diameter 200.5 mm) and five carrier plates made of stainless steel with a thickness of 720 μm were mounted. The upper and lower abrasive plates were covered with a commercial polyurethane abrasive cloth (SUBA 500) manufactured by Rodel and reinforced with polyurethane fibers having a hardness of 74 (shore A).

The abrasive cloth spread over the lower abrasive plate had a smooth surface, and the surface of the abrasive cloth on the upper abrasive plate had a profile of circular segment, and the milled shannels 1.5 mm wide and 0.5 mm deep had a gap of 30 mm. Had a checkerboard pattern arranged as.

Comparative example

Thirty silicon wafers with an etch surface of 200 mm in diameter were each placed manually in the cutout of the carrier plate with the front face up. The polishing process was carried out while continuously supplying an aqueous abrasive (type Levasil 200 manufactured by Bayer, Leverkusen, Germany) with a fixed SiO ₂ solids content of 3.1 wt% and a pH of 11.4 through the addition of potassium carbonate and potassium hydroxide. .

Polishing was carried out at a pressure of 0.2 bar at the temperature of the upper and lower abrasive plates of 38 ° C., respectively, and the material was removed at a rate of 0.58 μm / minute. 15 μm of silicon was removed from each surface of the wafer. After the abrasive wafer had reached thickness 725 mu m, the supply of the abrasive was terminated and replaced by the supply of a stopping agent for 2 minutes. The stopping agent was an aqueous solution of 1% by weight of Granzox manufactured by Fujimi, Japan.

After the stop step was completed and the device was opened, the silicon wafer placed on the carrier plate was fully wetted with the stop solution. The silicon wafers were transferred to racks in the bath using an unloading device manufactured and marketed by Peter Wolters. Then, the silicon wafer is TMAH / H ₂ O ₂ ; HF / HCI; Ozone; In a batch cleaning apparatus with HCI's bath order, it was dried using a commercially available dryer operating according to the Marangoni principle. The nanotopology of the cleaned wafers was measured on an ADE SZM CR83 using the measurement fields 2 mm × 2 mm (HCT 2 × 2) and 10 mm × 10 mm (HCT 10 × 10), and a total of 1968 silicon wafers were polished. Then his nanotopology was examined.

Example

A total of 2157 silicon wafers were treated with a surface 200 mm in diameter by a method similar to that of the comparative example. The only difference from the comparative example is that the silicon wafer is placed in the cutout of the carrier plate with the front face down and then polished in that orientation. The results of the statistical analysis of the nanotopology are shown in the following table.

Comparative Example: 1968 Silicon Wafers Example 2711 Silicon Wafers Measure field HCT 2 × 2 HCT 10 × 10 HCT 2 × 2 HCT 10 × 10 Average 18.50 40.48 15.24 33.06 Standard Deviation 4.87 9.65 2.06 5.66

When the silicon wafer is polished with the front face down, the comparison table shows a greatly improved nanotopology of the silicon wafer for both sizes of the measurement field.

According to the present invention, by simultaneously polishing both surfaces of a semiconductor wafer, it is possible to improve nanotopology and satisfy the increasing demand for electronic components.

Claims (3)

A method of simultaneously polishing the front and back surfaces of a semiconductor wafer between two rotating polishing plates covered with a polishing cloth while supplying a polishing liquid, The abrasive cloth of the lower abrasive plate of the abrasive plate has a flat surface, the abrasive cloth of the upper abrasive plate of the abrasive plate has a surface on which a channel is formed, The semiconductor wafer is placed in a cutout of the carrier plate and received on a defined geometric path, The front surface of the semiconductor wafer is in contact with the polishing cloth of the lower polishing plate when polishing, and the back surface of the semiconductor wafer is in contact with the polishing cloth of the upper polishing plate when polishing. Polishing method of semiconductor wafer. The method of claim 1, After simultaneous polishing of the front and rear surfaces of the semiconductor wafer, the semiconductor wafer is transferred into an aqueous bath by vacuum suction means. The method according to claim 1 or 2, And the front surface of the semiconductor wafer is subjected to final polishing after simultaneous polishing of the front surface and the back surface.