KR100864347B1 - Method for producing silicon wafer - Google Patents

Abstract

The silicon wafer manufacturing method includes a planarization step of grinding or lapping the front and back surfaces of the wafer, supplying an acid etching solution to the surface while spinning the wafer, and etching the entire surface of the wafer to obtain a surface roughness (Ra) of 20.mu.m. The sheet-type acid etching process to control below and the double-sided simultaneous grinding | polishing process of grind | polishing the front and back surfaces of the said acid-etched wafer simultaneously are included in this order. Instead of the double-sided simultaneous polishing step, a single-side polishing step of polishing the front and back surfaces of the acid-etched wafer by one surface may be included.

Description

METHODS FOR PRODUCING SILICON WAFER

The present invention relates to a method for producing a silicon wafer, which can reduce both the load of the double-sided simultaneous polishing step and achieve both high flatness and reduced surface roughness.

This application claims priority with respect to Japanese Patent Application No. 2004-257886 for which it applied on September 6, 2004, and Japanese Patent Application No. 2005-237520 for which it applied on August 18, 2005. Here it is.

Generally, the manufacturing process of a semiconductor silicon wafer consists of the process of chamfering, mechanical polishing (lapping), etching, mirror polishing (polishing), and washing | cleaning the wafer obtained by cutting out and slice | stacking from the pulled-up silicon single-crystal ingot, and high precision. It is produced as a wafer having a flatness of.

Silicon wafers that have undergone machining processes such as block cutting, outer diameter grinding, slicing, and lapping have a damage layer on the surface, that is, a processing altered layer. The processing deterioration layer must be removed completely because it causes crystal defects such as slip dislocations in the device fabrication process, lowers the mechanical strength of the wafer, and adversely affects electrical properties.

An etching process is performed in order to remove this process deterioration layer. In the etching treatment, a batch-type acid etching for chemically removing a processed altered layer by immersing a plurality of wafers in an etching tank in which an acid etching solution such as mixed acid is stored, or an alkaline etching solution such as NaOH is stored. Batch-type alkaline etching which chemically removes a process deterioration layer by immersing a wafer in one etching tank is performed.

Specifically, in the batch etching using acid etching, as shown in FIG. 10, first, a plurality of wafers 1a are held vertically in the holder 1, and the holder 1 is moved by the solid arrows in FIG. 10. As shown by FIG. 1, it is lowered and immersed in an acid etching aqueous solution 2a such as mixed acid stored in the etching bath 2 to remove the processed altered layer on the wafer surface with the etching aqueous solution. Subsequently, the holder 1 on which the wafer 1a immersed in the etching aqueous solution 2a is held is pulled up as shown by the broken arrow in FIG. 10. Next, as shown by the solid arrow in FIG. 10, the holder 1 on which the wafer 1a after acid etching is finished is lowered and immersed in a rinse liquid 3a such as pure water stored in the rinse bath 3. The etching aqueous solution adhering to the wafer surface is removed. Subsequently, the holder 1 on which the wafer 1a immersed in the rinse liquid 3a for a predetermined time is held, as shown by the broken arrow in FIG. 10, and the silicon wafer is dried.

However, in batch acid etching, although the process deterioration layer can be etched while improving the wafer surface roughness, the flatness obtained by lapping is impaired, so that the etching surface has the undulation and peeling of mm order. There was a problem that the irregularities called. In addition, in batch alkaline etching, although the process deterioration layer can be etched while maintaining wafer flatness, pits having a local depth of several micrometers and sizes of several to several tens of micrometers (hereinafter referred to as facets) are referred to as facet. Has a problem that the surface roughness of the wafer deteriorates.

As a method for solving the above problems, as shown in Fig. 9, at least the semiconductor wafer obtained by slicing the single crystal ingot 4 is at least chamfered 5, wrapped 6, etching 7, 8, mirror polishing ( 9) and in the processing method of the semiconductor wafer which consists of a process of washing | cleaning, acid etching 8 is performed after alkali etching (7), and at that time, the etching value of the alkali etching (7) is acid-etched ( A processing method of a wafer larger than the etching value of 8) and a wafer processed by this method have been proposed (see Patent Document 1, for example).

By the method shown in the said patent document 1, the flatness after lapping can be maintained, the undulation of the wafer surface after etching is reduced, the occurrence of local deep pits and deterioration of surface roughness are suppressed, and particle | grains, stains, etc. It is possible to fabricate a chemical etched wafer having an etched surface that is unlikely to cause contamination. Such a wafer can reduce the polishing value in mirror polishing, and also improve its flatness.

However, in the conventional method, including the method described in Patent Document 1, the wafer which has been etched is subjected to a double-sided simultaneous polishing process or a one-side polishing process, and the surface thereof is processed to a mirror surface, but in the front and back surfaces of the silicon wafer which has finished the etching process, Since the wafer flatness at the end of the planarization process cannot be maintained and the desired wafer surface roughness is not obtained, in order to improve the wafer flatness and the wafer surface roughness, it is necessary to use both simultaneous polishing and single surface polishing processes. Since it is necessary to take many grinding | polishing values, the double-side simultaneous grinding | polishing process or single-sided polishing process was putting a big load.

Patent Document 1: Japanese Patent Application Laid-Open No. 11-233485 (claim 1, paragraph [0042])

SUMMARY OF THE INVENTION An object of the present invention is to reduce the load of a double-sided simultaneous polishing process and a one-side polishing process, and to achieve both of maintaining wafer flatness and reducing wafer surface roughness when the planarization process is completed. It is to provide a manufacturing method.

A silicon wafer manufacturing method according to the first aspect of the present invention is a planarization step of grinding or lapping the front and back surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot, and a wafer while spinning a single planarized silicon wafer. The acid etching liquid is supplied to the surface of the wafer, the acid etching liquid is spread over the entire wafer surface by centrifugal force by spin, and the entire wafer surface is etched to control the surface roughness Ra of the wafer surface to 0.20 µm or less. This step includes a step and a double-sided simultaneous polishing step of simultaneously polishing the front and back surfaces of the single wafer acid-etched silicon wafer.

In the method for manufacturing a silicon wafer according to the first aspect, polishing is performed on the front and back surfaces of the wafer in a double-sided simultaneous polishing process by controlling the surface roughness and texture size of the wafer before polishing by a single wafer type etching process using an acid etching solution. It is possible to achieve both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the flattening step is completed while reducing the values, respectively.

In the method for producing a silicon wafer according to the first aspect, the acid etching solution is an aqueous solution containing hydrofluoric acid, nitric acid, and phosphoric acid, respectively, and the mixing ratio of hydrofluoric acid, nitric acid, phosphoric acid, and water contained in the aqueous solution is in weight%, hydrofluoric acid: nitric acid: phosphoric acid = 4.5%-10.5%: 25.5%-40.0%: 30.0%-45.5% may be sufficient.

In this case, by using an aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid in a predetermined mixing ratio in the acid etching solution, the wafer surface roughness and wafer flatness after the etching process can be further reduced.

Moreover, the spin rotation speed which spins a wafer in a single wafer type etching process may be 500-2000 rpm.

The viscosity of the acid etching solution may be 10 to 35 mPa · sec.

The surface tension of the acid etching solution may be 55 to 60 dyne / cm.

The silicon wafer manufacturing method according to the second aspect of the present invention is a planarization step of grinding or lapping the front and back surfaces of a thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot, and a wafer while spinning a single planarized silicon wafer. The acid etching liquid is supplied to the surface of the wafer, the acid etching liquid is spread over the entire wafer surface by centrifugal force by spin, and the entire wafer surface is etched to control the surface roughness Ra of the wafer surface to 0.20 µm or less. This step includes a step and a single side polishing step of polishing the front and back surfaces of the single wafer type acid-etched silicon wafer one by one.

In the method for manufacturing a silicon wafer according to the second aspect, the polishing value at the front and back surfaces of the wafer in one-side polishing step is controlled by controlling the surface roughness and texture size of the wafer before polishing by a single wafer type etching step using an acid etching solution. While reducing the respective thicknesses, it is possible to achieve both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization step is completed.

In the method for producing a silicon wafer according to the second aspect, the acid etching solution is an aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid, respectively, and the mixing ratio of hydrofluoric acid, nitric acid, phosphoric acid and water in the aqueous solution is in weight%, hydrofluoric acid: nitric acid: phosphoric acid = 4.5%-10.5%: 25.5%-40.0%: 30.0%-45.5% may be sufficient.

In this case, by using an aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid in a predetermined mixing ratio in the acid etching solution, the wafer surface roughness and wafer flatness after the etching process can be further reduced.

Moreover, the spin rotation speed which spins a wafer in a single wafer type etching process may be 50-2000 rpm.

The viscosity of the acid etching solution may be 10 to 35 mPa · sec.

The surface tension of the acid etching solution may be 55 to 60 dyne / cm.

(Effects of the Invention)

In the method for producing a silicon wafer of the present invention, the surface roughness and texture size of the wafer before polishing are controlled by a single wafer type etching process using an acid etching solution. Thereby, both the maintenance of the wafer flatness and the reduction of the wafer surface roughness at the end of the planarization step can be achieved while reducing the polishing value at the front and back surfaces of the wafer in the double-side simultaneous polishing step or the single-side polishing step, respectively. By performing this method, productivity in wafer fabrication is greatly improved.

1 is a process chart showing a method of manufacturing a silicon wafer of the present invention.

2 is a plan view of the grinding apparatus.

3 is a longitudinal cross-sectional view of the grinding apparatus.

4 is a configuration diagram of the wrapping apparatus.

5 is a block diagram of a sheet type spinner.

6 is a block diagram of a double-sided simultaneous polishing apparatus.

FIG. 7 is a graph showing the relationship between wafer surface roughness and TTV in silicon wafers obtained in Examples 1 and 2 and Comparative Examples 1 to 5; FIG.

8 is a graph showing the relationship between the wafer surface roughness and LPD in the silicon wafers obtained in Examples 1 and 2 and Comparative Examples 1 to 5;

 9 is a process chart showing a conventional method for manufacturing a silicon wafer.

It is a figure which shows a batch etching process process.

* Description of the sign *

13 flattening process

14 Single Sheet Acid Etching Process

16 double-sided simultaneous polishing process

Next, the best mode for implementing this invention is demonstrated based on drawing.

First, the grown silicon single crystal ingot is cut into a block shape by cutting the tip and end portions, and the outer diameter of the ingot is ground to make a block body in order to make the diameter of the ingot uniform. Orientation planarization or orientation notching is performed on this block body to indicate a specific crystal orientation. After this process, as shown in FIG. 1, a block body is sliced at a predetermined angle with respect to the rod axis direction (step 11). The wafer sliced in step 11 is chamfered around the wafer in order to prevent chipping and chips at the periphery of the wafer (step 12). By performing this chamfering, for example, when epitaxial growth is carried out on the surface of the silicon wafer which is not chamfered, abnormal growth occurs in the periphery and the crown phenomenon that rises in an annular shape can be suppressed.

Subsequently, the uneven layer of the thin disk-shaped silicon wafer front and back surfaces generated in the step of slice and the like is flattened to increase the flatness of the front and back surfaces of the wafer and the parallelism of the wafer (Step 13). In this planarization step 13, the wafer front and back surfaces are planarized by grinding or lapping.

As a method of planarizing a wafer by grinding, it is performed by the grinding apparatus 20 as shown in FIG. 2 and FIG. As shown in FIG. 2, the turntable 22 which is a to-be-processed support part for mounting the silicon wafer 21 is comprised so that rotation is possible about the vertical axis | shaft by the drive mechanism not shown. Moreover, on the upper side of the turntable 22, as shown in FIG. 3, the grinding surface is pressed against the silicon wafer 21 adsorbed and mounted on the turntable 22 via the chuck 22a. Whetstone support means 24 for supporting 23 are provided. This grinding wheel support means 24 is comprised by the drive mechanism which is not shown in figure so that the grinding wheel 23 for rotation can be rotated about a vertical axis. Further, above the silicon wafer, a water supply nozzle 26 for supplying grinding water to the surface of the silicon wafer 21 at the time of grinding is provided. In such a grinding device 20, the grinding wheel 23 and the silicon wafer 21 are relatively rotated by the respective driving mechanisms, and the contact portion with the grinding wheel 23 on the surface of the silicon wafer 21. Grinding water is supplied from the water supply nozzle 26 to the part which deviates further, and the grinding grindstone 23 is pressed on the surface of the silicon wafer 21, and the grinding | polishing is carried out while cleaning the surface of the silicon wafer 21.

Moreover, as a method of planarizing a wafer by lapping, it is performed by the lapping apparatus 30 as shown in FIG. As shown in FIG. 4, first, the carrier plate 31 is engaged with the sun gear 37 and the internal gear 38 of the wrapping apparatus 30, and the silicon wafer 21 is held in the holder of the carrier plate 31. Set. Thereafter, both surfaces of the silicon wafer 21 are held so as to be sandwiched between the upper plate 32 and the lower plate 33, the abrasive 36 is supplied from the nozzle 34, and the sun gear 37 is interposed with the sun gear 37. By carrying out the planetary motion of the carrier plate 31 by the null gear 38, and simultaneously rotating the upper plate 32 and the lower plate 33 in a relative direction, both surfaces of the silicon wafer 21 are simultaneously wrapped.

In this manner, the silicon wafer subjected to the planarization step 13 increases the flatness of the front and back surfaces of the wafer and the parallelism of the wafer, and is cleaned in the cleaning step and sent to the next step.

Next, returning to FIG. 1, the acid etching solution is supplied to the surface of the wafer while spinning a single flattened silicon wafer, the supplied acid etching solution is spread over the entire wafer surface by centrifugal force by spin, and the entire wafer surface is etched. The surface roughness Ra of the wafer surface is controlled to 0.20 µm or less (step 14). In this single sheet type acid etching step 14, the processing altered layer introduced by a machining process such as the chamfering step 12 or the planarization step 13 is completely removed by etching. The sheet roughening using the acid etching solution is performed to control the surface roughness and the texture size of the wafer. Thereby, both the maintenance of the wafer flatness and the reduction of the wafer surface roughness at the end of the planarization step can be achieved while reducing the polishing values at the front and back surfaces of the wafer in the subsequent double-side simultaneous polishing step 16 or the single-side polishing step, respectively. Can be achieved. As for the etching allowance in this single wafer type acid etching process 14, 28-32 micrometers is preferable with 14-16 micrometers single side | surface and the total margin of a wafer front and back. By setting the etching allowance in the above range, the polishing value in the subsequent double-side simultaneous polishing step or single-side polishing step can be greatly reduced. If the etching allowance is less than the lower limit, the wafer surface roughness is not sufficiently reduced. If the load for double-sided simultaneous polishing and single-side polishing is large, and the upper limit is exceeded, the wafer flatness is impaired and the productivity in wafer manufacture is deteriorated. In this sheet type acid etching process, the surface roughness Ra of the wafer surface is controlled to 0.20 micrometer or less, Preferably it is 0.05 micrometer or less. By controlling the surface roughness Ra of the wafer surface in the above range, the polishing value in the subsequent double-side simultaneous polishing step or single-side polishing step can be reduced, the productivity of wafer manufacturing can be improved, and the cost can be reduced. If the surface roughness Ra of the wafer surface exceeds 0.20 µm, a problem arises in that the polishing value in the subsequent double-side simultaneous polishing step or single-side polishing step increases.

In this single wafer type acid etching step, as shown in FIG. 5, the single wafer spinner 40 is loaded with the silicon wafer 21. That is, the surface of the wafer 21 is held flat by the vacuum suction wafer chuck 42 disposed in the cup 41 so as to be the upper surface. Subsequently, the acid etching solution 44 is moved from the etching solution supply nozzle 43 to the upper surface of the wafer 21 while horizontally moving the etching solution supply nozzle 43 provided above the wafer 21 as indicated by the solid arrow in FIG. 5. By spin-rotating the wafer 21 by the wafer chuck 42 while supplying, the wafer surface is acid etched to remove the processed deterioration layer of the wafer surface. The acid etching liquid 44 supplied to the upper surface of the wafer 21 gradually moves while etching the processing altered layer on the wafer surface from the wafer center side to the wafer outer peripheral edge side by the centrifugal force of the spin rotation, and drops of water ( 44) to fly.

Examples of the acid etching liquid used for the single-leaf acid etching of the present invention include aqueous solutions containing hydrofluoric acid, nitric acid and acetic acid, aqueous solutions containing hydrofluoric acid, nitric acid and phosphoric acid, and further aqueous solutions containing hydrofluoric acid in hydrofluoric acid, nitric acid and phosphoric acid. Etc. can be mentioned. Among them, aqueous solutions containing hydrofluoric acid, nitric acid and phosphoric acid, and aqueous solutions containing sulfuric acid in hydrofluoric acid, nitric acid and phosphoric acid, respectively, are preferable because high flattening can be obtained. Aqueous solutions containing hydrofluoric acid, nitric acid and phosphoric acid are particularly preferable because they can achieve both high flattening and low surface roughness, and can adjust the viscosity of the etching solution within a predetermined range. In the case of the aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid, the mixing ratio of hydrofluoric acid, nitric acid and phosphoric acid contained in the aqueous solution is preferably 4.5% to 10.5%: 25.5% to 40.0%: 30.0% to 45.5% by weight. Do. In the case of the aqueous solution further containing sulfuric acid in hydrofluoric acid, nitric acid and phosphoric acid, the mixing ratio of hydrofluoric acid, nitric acid, phosphoric acid and sulfuric acid contained in the aqueous solution is 4.5% to 10.5%: 25.5% to 40.0%: 30.0% by weight. 45.5%: 12.5%-27.5% are preferable.

Moreover, the viscosity of an acid etching liquid is 10-35 mPa * sec suitably. More preferably, it is 15-25 mPa * sec. If the viscosity is less than 10 mPa · sec, the viscosity of the liquid is so low that the acid etching liquid dropped onto the upper surface of the wafer is blown off directly from the wafer surface by centrifugal force, and the wafer surface cannot be brought into uniform and sufficient contact. For this reason, it takes time to ensure sufficient etching margin, and productivity falls. When the viscosity exceeds 35 mPa · sec, the acid etching liquid dropped onto the wafer surface will stay on the upper surface of the wafer for longer than necessary. For this reason, it becomes impossible to control the in-plane and outer-circumferential shape of a wafer, and the defect which worsens wafer flatness arises.

Moreover, the surface tension of acid etching liquid is suitable for 55-60 dyne / cm. If the surface tension is less than 55 dyne / cm, the acid etching liquid dropped onto the wafer upper surface immediately blows away from the wafer surface by centrifugal force, so that the surface cannot be uniformly and sufficiently contacted with the wafer surface. For this reason, it takes time to ensure sufficient etching margin, and productivity falls. When the surface tension exceeds 60 dyne / cm, the acid etching liquid dropped on the wafer surface stays longer than necessary on the upper surface of the wafer. For this reason, the in-plane and outer-circumferential shape of a wafer cannot be controlled, and the defect which deteriorates wafer flatness arises.

The number of spin rotations for spinning the silicon wafer 21 in single wafer type etching is somewhat depending on the diameter of the silicon wafer, the viscosity of the acid etching liquid, and the supply flow rate of the acid etching liquid to be dropped, but the range is 500 to 2000 rpm. If the spin rotational speed is less than 500 rpm, the in-plane and outer circumferential shapes of the wafer cannot be controlled, resulting in a defect that deteriorates wafer flatness. When the spin rotation speed exceeds 2000 rpm, the acid etching liquid dropped onto the wafer surface is blown off directly from the wafer surface by centrifugal force, and the wafer surface cannot be brought into uniform and sufficient contact with the wafer surface. For this reason, it takes time to ensure sufficient etching margin, and productivity falls.

After acid etching the surface of the wafer 21, the surface of the wafer 21 is spin-rotated while supplying a rinse liquid such as pure water to the upper surface of the wafer 21 by a rinse liquid supply nozzle (not shown). The acid etching liquid 44 remaining in the was washed. After cleaning, the wafer 21 is spin-rotated while the supply of the rinse liquid is stopped to dry the wafer 21. Next, the wafer 21 is held upside down, and the wafer 21 is held on the wafer chuck 42 so that the back surface of the wafer 21 becomes an upper surface, and the acid etching treatment, the rinse liquid cleaning treatment and the drying treatment are similarly performed.

Next, returning to FIG. 1, double-sided simultaneous polishing for simultaneously polishing the front and back surfaces of the wafer which has completed the sheet type acid etching step 14 is performed (step 16).

As a method of simultaneously double-sided polishing, it is performed by the double-sided simultaneous polishing apparatus 50 as shown in FIG. As shown in FIG. 6, first, the carrier plate 51 is engaged with the sun gear 57 and the internal gear 58 of the double-sided simultaneous polishing apparatus 50, and the silicon wafer is held in the holder of the carrier plate 51. Set (21). Thereafter, both surfaces of the silicon wafer 21 are placed on the upper surface plate 52 having the first polishing cloth 52a attached to the polishing surface side and the lower surface plate 53 having the second polishing cloth 53a attached to the polishing surface side. While holding it, the abrasive 56 is supplied from the nozzle 54, and the carrier plate 51 is planetarily moved by the sun gear 57 and the internal gear 58, and at the same time, the top plate 52 and By rotating the lower plate 53 in the relative direction, both surfaces of the silicon wafer 21 are mirror polished simultaneously. Since the silicon wafer subjected to the sheet-mounted acid etching step 14 described above has the desired wafer surface roughness while maintaining the wafer flatness when the planarization step is finished, the wafer at this double-sided simultaneous polishing step 16 While the polishing value at the front and back surfaces can be reduced, both the maintenance of the wafer flatness and the reduction of the wafer surface roughness when the planarization step is completed can be achieved. In this double-sided simultaneous polishing step 16, the front and back surfaces of the silicon wafer are simultaneously polished while controlling the number of rotations of the upper and lower surfaces 52 and 53, respectively, so that the front and back surfaces of the wafer can be visually identified. A mirror wafer can be obtained. Thus, the productivity in wafer manufacture is greatly improved by performing the manufacturing method of the silicon wafer of this invention.

Moreover, in this embodiment, although the front and back surfaces of the wafer were polished simultaneously by double-sided simultaneous polishing, it is necessary to say that the same effect can be obtained even by polishing the wafer by one-side polishing in which the front and back surfaces of the wafer are polished one by one instead of the double-sided simultaneous polishing. There is no.

Example

Next, the Example of this invention is described in detail with a comparative example.

(Example 1)

First, a φ200 mm silicon wafer was prepared, and a silicon wafer front and back surface was wrapped using the lapping apparatus shown in FIG. 4 as a planarization step. Abrasive in the lapping process, the number of times of the Al ₂ O # 1000 using the abrasive containing a _3, a slurry flow rate of supplying 2.0L / min, 100g / ㎠ the assumed half load, assumes a half revolutions the 10rpm and hajeong The silicon wafer was planarized while controlling the half rotation speed at 40 rpm, respectively.

Next, single wafer type etching was performed on the silicon wafer which had been planarized using the single wafer type | mold spinner shown in FIG. As the etching solution, an acid etching solution in which the mixing ratio of hydrofluoric acid, nitric acid and phosphoric acid was set at weight% to hydrofluoric acid: nitric acid: phosphoric acid = 4.9%: 33.4%: 36.4%. Moreover, the spin speed in etching was controlled at 600 rpm and the flow rate of the etching liquid to be supplied at 10 liters / minute, respectively, and etching was performed for 150 seconds. The etching allowance in sheet type acid etching was 15 micrometers on one side.

(Example 2)

In the etching step, planarization was carried out in the same manner as in Example 1 except that an aqueous solution containing hydrofluoric acid, nitric acid, and acetic acid as an etching solution, each having a mixing ratio of hydrofluoric acid: nitric acid: acetic acid = 8.95%: 46.35%: 14.72% by weight%, was used. Process and the etching process were implemented.

(Comparative Example 1)

A flattening step and an etching step were performed in the same manner as in Example 1 except that batch etching was performed as shown in FIG. 9 instead of the single wafer etching.

(Comparative Example 2)

In the etching step, planarization was carried out in the same manner as in Comparative Example 1 except that an aqueous solution containing hydrofluoric acid, nitric acid and acetic acid as an etching solution, each having a mixing ratio of hydrofluoric acid: nitric acid: acetic acid = 8.95%: 46.35%: 14.72% by weight%, was used. Process and the etching process were implemented.

(Comparative Example 3)

 In the etching step, the planarization step and the etching step were performed in the same manner as in Comparative Example 1 except that 48 wt% NaOH aqueous solution was used as the etching solution.

(Comparative Example 4)

In the etching step, the planarization step and the etching step were performed in the same manner as in Comparative Example 1 except that 48 wt% KOH aqueous solution was used as the etching solution.

(Comparative Example 5)

In the lapping step, a flattening step and an etching step were performed in the same manner as in Comparative Example 1 except that an abrasive containing Al ₂ O ₃ of # 1500 was used, and an 48% by weight aqueous KOH solution was used as the etching solution in the etching step.

(Comparative Test 1)

About the silicon wafers obtained in Examples 1 and 2 and Comparative Examples 1 to 5, the wafer surface roughness and wafer flatness expressed by TTV (Total Thickness Variation) were obtained using a non-contact surface roughness machine (manufactured by Chapman). The wafer surface roughness and TTV results in the silicon wafers obtained in Examples 1 and 2 and Comparative Examples 1 to 5, respectively, are shown in FIG.

As is apparent from FIG. 7, in Comparative Examples 1 and 2, the wafer surface roughness is improved, but wafer flatness is deteriorated. In Comparative Examples 3 to 5, wafer flatness is good, but wafer surface roughness is deteriorated. Therefore, it is necessary to make large the polishing value in the double-sided simultaneous polishing process which is continued after each. On the other hand, in Examples 1 and 2, compared with Comparative Examples 1 and 2, the wafer surface roughness and wafer flatness were respectively improved, and the result which can greatly reduce the polishing value in the subsequent double-side simultaneous polishing process was obtained. .

(Comparative Test 2)

Double-sided simultaneous polishing was performed on the silicon wafers obtained in Examples 1 and 2 and Comparative Examples 1 to 5, respectively. The polishing allowance in double-sided simultaneous polishing was 5 micrometers on one side. The number of LPDs (Light Point Defects) having a size of 65 nm or more present on the wafer surface was determined using the light scattering particle counter for the obtained wafer. The relationship between the wafer surface roughness Ra and LPD number calculated | required by the said comparative test 1 is shown in FIG.

As apparent from Fig. 8, the surface roughness Ra after etching and the surface quality after polishing are highly correlated, and the surface roughness Ra of the wafer surface is 0.20 µm or less, preferably 0.15 µm or less, and after polishing It was found that good surface quality was obtained.

According to the method of manufacturing the silicon wafer of the present invention, the load of the double-sided simultaneous polishing process and the one-side polishing process is reduced, and both the maintenance of the wafer flatness and the reduction of the surface roughness of the wafer at the end of the planarization process are achieved. can do. For this reason, it can apply to the manufacturing process of a semiconductor silicon wafer.

Claims (10)

delete A planarization step of grinding or lapping the front and back surfaces of the thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot; The acid etching solution is supplied to the surface of the wafer while spinning the planarized single silicon wafer, and the acid etching solution is spread over the entire wafer surface by centrifugal force by spin, and the entire wafer surface is etched to make the surface roughness of the wafer surface. Single sheet type acid etching process which controls (Ra) to 0.20 micrometer or less, A double-sided simultaneous polishing step of simultaneously polishing the front and back surfaces of the single wafer acid-etched silicon wafer; The acid etching solution is an aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid, respectively, and the mixing ratio of hydrofluoric acid, nitric acid and phosphoric acid contained in the aqueous solution is in weight%, hydrofluoric acid: nitric acid: phosphoric acid = 4.5% to 10.5%: 25.5% to 40.0%. : 30.0% to 45.5% of the silicon wafer manufacturing method. The method according to claim 2, A method of manufacturing a silicon wafer, wherein the spin rotational speed for spinning the wafer in the sheet type acid etching step is 500 to 2000 rpm. The method according to claim 2, The viscosity of the said acid etching liquid is a manufacturing method of a silicon wafer whose 10-35 mPa * sec. The method according to claim 2, The surface tension of the said acid etching liquid is 55-60 dyne / cm, The manufacturing method of a silicon wafer. delete A planarization step of grinding or lapping the front and back surfaces of the thin disk-shaped silicon wafer obtained by slicing a silicon single crystal ingot; The acid etching solution is supplied to the surface of the wafer while spinning the planarized single silicon wafer, and the acid etching solution is spread over the entire wafer surface by centrifugal force by spin, and the entire wafer surface is etched to make the surface roughness of the wafer surface. Single sheet type acid etching process which controls (Ra) to 0.20 micrometer or less, A one-side polishing step of polishing the front and back surfaces of the single wafer acid-etched silicon wafer by one side, in this order; The acid etching solution is an aqueous solution containing hydrofluoric acid, nitric acid and phosphoric acid, respectively, and the mixing ratio of hydrofluoric acid, nitric acid and phosphoric acid contained in the aqueous solution is in weight%, hydrofluoric acid: nitric acid: phosphoric acid = 4.5% to 10.5%: 25.5% to 40.0%. : 30.0% to 45.5% of the silicon wafer manufacturing method. The method according to claim 7, A method of manufacturing a silicon wafer, wherein the spin rotational speed for spinning the wafer in the sheet type acid etching step is 500 to 2000 rpm. The method according to claim 7, The viscosity of the said acid etching liquid is a manufacturing method of a silicon wafer whose 10-35 mPa * sec. The method according to claim 7, The surface tension of the said acid etching liquid is 55-60 dyne / cm, The manufacturing method of a silicon wafer.

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