CN1610069A - Process for polishing a semiconductor wafer - Google Patents
Process for polishing a semiconductor wafer Download PDFInfo
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- CN1610069A CN1610069A CNA2004100431526A CN200410043152A CN1610069A CN 1610069 A CN1610069 A CN 1610069A CN A2004100431526 A CNA2004100431526 A CN A2004100431526A CN 200410043152 A CN200410043152 A CN 200410043152A CN 1610069 A CN1610069 A CN 1610069A
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- polishing
- semiconductor wafer
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- cloth
- polishing cloth
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- 238000005498 polishing Methods 0.000 title claims abstract description 137
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000004744 fabric Substances 0.000 claims abstract description 34
- 239000012530 fluid Substances 0.000 claims abstract description 8
- 235000012431 wafers Nutrition 0.000 claims description 90
- 238000005520 cutting process Methods 0.000 claims description 15
- 238000007517 polishing process Methods 0.000 claims description 10
- 239000010703 silicon Substances 0.000 description 42
- 229910052710 silicon Inorganic materials 0.000 description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 41
- 239000000463 material Substances 0.000 description 12
- 238000000227 grinding Methods 0.000 description 8
- 238000012545 processing Methods 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- 239000003795 chemical substances by application Substances 0.000 description 6
- 230000000052 comparative effect Effects 0.000 description 5
- KWYUFKZDYYNOTN-UHFFFAOYSA-M Potassium hydroxide Chemical compound [OH-].[K+] KWYUFKZDYYNOTN-UHFFFAOYSA-M 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 229920003023 plastic Polymers 0.000 description 4
- 229920002635 polyurethane Polymers 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 230000001771 impaired effect Effects 0.000 description 3
- 238000005259 measurement Methods 0.000 description 3
- 239000004814 polyurethane Substances 0.000 description 3
- 229920002430 Fibre-reinforced plastic Polymers 0.000 description 2
- 239000004698 Polyethylene Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000000835 fiber Substances 0.000 description 2
- 239000011151 fibre-reinforced plastic Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- -1 polyethylene Polymers 0.000 description 2
- 229920000573 polyethylene Polymers 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 241000345998 Calamus manan Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
- 239000002033 PVDF binder Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
- 238000003287 bathing Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 229910001651 emery Inorganic materials 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920002981 polyvinylidene fluoride Polymers 0.000 description 1
- 229940072033 potash Drugs 0.000 description 1
- BWHMMNNQKKPAPP-UHFFFAOYSA-L potassium carbonate Substances [K+].[K+].[O-]C([O-])=O BWHMMNNQKKPAPP-UHFFFAOYSA-L 0.000 description 1
- 235000015320 potassium carbonate Nutrition 0.000 description 1
- 235000012950 rattan cane Nutrition 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 239000012089 stop solution Substances 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/02008—Multistep processes
- H01L21/0201—Specific process step
- H01L21/02024—Mirror polishing
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B24—GRINDING; POLISHING
- B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
- B24B37/00—Lapping machines or devices; Accessories
- B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
- B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
- B24B37/08—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for double side lapping
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Engineering (AREA)
- Finish Polishing, Edge Sharpening, And Grinding By Specific Grinding Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
A process is for the simultaneous polishing of the front surface and the back surface of a semiconductor wafer between two rotating polishing plates covered with polishing cloth while a polishing fluid is supplied, the polishing cloth of the lower polishing plate having a smooth surface and the polishing cloth of the upper polishing plate having a surface which is interrupted by channels. The semiconductor wafer lying in a cutout in a carrier plate is held on a defined geometric path. The front surface of the semiconductor wafer, during polishing, is in contact with the polishing cloth of the lower polishing plate. The back surface of the semiconductor wafer, during polishing, is in contact with the polishing cloth of the upper polishing plate.
Description
Technical field
The present invention relates to a kind of method of polishing of semiconductor wafers, this method can obtain the improvement nanometer position phase of polishing of semiconductor wafers.This type of semiconductor wafer is applicable to semi-conductor industry, is particularly useful for the making of electronic component.
Background technology
The predetermined making live width that is applicable to is less than or equal to the semiconductor wafer of 0.1 micron electronic component and must be had many particular characteristics.A wherein most important performance is a known semiconductor wafer nanometer position phase.
" semiconductor equipment and material " (SEMI) to " nanometer position phase " (nanotopology) or " nanometer configuration " (nanotopography) definition of a speech be: the flatness deviation of entire wafer front (front surface) is in the scope of space wavelength 0.2 to 20 millimeter (side correlation length) and be positioned at " be suitable for district " (FQA: fixing suitable application region; Must satisfy the surf zone of characteristic that product specification requires).The nanometer position is measured by the overlapping of measurement field of scanning and utilize different sizes fully on entire wafer surface.In measuring the field, these do not find that surperficial height change (peak is to paddy) can surpass the desired maximum of entire wafer.A big or small visual gauge model that measures and deciding for example, can be defined as 2 * 2 square millimeters, 5 * 5 square millimeters and 10 * 10 square millimeters.
The final nanometer position of semiconductor wafer is processed to form by polishing.Be the evenness of improvement semiconductor wafer, be showing improvement or progress day by day and sustainable development in order to the device and method on the positive and negative two sides of while polishing of semiconductor wafers.
For example, once addressed so-called twin polishing in the U.S. Pat 3691694.Specific embodiment according to twin polishing described in European patent EP 208315 B1, under the situation that has polishing liquid to exist, the semiconductor wafer of the carrier disk that is positioned at cutting frame (or grooving) with appropriate size and is made by metal or plastics is two path movement of being scheduled to along machine and machined parameters between coated with the rotary finishing dish of polishing cloth, thereby polished (in expert's document, carrier disk is also referred to as template).
For example, once addressed among German patent DE 10004578 C1 and utilize one to implement the twin polishing step by even, that the porous polymer foamed material is made, hardness is 60 to 90 (Shore A) polishing cloth.The document also discloses that following content, the polishing cloth that promptly sticks on the polishing disk has the groove net, and the polishing cloth that sticks to down on the polishing disk then has smooth surface and do not have any this class texture or structure.The purpose of this measure is, one is guaranteed the even distribution of used polishing grinding agent in the polishing process; Its two, semiconductor wafer sticks on the polishing cloth when preventing that going up polishing disk after polishing from finishing lifts.
For implementing twin polishing, the semiconductor die wafer is inserted in the interior cutting frame of carrier disk, so that the back side of semiconductor wafer (or reverse side) is held on down on the polishing disk by this way.Therefore, in polishing process, the back side of semiconductor wafer is by the no lines polishing cloth polishing that sticks to down on the polishing disk, and the front of semiconductor wafer is polished by the lines polishing cloth that has that sticks on the polishing disk.This semi-conductive front is the predetermined surface that makes electronic component in the above.After polishing step, this semiconductor wafer for example is transferred in the water-bath by means of a vacuum suction apparatus usually.
This method of prior art can not satisfy implementing the growing requirement of twin polishing for the nanometer position phase of the semiconductor wafer of new-type element use from generation to generation in future.Therefore, the purpose of this invention is to provide a kind of method, this method can make the semiconductor wafer with improvement nanometer position phase, can satisfy the requirement of making the specific demand element.
Summary of the invention
The present invention propose a kind of for have under the situation of polishing fluids in two coated with the rotary finishing dish of polishing cloth between the front of polishing of semiconductor wafers and the method at the back side simultaneously, the polishing cloth of following polishing disk has a smooth surface, the surface of the polishing cloth of last polishing disk by groove in addition at interval, semiconductor wafer is positioned at the cutting frame of a carrier disk and remains on the geometric path of determining, wherein, in polishing process, the front of semiconductor wafer contacts with the polishing cloth of following polishing disk, and in polishing process, the back side of semiconductor wafer contacts with the polishing cloth of last polishing disk.
The semiconductor wafer of processed starting products for being split to form from a crystal with known method, it is for example separated from a silicon single crystal, be cut into certain-length and by grinding in addition round edge, its front and/or the back side are by means of grinding or the lappingout step is processed.The edge of semiconductor wafer also can be in the somewhere of processing sequence by means of the abrasive wheel of suitable profile rounding in addition.Moreover, after grinding steps, also can be with the surface etching in addition of semiconductor wafer.
According to the present invention, when preparing to implement twin polishing, by this way semiconductor wafer is inserted in the cutting frame (cutout) of a carrier disk (carrier plate), so that its front is held on down on the polishing cloth of polishing disk.Therefore, in the process of implementing twin polishing, the front of semiconductor wafer contacts with the smooth polishing cloth of following polishing disk, and the back side of semiconductor wafer contacts with the lines polishing cloth that has of last polishing disk.Otherwise twin polishing processing is implemented according to being skillful in the known mode of this operator.
This method gained final products are to have implemented twin polishing and had the semiconductor wafer of significantly improveing nanometer position phase.
In principle, method of the present invention can be used for making the object that is wafer shape, and it is by adopting chemical-mechanical twin polishing method material processed to be formed.For example, this class material is further processed being mainly used in the semi-conductor industry, but it is not limited to this kind particular application, and for example comprises: silicon, silicon-germanium, silicon dioxide, silicon nitride, GaAs and other III-V semiconductors.Wherein, for example the silicon of the monocrystalline form by left Kolaski crystal pulling method or the crystallization of floating zone band crystal pulling method is good.Especially better with silicon with (100), (110) or (111) crystal orientation.
This method be particularly suited for making diameter be 200 millimeters, 300 millimeters, 400 millimeters, 450 millimeters and thickness from hundreds of microns the silicon wafer to several centimetres (better with 400 microns to 1200 microns especially).This semiconductor wafer can be directly used in the parent material of making semiconductor element, or implement after the final polishing step and/or after coated several layers (for example backside seal layer or the positive extension coating that forms with silicon or other suitable semi-conducting materials) handles afterwards and/or by means of heat treatment according to prior art, the purposes that can be used for being scheduled to.
Embodiment
Be example now, method of the present invention is made further instructions to make silicon wafer.
In principle, through utilizing the cutting of annular saw or scroll saw to form and apparent diameter and sawing method kind and having surely undermines the silicon wafer that lattice reaches 10 to 40 microns zone deeply and can directly impose the twin polishing step according to the present invention.But, before implementing twin polishing, preferably by means of the emery wheel of suitable profile or profile with clear definition (having sharp interface) and therefore mechanical extremely sensitive Waffer edge rounding in addition.In addition, for improved geometric shape and part remove impaired crystal layer, can impose mechanical lapping step (for example lappingout or grinding) to this silicon wafer, to reduce the material amount of removing in the polishing step of the present invention.For the crystal region that removes in the mechanical processing steps unavoidable impaired wafer surface and edge and remove any impurity that may occur (for example metal impurities that are sticked together with impaired part), herein can be succeeded by etching step.The execution mode of this etching step can be in alkalescence or acid etching mixture silicon wafer to be carried out wet-chemical treatment or plasma treatment.
For example, once addressed a kind of Twp-sided polishing machine of commercially available appropriate size among the technical report TR 22.2342 of IBM Corporation, this Twp-sided polishing machine can be used for implementing polishing step of the present invention.This polishing machine mainly comprises: a following polishing disk that can in horizontal plane, rotate freely and can in horizontal plane, rotate freely on polishing disk, above-mentioned polishing disk is all coated with polishing cloth, and can impose material to the two sides of semiconductor wafer (being silicon wafer) herein and remove polishing action, be provided with the polishing fluids of suitable chemical constituent simultaneously continuously.
Can only polish a silicon wafer.But, usually,, be good to polish a plurality of silicon wafers simultaneously for saving cost, actual number is then decided on the structure of polishing machine.These silicon wafers remain on the geometric path, this path by polishing machine and carrier disk the machined parameters in polishing process determine that this carrier disk has the cutting frame that is enough to keep silicon wafer.For example, by means of needle pin gear drive or Involutes Gears Transmission (rotating sold inside the country or roughly relative rotation export trade or the ring gear of ring gear and) carrier disk is contacted with polishing machine, thereby carrier disk can rotatablely move between two polishing disks via one.
In the polishing operation process, influence the example of parameter that silicon wafer is relevant to the path of upper and lower polishing disk and comprise: the size of polishing disk, the design of carrier disk and go up polishing disk, the rotating speed of polishing disk and carrier disk down.If always there is a silicon wafer in the central authorities of carrier disk, silicon wafer then moves along a circle around the polishing machine center.If many silicon wafers are placed in the carrier disk prejudicially, carrier disk then forms a hypocycloid path around the rotation of self axis.Polishing processing of the present invention is good with the hypocycloid path.Especially to use four to six carrier disks (each carrier disk be loaded with at least three at interval be arranged in a silicon wafer circular path on rule) better simultaneously.
In principle, the used carrier disk of the inventive method can be made by any material, and these materials have enough mechanical stabilities to driving caused mechanical load (especially compression and tensile load).In addition, this material must not be subjected to the great chemistry and the machinery infringement of used polishing fluids and polishing cloth, with enough useful life of guaranteeing carrier disk and prevent to polish the back silicon wafer and polluted.In addition, it is smooth, unstressed and do not have a up-and-down carrier disk that this material must be suitable for making the height with expection thickness and geometry.In principle, for example, these carrier disks can be made by the metal of metal, plastics, fiber-reinforced plastic or coating plastic.Preferably, this carrier disk is made by steel or fiber-reinforced plastic.More preferably, this carrier disk is made by stainless steel.
Carrier disk has one or more cutting frame (being good with circle especially), to keep or to hold one or more silicon wafer.For guaranteeing that silicon wafer can move freely in the carrier disk in rotation, the diameter of cutting frame is must more polished silicon wafer bigger.With slightly larger in diameter is good for 0.1 to 2 millimeter, better with 0.3 to 1.3 millimeter of slightly larger in diameter especially.For preventing that Waffer edge is damaged by the inner edge of the cutting frame in the carrier disk in the polishing process, such as among European patent EP 208315 B1 suggestion, the inboard of cutting frame preferably adds last layer and carrier disk thick plastic gasket equally.
Described in German patent DE 19905737 A1, the thickness of the used carrier disk of finishing method of the present invention is good with 400 to 1200 microns, and rule is better with the final thickness of looking the silicon wafer through polishing especially.The silicon amount of removing in the polishing step is good with 5 to 100 microns, but preferable, better with 20 to 50 microns especially with 10 microns to 60 microns.
In the content that the semiconductor wafer orientation at face down describes, the twin polishing step is preferably implemented to be skillful in the known mode of this operator.Polishing cloth with popularity energy range is all commercially available.Preferably utilizing commercially available, hardness is that polyurethanes ((being the polyurethane)) polishing cloth of 40 to 120 (Shore A) is implemented polishing action.Especially be that the polyurethanes polishing cloth of 60 to 90 (Shore A) is better to mix with polyethylene fibre, hardness.Under the situation of polished silicon wafer, suggestion is provided with the polishing fluids that the pH value is 9 to 12 (better with 10 to 11 especially) continuously, and it includes percentage by weight be 1 to 10% SiO of (being 1 to 5% better with percentage by weight especially) in water
2, polish pressure is good, better with 0.1 to 0.3 especially with 0.05 to 0.5 crust.It is good, better with 0.4 to 0.9 micron/minute especially with 0.1 to 1.5 micron/minute that silicon removes speed.
Semiconductor wafer after the polishing when unloading on the following polishing disk, is preferably placed this semiconductor wafer on the one standard processing support, further it being handled, and make its surface in procedure of processing subsequently, be correct orientation.Compare with traditional double mirror polish when semiconductor wafer polishing (wherein face up),, needing then can avoid semiconductor wafer Rotate 180 ° if the support of holding semiconductor wafer is configured to Rotate 180 °.This work is with manually unloading or robot unloads automatically all and can obtain same excellent results.When being contained in down semiconductor wafer on the polishing disk, the work of above-mentioned character also can be imagined.
Semiconductor wafer after the polishing can be by manually or by means of an automatic mobile device taking off on the polishing disk down certainly; In both cases, be good to use vacuum suction apparatus.German patent DE 19958077 A1 (the 6th page, the 23rd to 30 row) once addressed a kind of suitable vacuum suction apparatus.After on polishing disk, taking off, preferably immediately semiconductor wafer is sent into (especially with water-bath Nei Gengjia) in the liquid bath.Like this, can effectively prevent to polish grinding agent becomes dry and prevents at vacuum suction apparatus or form the marking in the mobile device more in a broad aspect.
After polishing machines, any polishing fluids that adheres to is washed on silicon wafer and wafer is dried.
Decide on its further purposes, the front of these wafers may need to impose final polishing according to prior art, for example utilizes a soft polishing cloth to reach by means of a SiO
2Base alkaline polishing fluid.
Example:
Following experimental example and comparative example use a commercially available AC 2000P
2Type Twp-sided polishing machine (those moral Wal Te Si companies produce, Lun Zibao, Germany).This polishing machine is equipped with five stainless chromium steel systems, has the lappingout surface, thickness is 720 microns carrier disk, it is 200.5 millimeters circle cutting frame that each carrier disk has six internal diameters, these cutting frames with rule or equal pitch arrangement on a circular path and lining with polyvinylidene fluoride layer, it is 200 millimeters silicon wafer that every batch of this polishing machine can polish 30 diameters simultaneously.Upper and lower polishing disk coated with commercially available by Rhodel Corp make, brand name is that SUBA500, hardness are 74 (Shore A), the polyurethanes polishing cloth strengthened with polyethylene fibre.Tight polishing cloth on following polishing disk has smooth surface, the surface of tight polishing cloth on last polishing disk has that milling forms, width is that 1.5 millimeters and the degree of depth are 0.5 millimeter, are the formed checkerboard pattern of the circular groove of part, and these grooves are with 30 millimeters pitch arrangement.
Comparative example
In each case, having etched surfaces, diameter with manual mode with 30 is that 200 millimeters silicon wafer is inserted in the cutting frame of carrier disk, and it is faced up.In implementing polishing processing, be provided with water-based polished grinding agent (Levasil 200 types, Beyer Co., Ltd produce Lie Fokusen, Germany) continuously, it has percentage by weight is 3.1% fixedly SiO
2Solids content, the pH value is set at 11.4 by adding potash and potassium hydroxide.This polishing processing is that 0.2 crust and upper and lower polishing disk temperature are always implemented under 38 ℃ the situation at pressure, and its material removal rate is 0.58 micron/minute.Remove 15 microns silicon from each surface of wafer.Thickness at polished wafer has reached after 725 microns, stops supply polishing grinding agent, and replaces supply and stop agent (stoppingagent), and lasts 2 minutes.It is used that to stop agent be that Japanese rattan sees that the percentage by weight of Glanzox 3600 types that company produces is 1% the aqueous solution.After stopping the step termination, equipment to be opened, the silicon wafer that is positioned at carrier disk is then wetting by stop solution fully.Utilize commercially available, that moral Wal Te Si companies make unloads and get the station and silicon wafer is delivered to the support that is arranged in water-bath.Afterwards, in the cleaning equipment these silicon wafers are dried one, the bathing of this equipment is in proper order: tetramethyl ammonium hydroxide (TMAH)/H in batches
2O
2HF/HCl: ozone; HCl and utilize a commercially available drying unit and according to the Ma Langeni operate.Utilize measurement 2 millimeters * 2 millimeters (HCT 2 * 2) and 10 millimeters * 10 millimeters (HCT 10 * 10) on an ADE SQM CR83 device, to measure mutually through the nanometer position of clean wafers.Amount to 1968 silicon wafers of polishing, subsequently its nanometer position is measured mutually.
Experimental example
To amount to 2157 in the mode that is similar to comparative example, to have etched surfaces, diameter be that 200 millimeters silicon wafer is handled.Unique different with comparative example be to insert the face down of the silicon wafer of carrier disk cutting frame, afterwards along this orientation polishing.The statistic analysis result that gained nanometer position is worth mutually is as shown in following table.
| Comparative example: 1968 silicon wafers | Experimental example: 2157 silicon wafers | |||
| Measure the field | ????HCT?2×2 | ??HCT?10×10 | ????HCT?2×2 | ????HCT?10×10 |
| On average | ????18.50 | ??40.48 | ????15.24 | ????33.06 |
| Standard deviation | ????4.87 | ??9.65 | ????2.06 | ????5.66 |
As can be seen, if these silicon wafers polish in the mode of face down, for the measurement field of two kinds of sizes, the nanometer position of silicon wafer all can obtain significantly to improve mutually from The above results.
Claims (3)
- One kind for have under the situation of polishing fluids in two coated with the rotary finishing dish of polishing cloth between the method at polishing of semiconductor wafers front and the back side simultaneously, the polishing cloth of following polishing disk has a smooth surface, the surface of the polishing cloth of last polishing disk by groove in addition at interval, semiconductor wafer is positioned at the cutting frame of a carrier disk and remains on the geometric path of determining, wherein, in polishing process, the front of semiconductor wafer contacts with the polishing cloth of following polishing disk, and in polishing process, the back side of semiconductor wafer contacts with the polishing cloth of last polishing disk.
- 2. the method for claim 1 is characterized in that, after polish simultaneously at front and the back side, by means of a vacuum suction apparatus this semiconductor wafers is transferred in the water-bath.
- 3. method as claimed in claim 1 or 2 is characterized in that, after polish simultaneously at front and the back side, the front of this semiconductor wafer is imposed final polishing.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE10321940.4 | 2003-05-15 | ||
| DE10321940 | 2003-05-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1610069A true CN1610069A (en) | 2005-04-27 |
Family
ID=33394633
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2004100431526A Pending CN1610069A (en) | 2003-05-15 | 2004-05-12 | Process for polishing a semiconductor wafer |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20040229548A1 (en) |
| JP (1) | JP2004343126A (en) |
| KR (1) | KR20040098559A (en) |
| CN (1) | CN1610069A (en) |
| TW (1) | TWI244691B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101106082B (en) * | 2006-07-13 | 2011-07-06 | 硅电子股份公司 | Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness |
| CN102696096A (en) * | 2010-01-05 | 2012-09-26 | 住友电气工业株式会社 | Method and apparatus for processing compound semiconductor wafer |
| CN104152994A (en) * | 2010-10-20 | 2014-11-19 | 硅电子股份公司 | Support ring for supporting a semiconductor wafer composed of monocrystalline silicon during a thermal treatment, method for the thermal treatment of such a semiconductor wafer, and thermally treated semiconductor wafer composed of monocrystalline silicon |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4092993B2 (en) * | 2002-09-13 | 2008-05-28 | 信越半導体株式会社 | Single crystal growth method |
| DE202006004193U1 (en) * | 2006-03-14 | 2006-06-08 | Richter, Harald | Adapter plate for a vacuum suction device |
| JP5401683B2 (en) * | 2008-08-01 | 2014-01-29 | 株式会社Ｓｕｍｃｏ | Double-sided mirror semiconductor wafer and method for manufacturing the same |
| DE102009025242B4 (en) * | 2009-06-17 | 2013-05-23 | Siltronic Ag | Method for two-sided chemical grinding of a semiconductor wafer |
| DE102009030292B4 (en) * | 2009-06-24 | 2011-12-01 | Siltronic Ag | Method for polishing both sides of a semiconductor wafer |
| WO2016142237A1 (en) * | 2015-03-11 | 2016-09-15 | Nv Bekaert Sa | Carrier for temporary bonded wafers |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3691694A (en) * | 1970-11-02 | 1972-09-19 | Ibm | Wafer polishing machine |
| JPH09270401A (en) * | 1996-01-31 | 1997-10-14 | Shin Etsu Handotai Co Ltd | Polishing method of semiconductor wafer |
| JP3664593B2 (en) * | 1998-11-06 | 2005-06-29 | 信越半導体株式会社 | Semiconductor wafer and manufacturing method thereof |
| US6227944B1 (en) * | 1999-03-25 | 2001-05-08 | Memc Electronics Materials, Inc. | Method for processing a semiconductor wafer |
| DE20004223U1 (en) * | 1999-10-29 | 2000-08-24 | Peter Wolters Werkzeugmaschinen GmbH, 24768 Rendsburg | Device for removing semiconductor wafers from the rotor wafers in a double-sided polishing machine |
| US6376395B2 (en) * | 2000-01-11 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
| US6376335B1 (en) * | 2000-02-17 | 2002-04-23 | Memc Electronic Materials, Inc. | Semiconductor wafer manufacturing process |
| US20010024877A1 (en) * | 2000-03-17 | 2001-09-27 | Krishna Vepa | Cluster tool systems and methods for processing wafers |
| DE10058305A1 (en) * | 2000-11-24 | 2002-06-06 | Wacker Siltronic Halbleitermat | Process for the surface polishing of silicon wafers |
| DE10117612B4 (en) * | 2001-04-07 | 2007-04-12 | Infineon Technologies Ag | polishing system |
| US6582279B1 (en) * | 2002-03-07 | 2003-06-24 | Hitachi Global Storage Technologies Netherlands B.V. | Apparatus and method for reclaiming a disk substrate for use in a data storage device |
-
2004
- 2004-05-12 US US10/843,778 patent/US20040229548A1/en not_active Abandoned
- 2004-05-12 KR KR1020040033533A patent/KR20040098559A/en not_active Application Discontinuation
- 2004-05-12 CN CNA2004100431526A patent/CN1610069A/en active Pending
- 2004-05-12 TW TW093113373A patent/TWI244691B/en active
- 2004-05-14 JP JP2004145370A patent/JP2004343126A/en not_active Abandoned
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101106082B (en) * | 2006-07-13 | 2011-07-06 | 硅电子股份公司 | Method for the simultaneous double-side grinding of a plurality of semiconductor wafers, and semiconductor wafer having outstanding flatness |
| CN102696096A (en) * | 2010-01-05 | 2012-09-26 | 住友电气工业株式会社 | Method and apparatus for processing compound semiconductor wafer |
| CN104152994A (en) * | 2010-10-20 | 2014-11-19 | 硅电子股份公司 | Support ring for supporting a semiconductor wafer composed of monocrystalline silicon during a thermal treatment, method for the thermal treatment of such a semiconductor wafer, and thermally treated semiconductor wafer composed of monocrystalline silicon |
| CN104152994B (en) * | 2010-10-20 | 2017-04-05 | 硅电子股份公司 | For the support ring, the method for this semiconductor wafer of heat treatment and the semiconductor wafer that support semiconductor wafer in heat treatment process |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI244691B (en) | 2005-12-01 |
| KR20040098559A (en) | 2004-11-20 |
| US20040229548A1 (en) | 2004-11-18 |
| JP2004343126A (en) | 2004-12-02 |
| TW200425322A (en) | 2004-11-16 |
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