KR20040071713A - Constant-current circuit, drive circuit and image display device - Google Patents

Abstract

The first amplifier circuit 132 included in the voltage generating circuit 114 includes a differential circuit constituted by the P-type TFT elements P101 and P102 and the N-type TFT elements N101 and N102, and the constant current circuit 150a, 150b) and an N-type TFT element N103. The constant current circuits 150a and 150b include P-type TFT elements P132a and P132b, capacitors C132a and C132b, switches S104a to S106a, S104b to S106b, and resistors R132a and R132b. The capacitors C132a and C132b maintain the voltages of the nodes 204 and 208 when the voltage is set, that is, when a current is supplied to the P-type TFT elements P132a and P132b to be diode-connected.

Description

Constant current circuit, drive circuit and image display device {CONSTANT-CURRENT CIRCUIT, DRIVE CIRCUIT AND IMAGE DISPLAY DEVICE}

Constant current circuits that allow a constant current to flow regardless of load variations are one of the basic and most important circuits in semiconductor integrated circuits.

Conventionally, it is common to use a current mirror type circuit for a constant current circuit. In the current mirror type constant current circuit, one transistor of two transistors to which each gate is connected is diode-connected, and the capability ratio of both transistors (specifically, the ratio of channel width) to a constant reference current flowing through the transistor. A double constant current can flow through the other transistor connected to the load circuit at an independent potential.

In this current mirror type constant current circuit, the current setting accuracy depends on whether or not the current driving capability of the transistor constituting the current mirror is as designed. Generally, the drive current Id of a transistor is represented by following formula (1).

Id = β (Vgs-Vth) ² ... (One)

Here, Vgs represents the gate voltage, Vth represents the threshold voltage, and β represents the conductance. That is, the accuracy of setting the drive current is influenced by the conductance β and the gate voltage, that is, the power supply voltage, determined by the transistor manufacturing process, and also by the threshold voltage Vth of the transistor.

In Japanese Patent Laid-Open No. 5-191166, in order to be able to set a desired driving current without being influenced by the threshold voltage Vth of the transistors constituting the current mirror, the first transistor having a drain connected to the gate through the resistor R; The gate is connected to the drain of the first transistor, and the second transistor having the same capability ratio as that of the first transistor is driven in a current mirror circuit having a capability ratio of two transistors of K: 1, thereby changing the current variation with respect to the manufacturing deviation. A constant current circuit which can be made small and which can set a current irrespective of threshold voltages of the first and second transistors is disclosed.

However, the constant current circuit using the current mirror including the constant current circuit described in Japanese Patent Laid-Open No. 5-191166 is based on the premise that the threshold voltages Vth of the two transistors constituting the current mirror are the same. For example, in the constant current circuit described in Japanese Patent Laid-Open No. 5-191166, the first and second transistors also constitute a current mirror, and the threshold voltages Vth of the first and second transistors are the same. The threshold voltages of the two transistors constituting the current mirror circuit for driving the first and second transistors are also assumed to be the same.

In other words, in the two transistors constituting the current mirror circuit, the threshold voltage Vth1 of the transistor through which the reference current flows (hereinafter also referred to as a "reference transistor") and the transistor through which the drive current flows (hereinafter referred to as "drive transistor"). When the threshold voltage Vth2 is different, the set accuracy of the driving current deteriorates. When the threshold voltage Vth2 is larger than the threshold voltage Vth1, the driving transistor becomes non-conductive even when the reference transistor is conducting, and the driving current may not flow.

In particular, in a polysilicon thin film transistor (hereinafter, also referred to as "TFT" or "TFT element") formed on a glass substrate or a resin substrate, a transistor formed on a silicon substrate (hereinafter referred to as "TFT" The variation in the threshold voltage is large compared to the " bulk transistor. &Quot;

In recent years, in the field of flat-panel displays, a TFT liquid crystal display device and an electroluminescent display device (hereinafter referred to as "EL display device") composed of low-temperature polysilicon type TFTs that have been noted for several years. It is desired to integrally mold peripheral circuits conventionally constituted by externally attached LSIs on the same glass substrate as the image display unit. This is because the image display apparatus can be miniaturized if the peripheral circuit and the peripheral circuit can also be integrally formed on the same glass substrate.

On the other hand, in these image display apparatuses, gradation display is performed by changing the voltage applied to the pixel. That is, in the liquid crystal display device, the voltage modulation method which changes the transmittance | permeability of a liquid crystal by changing the voltage applied to a pixel is generally employ | adopted. Further, in the EL display device, the display luminance of the organic light emitting diode is changed by changing the current applied to the organic light emitting diode, which is a current drive type light emitting element set for each pixel, by changing the voltage applied to the pixel.

As one of the peripheral circuits of these image display apparatuses, a voltage generation circuit for generating a plurality of voltages (hereinafter also referred to as " gradation voltages ") for driving a pixel with display luminance according to image data is provided. For this voltage generating circuit provided with gray scale display, high operation stability is required, and in order to achieve the high stable operation, the stable operation of the constant current circuit included in the voltage generating circuit becomes important.

Also in the driving circuit (analog amplifier) which receives the gray scale voltage generated by the voltage generating circuit and outputs the display voltage corresponding to the gray scale voltage to the data line to which the pixel is connected, similarly to the voltage generating circuit, the operation is high. Stability is required and output of high precision display voltage without offset is required. Also in the stable and high precision operation of this drive circuit, the stable operation of the constant current circuit included therein becomes important.

However, as described above, if the voltage generating circuit or the driving circuit included in the peripheral circuit is integrally formed on the same glass substrate at the same time as the image display section for the purpose of miniaturization of the apparatus, and the circuit is constituted by the TFT, the constant current circuit composed of the TFT The above-mentioned problems arise remarkably, and as a result, the manufacturing efficiency of these image display apparatuses is greatly reduced.

(Initiation of invention)

The present invention has been made to solve such a problem, and an object thereof is to provide a constant current circuit in which the influence of variation in the threshold voltage of the transistors constituting the circuit is eliminated.

Further, another object of the present invention is to provide a driving circuit having a constant current circuit that eliminates the influence of variations in threshold voltages of the transistors constituting the circuit.

Further, another object of the present invention is to provide an image display apparatus having a constant current circuit and / or a drive circuit including such a constant current circuit that excludes the influence of variation in the threshold voltage of the transistors constituting the circuit.

According to the present invention, the constant current circuit is determined according to the transistor connected between the first node and the second node and the threshold voltage of the transistor, and also maintains a voltage for holding the first voltage for turning on the transistor. A circuit is provided, and a transistor receives a first voltage at a gate, makes a current at a first node constant, and a differential circuit is connected to the first node.

Further, according to the present invention, an image display apparatus includes a plurality of image display elements arranged in a matrix, a plurality of scan lines arranged in correspondence with rows of the plurality of image display elements, and sequentially selected at predetermined cycles, and a plurality of A plurality of data lines arranged in correspondence with the columns of the image display element, a voltage generation circuit for generating at least one voltage level corresponding to the display luminance in each of the plurality of image display elements, and at least one generated by the voltage generation circuit The voltage level indicated by the pixel data corresponding to each of the image display elements of the scanning target row and the voltage level indicated by the pixel data corresponding to each of the image display elements of the scanning target row. A data line driver for selecting from a level and for activating a plurality of data lines at the selected voltage level, the at least one buffer Each of the furnaces comprises an internal circuit which inputs any one of at least one voltage level and amplifies and outputs a current, and a constant current circuit which allows a constant current to flow through the internal circuit. The constant current circuit includes an internal circuit and a first node. And a voltage holding circuit which is determined according to the threshold voltage of the transistor and which holds the first voltage for turning on the transistor, wherein the transistor receives the first voltage at the gate, and Make the current in the circuit constant.

In addition, according to the present invention, a driving circuit is a driving circuit for outputting an output voltage according to an input voltage, the first transistor being connected between a first power node and an output node, an output node and a second power node. And an offset compensating circuit for compensating an offset voltage generated according to the threshold voltage of the first transistor, wherein the offset compensating circuit maintains the offset voltage and maintains the offset voltage as much as the input voltage. Outputs the first voltage shifted to the gate electrode of the first transistor, and the constant current circuit is determined according to the threshold voltage of the second transistor and the second transistor connected between the output node and the second power supply node, And a first voltage holding circuit for holding a second voltage for turning on the second transistor, wherein the second transistor receives the second voltage at the gate electrode, The current in the first transistor connected to the output node is made constant, and the first transistor receives the first voltage output from the offset compensation circuit to the gate electrode, and outputs the input voltage and the output voltage above the coin to the output node. do.

According to the present invention, the driving circuit includes a first transistor of a first conductivity type connected between a first power supply node and an output node in a driving circuit for outputting an output voltage according to an input voltage, and an output node. A first constant current circuit connected between the second power supply node and the second power supply node, a level shift circuit that receives the first voltage and outputs a second voltage obtained by shifting the received first voltage by a predetermined amount; An offset compensation circuit for compensating an offset voltage generated according to the threshold voltage of the first transistor of the first transistor, wherein the level shift circuit is connected between the third power supply node and the gate electrode of the first transistor of the first conductivity type. And a second constant current circuit and a first transistor of a second conductivity type connected between the gate electrode of the first transistor of the first conductivity type and the fourth power supply node, wherein the offset compensation circuit is of the first conductivity type. First transistor Maintains the voltage difference between the threshold voltage of the first transistor of the second conductivity type and the voltage obtained by shifting the input voltage by the voltage difference maintained as the first voltage. The first constant current circuit is determined according to the threshold voltages of the first transistor of the first conductivity type and the second transistor of the first conductivity type connected between the output node and the second power supply node. And a first voltage holding circuit holding a third voltage for turning on the second transistor of the first conductivity type, wherein the second transistor of the first conductivity type receives the third voltage at the gate electrode and outputs the output node. The current in the first transistor of the first conductivity type connected to is kept constant, and the second constant current circuit is connected to the second power supply node and the gate electrode of the first transistor of the first conductivity type. Brother's second transition And a second voltage holding circuit which is determined according to the threshold voltage of the second transistor of the second conductivity type and which holds a fourth voltage for turning on the second transistor of the second conductivity type, The second transistor of the conductivity type receives the fourth voltage at the gate electrode, makes the current in the first transistor of the second conductivity type connected to the gate electrode of the first transistor of the first conductivity type constant, and the second voltage. The first transistor of the conductivity type receives the first voltage output from the offset compensation circuit to the gate electrode and receives the second voltage obtained by shifting the first voltage by the threshold voltage of the first transistor of the second conductivity type. Outputs to the gate electrode of the first transistor of the type, and the first transistor of the first conductivity type applies the second voltage output from the level shift circuit to the gate electrode, and inputs the input voltage and the output voltage of the coin to the output node. Exodus The.

Further, according to the present invention, an image display apparatus includes a plurality of image display elements arranged in a matrix, a plurality of scan lines arranged in correspondence with rows of the plurality of image display elements, and sequentially selected at predetermined cycles, and a plurality of A plurality of data lines arranged in correspondence with the columns of the image display elements, a voltage generating circuit for generating at least one voltage corresponding to the display luminance in each of the plurality of image display elements, and a corresponding image display element in each of the scanning target rows A decode circuit for selecting a voltage indicated by the pixel data from at least one voltage for each image display element of a scanning target row, a voltage selected by the decode circuit from a decode circuit, and activating a plurality of data lines with corresponding voltages The above-described driving circuit is provided.

In the constant current circuit according to the present invention, there is provided a voltage holding circuit that maintains a voltage set based on a threshold voltage of a driving transistor through which a current flows, and the driving transistor receives a voltage held by the voltage holding circuit at a gate to receive a current. To flow.

Therefore, according to the present invention, even if there is a manufacturing variation in the threshold voltage of the drive transistor, the influence is eliminated and the operation of the constant current circuit is stable.

As the operation of the constant current circuit is stabilized, the operation of the drive circuit and the image display device provided therewith is also stable.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a constant current circuit, a drive circuit, and an image display device, and more particularly, to a constant current circuit, a drive circuit, and an image display device in which the influence of the characteristics of a transistor constituting a circuit is eliminated.

1 is a circuit diagram showing the configuration of a constant current circuit according to the first embodiment of the present invention.

FIG. 2 is a view showing an operating state at the time of current driving of the constant current circuit shown in FIG.

3 is a circuit diagram showing the configuration of a constant current circuit according to a second embodiment of the present invention.

FIG. 4 is a diagram showing an operating state at the time of current driving of the constant current circuit shown in FIG.

Fig. 5 is a circuit diagram showing the configuration of the differential amplifier according to the third embodiment of the present invention.

Fig. 6 is a diagram showing an operating state when the differential amplifier according to the third embodiment of the present invention is activated.

FIG. 7 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 5.

Fig. 8 is a circuit diagram showing the construction of a differential amplifier according to a fourth embodiment of the present invention.

Fig. 9 is a diagram showing an operating state at the time of activation of the differential amplifier according to the fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 8.

Fig. 11 is a schematic block diagram showing the overall configuration of a color liquid crystal display device according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing the configuration of a pixel shown in FIG. 11.

FIG. 13 is a circuit diagram showing the configuration of the voltage generating circuit shown in FIG.

FIG. 14 is a circuit diagram showing the configuration of the buffer circuit shown in FIG.

FIG. 15 is a circuit diagram showing a configuration of the first amplifier circuit shown in FIG. 14.

FIG. 16 is a circuit diagram showing a configuration of a second amplifier circuit shown in FIG. 14.

17 is a circuit diagram showing a configuration of a pixel of an EL display device according to a sixth embodiment of the present invention.

18 is a schematic block diagram showing the overall configuration of a color liquid crystal display device according to a seventh embodiment of the present invention.

FIG. 19 is a circuit diagram showing the configuration of the analog amplifier shown in FIG.

20 is a circuit diagram showing a configuration of the analog amplifier in Example 8. FIG.

Fig. 21 is a circuit diagram showing the construction of an analog amplifier according to the ninth embodiment.

Fig. 22 is a circuit diagram showing the configuration of the analog amplifier in the tenth embodiment.

Fig. 23 is a circuit diagram showing the configuration of the analog amplifier in the eleventh embodiment.

FIG. 24 is a circuit diagram showing the configuration of the analog amplifier in Example 12. FIG.

FIG. 25 is a circuit diagram showing the configuration of the analog amplifier in Example 13. FIG.

Fig. 26 is a circuit diagram showing the configuration of the analog amplifier in the fourteenth embodiment.

EMBODIMENT OF THE INVENTION Hereinafter, embodiment of this invention is described in detail, referring drawings. At this time, the same reference numerals are attached to the same or corresponding parts in the drawings and the description thereof will not be repeated.

Example 1

1 is a circuit diagram showing the configuration of a constant current circuit according to the first embodiment of the present invention.

Referring to FIG. 1, the constant current circuit 1 includes an N-type transistor N1, a capacitor C1, switches S1 to S3, and a resistor R101. The N-type transistor N1 is a driving transistor for flowing a constant current, and is connected between the node 2 and the node 8 to which the constant voltage VL is applied, and the gate is connected to the node 4. The N-type transistor N1 may be an N-type TFT or an N-type bulk transistor. The capacitor C1 is provided to maintain the gate voltage of the N-type transistor N1, and is connected between the node 4 and the node 8.

The switches S1 to S3 are switched at the time of voltage setting for setting the gate voltage of the N-type transistor N1 and at the time of current driving. The switch S1 is connected between the resistor R101 and the node 2, and the switch S2 is connected between the node 10 and the node 2 to which a load requiring a constant current is connected, and the switch S3 is connected between the node 2 and the node 4. Connected. The resistor element R101 is provided for supplying a predetermined current to the node 2 at the time of voltage setting, and is connected between the node 6 to which the predetermined voltage VH higher than the voltage VL is applied and the switch S1.

As described above, the constant current circuit 1 has two operation modes, a voltage setting operation of setting the gate voltage of the N-type transistor N1 and a current driving operation of the original function. FIG. 1 shows an operating state at the time of voltage setting, and FIG. 2 described later shows an operating state at the time of current driving. Hereinafter, the voltage setting operation in the constant current circuit 1 will be described.

When the voltage is set, the switches S1 and S3 are turned on and the switch S2 is turned off. Then, a current flows from node 6 to node 8 through resistor R1O1, switch S1 and diode-connected N-type transistor N1, and the voltage level of node 4 is higher than threshold voltage Vth1 of N-type transistor N1 (Vth1 +). ΔV1). The capacitor C1 is charged with electric charges corresponding to the voltage level of the node 4.

Although not shown, when charging of the capacitor C1 is completed, the switches S1 and S3 are turned off, and the voltage level of the node 4 is maintained at (Vth1 + ΔV1) by the capacitor C1.

2 is a view showing an operating state at the time of driving the current of the constant current circuit 1.

Referring to Fig. 2, when the charge according to the voltage level (Vth1 + [Delta] V1) is charged to the capacitor C1, and the switches S1 and S3 are OFF, the switch S2 is turned ON. If so, current flows from node 10 to node 8 via switch S2 and n-type transistor N1.

Here, the voltage of the node 4, that is, the gate voltage of the N-type transistor N1 is maintained at a constant voltage level (Vth1 + ΔV1) higher than the threshold voltage Vth1 by the capacitor C1, so that the N-type transistor N1 can flow a constant current. have.

At this time, the current value through which the N-type transistor N1 flows depends on ΔV 1, and this Δ V 1 can be adjusted by the resistance value of the resistance element R 101.

1 and 2, the capacitor C1 is connected to the node 8, but may be connected to another node as long as it is a node to which a constant voltage is applied.

At this time, the constant current circuit 1 according to the first embodiment can be applied to a general-purpose OP amplifier as long as it is a usage method that can secure a time for switching the switches S1 to S3. Application examples of the OP amplifier are various, but for example, when the OP amplifier is used in the sample hold circuit, it is possible to secure the time for switching the switches S1 to S3 before sampling the signal. Therefore, the constant current circuit 1 can be applied.

As described above, according to the constant current circuit 1 according to the first embodiment, the gate voltage when the N-type transistor N1 as the driving transistor is flowing a constant current is maintained, and the N-type transistor N1 is based on the held voltage. Therefore, the constant current can be stably flown even when the threshold voltage of the N-type transistor N1 is large.

Example 2

3 is a circuit diagram showing the configuration of a constant current circuit according to a second embodiment of the present invention.

Referring to FIG. 3, the constant current circuit 1A includes a P-type transistor P1, a capacitor C2, switches S4 to S6, and a resistor R102. The P-type transistor P1 is connected between a node 16 and a node 12 to which a constant voltage VH is applied in a drive transistor for allowing a constant current to flow, and a gate is connected to the node 14. The P-type transistor P1 may be a P-type TFT or a P-type bulk transistor. The capacitor C2 is provided to maintain the gate voltage of the P-type transistor P1 and is connected between the node 16 and the node 14.

The switches S4 to S6 are switched at the voltage setting for setting the gate voltage of the P-type transistor P1 and at the time of driving the current. The switch S4 is connected between the node 12 and the resistance element R101, and the switch S5 is connected between the node 20 and the node 12 to which a load requiring a constant current is connected, and the switch S6 is connected to the node 12 and the node 14. It is connected between and. The resistance element R102 is provided for flowing a predetermined current to the node 12 at the time of voltage setting, and is connected between the switch S4 and the node 18 to which the predetermined voltage VL lower than the voltage VH is applied.

This constant current circuit 1A has a configuration in which the polarity of the constant current circuit 1 according to the first embodiment is reversed. Fig. 3 shows an operating state at the time of voltage setting, and Fig. 4 described later shows an operating state at the time of driving a document. Hereinafter, the voltage setting operation in the constant current circuit 1A will be described.

At the time of voltage setting, switches S4 and S6 are turned on, and switch S5 is turned off. Then, a current flows from the node 16 to the node 18 through the diode-connected P-type transistor P1, the switch S4 and the resistance element R102, and the voltage level of the node 14 is based on the threshold voltage Vth2 of the P-type transistor P1 (VH−). | Vth2 |-DELTA V2). In the capacitor C2, a charge corresponding to the voltage level of the node 14 is charged.

Although not shown, when the charging of the capacitor C2 is completed, the switches S4 and S6 are turned off, and the voltage level of the node 14 is maintained at (VH- | Vth2 | -ΔV2) by the capacitor C2.

Fig. 4 is a diagram showing an operating state at the time of current driving of the constant current circuit 1A.

Referring to Fig. 4, when the charge according to the voltage level (VH- | Vth2 | -ΔV2) is charged to the capacitor C2, and the switches S4 and S6 are OFF, the switch S5 is turned on. If so, current flows from node 16 to node 20 through p-type transistor P1 and switch S5.

Here, the voltage of the node 14, that is, the gate voltage of the P-type transistor P1 is maintained at a constant voltage level (VH- | Vth2 | -ΔV2) by the capacitor C2, so that the P-type transistor P1 can flow a constant current. .

At this time, the current value through which the P-type transistor P1 flows depends on? V2, and this? V2 can be adjusted by the resistance value of the resistance element R102.

3 and 4, the capacitor C2 is connected to the node 16, but may be connected to another node as long as it is a node to which a constant voltage is applied.

At this time, the constant current circuit 1A according to the second embodiment can also be applied to a general-purpose OP amplifier as long as it is a usage method that can secure the time for switching the switches S4 to S6 like the constant current circuit 1 according to the first embodiment.

As described above, the same effect as the constant current circuit 1 according to the first embodiment can be obtained also by the constant current circuit 1A according to the second embodiment.

Example 3

In Embodiment 3, the case where the constant current circuit 1 according to Embodiment 1 is applied to a differential amplifier is shown.

Fig. 5 is a circuit diagram showing the configuration of the differential amplifier according to the third embodiment.

5, the differential amplifier according to the third embodiment includes the constant current circuit 1 and the differential circuit 30 according to the first embodiment. The N-type transistor N1 of the constant current circuit 1 is composed of an N-type TFT. Since the structure of the constant current circuit 1 has already been described, the description is not repeated.

The differential circuit 30 includes N-type TFT elements N2 and N3, and resistance elements R103 and R104. The N-type TFT element N2 is connected between the resistor R103 and the node 10 and receives an input signal IN1 at the gate. The N-type TFT element N3 is connected between the resistor R104 and the node 10 and receives an input signal IN2 at the gate. The resistance element R103 is connected between the node 6 and the N-type TFT element N2, and the resistance element R104 is connected between the node 6 and the N-type TFT element N3.

In the differential amplifier according to the third embodiment, a transistor constituting a circuit is composed of TFTs and is formed on a glass substrate or a resin substrate.

In FIG. 5, the operation state at the time of setting the voltage to the constant current circuit 1 is shown. At the time of voltage setting, the switch S2 is turned off, and the differential circuit 30 is electrically disconnected from the constant current circuit 1 and inactivated. At this time, since the operation in setting the voltage of the constant current circuit 1 has already been described in Embodiment 1, the description thereof will not be repeated.

Fig. 6 is a diagram showing an operating state when the differential amplifier according to the third embodiment is active.

With reference to Fig. 6, during activation, the switches S1 and S3 are turned OFF, and the switch S2 is turned ON, so that the differential circuit 30 is activated. Here, the differential amplifier is composed of TFTs, but operates stably since the constant current circuit 1 is used as the constant current source. That is, when the conventional current mirror type differential amplifier is composed of TFTs, the constant current circuit does not operate due to the variation of the threshold voltage between the TFTs, and the differential amplifier malfunctions. Such malfunctions do not occur.

At this time, in the differential amplifier according to the third embodiment, the electric charge held by the capacitor C1 is lost due to the gate leakage current of the N-type TFT element N1, the leakage current of the capacitor C1 itself, or the leakage current of the switch S3. At intervals, the refresh operation, that is, the above-described voltage setting operation, is executed.

As described above, according to the differential amplifier according to the third embodiment, since the constant current circuit for activating the differential amplifier is constituted by the constant current circuit 1 according to the first embodiment, the operation is stable even when the differential amplifier is constituted by the TFT.

[Modification of Example 3]

FIG. 7 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 5.

Referring to Fig. 7, this differential amplifier has a constant current circuit 1B instead of the constant current circuit 1 in the configuration of the differential amplifier shown in Fig. 5. The constant current circuit 1B includes the N-type TFT element N4 in place of the resistor element R101 in the configuration of the constant current circuit 1. The other structure is the same as that of the differential amplifier shown in FIG.

The N-type TFT element N4 constitutes a depletion transistor in which a source is connected to a gate. In general, the current Id flowing through the depletion transistor is represented by the following expression (2) because the gate voltage Vgs for the source is 0V.

Id = β (-Vth) ² ... (2)

Here, Vth represents the threshold voltage and β represents the conductance. That is, the current Id flowing through the N-type TFT element N4 becomes a constant current that does not depend on the voltages VH and VL.

Therefore, in the voltage setting operation that needs to be performed at predetermined intervals as described above, even if the voltages VH and VL vary, the node 4 is set to a constant voltage level every time by the N-type TFT element N4 capable of supplying a constant current. The constant current value flowing to the node 10 by the constant current circuit 1B does not change for each voltage setting operation. As a result, the operation of the differential amplifier is more stable.

As described above, according to this differential amplifier, since the depletion type N-type TFT element N4 capable of supplying a constant current is used as the current supply circuit at the time of voltage setting in the constant current circuit, the constant current circuit (1B) for each voltage setting operation is used. The set voltage becomes constant, and the operation of the differential amplifier is more stable.

Example 4

In Embodiment 4, the case where the constant current circuit 1A according to Embodiment 2 is applied to the differential amplifier is shown.

Fig. 8 is a circuit diagram showing the configuration of the differential amplifier according to the fourth embodiment.

Referring to Fig. 8, the differential amplifier according to the fourth embodiment includes a constant current circuit 1A and a differential circuit 30A according to the second embodiment. The P-type transistor P1 of the constant current circuit 1A is composed of a P-type TFT. Since the structure of the constant current circuit 1A has already been described, the description thereof will not be repeated.

The differential circuit 30A includes P-type TFT elements P2 and P3 and resistance elements R105 and R106. The P-type TFT element P2 is connected between the node 20 and the resistance element R105 and receives the input signal IN3 at the gate. The P-type TFT element P3 is connected between the node 20 and the resistance element R106 and receives an input signal IN4 at the gate. The resistive element R105 is connected between the P-type TFT element P2 and the node 18, and the resistive element R106 is connected between the P-type TFT element P3 and the node 18.

In the differential amplifier according to the fourth embodiment, a transistor constituting a circuit is formed of a TFT and is formed on a glass substrate or a resin substrate.

In FIG. 8, the operation state at the time of setting the voltage to the constant current circuit 1A is shown. At the time of voltage setting, the switch S5 is turned off, and the differential circuit 30A is electrically disconnected from the constant current circuit 1A and deactivated. At this time, since the operation in setting the voltage of the constant current circuit 1A has already been described in Embodiment 2, the description thereof will not be repeated.

9 is a diagram showing an operating state when the differential amplifier according to the fourth embodiment is active.

Referring to Fig. 9, during activation, switches S4 and S6 are turned OFF, and switch S5 is turned ON, and differential circuit 30A is activated. Here, the differential amplifier is also composed of a TFT, but operates stably since the constant current circuit 1A is a constant current source.

At this time, even in the differential amplifier according to the fourth embodiment, the electric charge held by the capacitor C2 is lost due to the gate leakage current of the P-type TFT element P1, the leakage current of the capacitor C2 itself, or the leakage current of the switch S6. At intervals, a refresh operation, that is, a voltage setting operation, is executed.

In the above description, the differential amplifier is composed of TFTs, but may be constituted by bulk transistors.

As described above, according to the differential amplifier according to the fourth embodiment, since the constant current circuit for activating the differential amplifier is constituted by the constant current circuit 1A according to the second embodiment, the operation is stable even when the differential amplifier is constituted by TFTs.

[Modification of Example 4]

FIG. 10 is a circuit diagram showing a modification of the differential amplifier shown in FIG. 8.

Referring to FIG. 10, this differential amplifier includes a constant current circuit 1C instead of the constant current circuit 1A in the configuration of the differential amplifier shown in FIG. The constant current circuit 1C includes the N-type TFT element N5 instead of the resistor element R102 in the configuration of the constant current circuit 1A. The other structure is the same as that of the differential amplifier shown in FIG.

The N-type TFT element N5 constitutes a depletion transistor in which a source is connected to a gate. Therefore, as described in the modification of the third embodiment, the current Id flowing through the N-type TFT element N5 becomes a constant current that does not depend on the voltages VH and VL.

Then, in the voltage setting operation that needs to be performed at predetermined intervals, even if the voltages VH and VL fluctuate, the node 14 is set to a constant voltage level every time by the N-type TFT element N5 capable of supplying a constant current, and the constant current circuit By 1C, the constant current flowing through the node 20 does not vary for each voltage setting operation. As a result, the operation of the differential amplifier is more stable.

As described above, also with this differential amplifier, the same effects as in the modification of the third embodiment can be obtained.

Example 5

In Embodiment 5, the case where the constant current circuits according to Embodiments 1 and 2 is applied to the liquid crystal display device is shown.

Fig. 11 is a schematic block diagram showing the overall configuration of a color liquid crystal display device according to a fifth embodiment of the present invention.

Referring to FIG. 11, the color liquid crystal display device 100 includes a display unit 102, a horizontal scanning furnace 104, and a vertical scanning furnace 106.

The display unit 102 includes a plurality of pixels 118 arranged in a matrix. In each pixel 118, any one of three primary colors of R (red), G (green), and B (blue) is set, and pixels (R), pixels (G), and One display unit 120 is configured as the pixel B. In addition, a plurality of scanning lines SL are disposed corresponding to the rows of the pixels 118 (hereinafter also referred to as "lines"), and a plurality of data lines DL are disposed corresponding to the columns of the pixels 118.

The horizontal scanning path 104 includes a shift register 108, first and second data latch circuits 110 and 112, a voltage generating circuit 114, and a data line driver 116.

The shift register 108 receives the clock signal CLK and sequentially outputs a pulse signal to the data latch circuit 110 in synchronization with the clock signal CLK.

The first data latch circuit 110 receives 6-bit pixel data DATA for selecting one voltage from a 64-level driving voltage output from the voltage generation circuit 114 described later, and receives a pulse signal from the shift register 108. In synchronization, the pixel data DATA is latched inside.

The second data latch circuit 112 receives the pixel data DATA for one line and the latch signal LT generated when introduced into the first data latch circuit 110, and the pixel data DATA for one line latched in the first data latch circuit 110. Is introduced from the first data latch circuit 110 and latched.

The voltage generating circuit 114 generates 64 levels of driving voltages V1 to V64 in order to display 64 gray levels in each pixel 118.

The data line driver 116 receives the pixel data for one line from the second data latch circuit 112 and the driving voltages V1 to V64 output from the voltage generating circuit 114, selects the driving voltage for each pixel in accordance with the pixel data, and selects the column voltage in the column direction. The data lines DL are outputted in unison.

106 vertically activates the scanning lines SL arranged in the row direction at predetermined timings.

In the liquid crystal display device 100, the pixel data DATA is sequentially introduced into the first data latch circuit 110 in accordance with the pulse signal output from the shift register 108 in synchronization with the clock signal CLK. In response to the latch signal LT received at the timing at which the pixel data DATA of one line is introduced, the second data latch circuit 112 receives the first data of the pixel data DATA of one line introduced into the first data latch circuit 110. The latch circuit 110 is introduced and latched to output pixel data DATA for one line to the data line driver 116.

The data line driver 116 selects a driving voltage for each pixel from the 64-level driving voltages V1 to V64 received from the voltage generating circuit 114 based on the pixel data for one line received from the second data latch circuit 112, and 1 The driving voltages corresponding to the pixels of the line are all output to the corresponding data lines DL. When the vertical scanning channel 106 activates the scanning line SL corresponding to the scanning target row, the pixels 118 connected to the scanning line SL are simultaneously activated, and each pixel 118 is connected to the corresponding data line DL. The display is performed at the luminance corresponding to the applied driving voltage, thereby displaying pixel data for one line.

The image is displayed on the display unit 102 by sequentially performing the above operation for each scan line arranged in the row direction.

FIG. 12 is a circuit diagram showing the configuration of the pixel 118 shown in FIG. In FIG. 12, the pixel 118 connected to the data line DL (R) and the scan line SL (n) is shown, but the configuration is the same for the other pixels.

Referring to FIG. 12, the pixel 118 includes an N-type TFT element N11, a liquid crystal display element PX, and a capacitor C11.

The N-type TFT element N11 is connected between the data line DL (R) and the liquid crystal display element PX, and a gate is connected to the scanning line SL (n). The liquid crystal display element PX has a pixel electrode connected to the N-type TFT element N11, and a counter electrode to which the counter electrode potential Vcom is applied. One side of the capacitor C11 is connected to the pixel electrode, and the other side is fixed to the common potential Vss.

In the liquid crystal display element PX, the orientation (liquidity) of the liquid crystal display element PX is changed by changing the orientation of the liquid crystal in accordance with the potential difference between the pixel electrode and the counter electrode. As a result, the luminance (reflectance) according to the driving voltage applied from the data line DL (R) through the N-type TFT element N11 can be displayed on the liquid crystal display element PX.

Then, after the scanning line SL (n) is activated and a driving voltage is applied from the data line DL (R) to the liquid crystal display element PX, the scanning line SL (n) is shifted to the image display of the next scanning line SL (n + 1). Is deactivated and the N-type TFT element N11 is turned off, but the capacitor C11 maintains the potential of the pixel electrode even in the OFF period of the N-type TFT element N11, so that the liquid crystal display element PX can change the luminance (reflectance) according to the pixel data. I can keep it.

FIG. 13 is a circuit diagram showing the configuration of the voltage generating circuit 114 shown in FIG.

Referring to Fig. 13, the voltage generating circuit 114 is provided in correspondence with the nodes ND100 and ND200, the resistance elements R1 to R65, the nodes ND1 to ND64, and the nodes ND1 to ND64, and 64 buffers having a constant current circuit therein. Circuit 130.

The resistance elements R1 to R65 are connected in series between the nodes ND100 and the node ND200 by the nodes ND1 to ND64, and constitute a leather resistance circuit. Then, the voltage between the nodes ND100 and ND200 is divided by this leather resistor circuit, and 64-level driving voltages V1 to V64 are generated at the nodes ND1 to ND64. Each buffer circuit 130 has a current driving force sufficient to drive the data line DL and the pixel, is connected to the corresponding node of the nodes ND1 to ND64, and outputs a voltage having the same level as the input voltage.

At this time, since the liquid crystal display element PX needs to be driven in alternating current, the voltages applied to the nodes ND100 and ND200 are replaced at predetermined cycles, such as one frame per line.

FIG. 14 is a circuit diagram showing the configuration of the buffer circuit 130 shown in FIG.

Referring to FIG. 14, the buffer circuit 130 includes first and second amplifier circuits 132 and 134 having a constant current circuit therein, a resistance element R136, and a node 138. The first amplifier circuit 132 is connected between the node NDi and the output node 140, and the second amplifier circuit 134 is connected between the node 138 and the output node 140. The resistance element R136 is connected between the node NDi and the node 138.

The first and second amplifier circuits 132 and 134 constitute a push-pull amplifier. That is, the first amplifying circuit 132 charges the output node 140 with a small current driving force, and discharges electric charges from the output node 140 with sufficient current driving force when the voltage level of the output node 140 exceeds the voltage level of the node NDi. do. The second amplifier circuit 134 charges the output node 140 with sufficient current driving force when the voltage level of the output node 140 is lower than the voltage level of the node 138.

When the first and second amplifying circuits 132 and 134 operate simultaneously, a large current flows from the second amplifying circuit 134 to the first amplifying circuit 132, and thus the first and second amplifying circuits 132 and 134. Since the first and second amplifier circuits 132 and 134 do not operate at the same time by supplying a potential difference to the input potential of the resistor, a resistor R136 is provided. At this time, on one side, the resistance value of the resistance element R136 is sufficiently small that the first and second amplifying circuits 132 and 134 are not operated simultaneously so that the driving voltage output to the output node 140 does not greatly vary. Is set.

FIG. 15 is a circuit diagram showing the configuration of the first amplifier circuit 132 shown in FIG.

Referring to Fig. 15, the first amplifier circuit 132 includes the P-type TFT elements P101 and P102, the N-type TFT elements N101 to N103, the constant current circuits 150a and 150b, the power node Vdd, and the like. And a ground node Vss, nodes 210 to 215, and an output node 216. The output node 216 is connected to the output node 140 shown in FIG.

The P-type TFT elements P101 and P102 and the N-type TFT elements N101 and N102 constitute a differential circuit. The N-type TFT element N103 is connected between the output node 216 and the ground node Vss, and a gate is connected to the node 212. When the voltage level of the output node 216 is higher than the voltage level of the node NDi, the voltage level of the node 212 increases, so that the current flowing through the N-type TFT element N103 increases, and the amount of discharge of charge from the output node 216 to the ground node Vss increases. do. Therefore, the voltage level of the output node 216 decreases.

The constant current circuit 150a includes a P-type TFT element P132a, a capacitor C132a, switches S104a to S106a, a resistor element R132a, and nodes 202 and 204. The P-type TFT element P132a is a transistor through which a constant current flows, and is connected between the power supply node Vdd and the node 202, and a gate is connected to the node 204. The capacitor C132a is a voltage holding capacitor that holds the gate voltage of the P-type TFT element P132a and is connected between the power supply node Vdd and the node 204.

The switches S104a to S106a are switched at the time of voltage setting and current driving to set the gate voltage of the P-type TFT element P132a, and the switch S104a is connected between the node 202 and the resistor R132a, and the switch S105a is connected to a differential circuit. It is connected between the connected node 210 and the node 202, and the switch S106a is connected between the node 202 and the node 204. The resistance element R132a is provided to allow a predetermined current to flow in the node 202 at the time of voltage setting, and is connected between the switch S104a and the ground node Vss.

This constant current circuit 150a has the same configuration as that of the constant current circuit 1A described in the second embodiment. Therefore, even if the transistor which flows a constant current is comprised by P-type TFT element P132a, since a constant current can flow to a differential circuit without being influenced by the fluctuation of the threshold voltage, a differential circuit does not malfunction.

The constant current circuit 150b includes a P-type TFT element P132b, a capacitor C132b, switches S104b to S106b, a resistor element R132b, and nodes 206 and 208. Since the configuration of the constant current circuit 150b is the same as that of the constant current circuit 150a, the description thereof will not be repeated.

The constant current circuit 150b is provided to increase the voltage level of the output node 216 to the voltage level of the node NDi. That is, when the voltage level of the output node 216 becomes higher than the voltage level of the node NDi, the N-type TFT element N103 is activated, and the voltage level of the output node 216 is lowered. When the voltage level of the output node 216 is lower than the voltage level of the node 138 shown in FIG. 14, the P-type TFT element included in the second amplifier circuit 134 described later in FIG. 16 is activated, and the voltage of the output node 216 is activated. Level rises.

However, as described above, the input voltage of the second amplifier circuit 134 is lower than the voltage level of the node NDi by the resistance element R136 so that the first and second amplifier circuits 132 and 134 do not operate at the same time. Therefore, the voltage level of the output node 216 only rises to the voltage level of the node 138. Thus, in order to raise the voltage level of the output node 216 to the voltage level of the node NDi, the constant current circuit 150b is provided.

If the constant current circuit provided to raise the voltage level of the output node 216 to the voltage level of the node NDi malfunctions, that is, does not operate, the voltage level of the output node 216 has an offset with respect to the voltage level of the node NDi. That is, the driving voltage applied to the pixel has an offset. Therefore, the stabilization of the operation of the constant current circuit is important. In the liquid crystal display device 100 according to the fifth embodiment, the above-described constant current circuit 150b is provided, whereby the operation of the constant current circuit is stabilized.

FIG. 16 is a circuit diagram showing the configuration of the second amplifier circuit 134 shown in FIG.

Referring to Fig. 16, the second amplifier circuit 134 includes P-type TFT elements P111 to P113, N-type TFT elements N111 and N112, a constant current circuit 152, a power supply node Vdd, and ground. The node Vss, the nodes 230 to 235, and the output node 236 are formed. The output node 236 is connected to the output node 140 shown in FIG.

The P-type TFT elements P111 and P112 and the N-type TFT elements N111 and N112 constitute a differential circuit. The P-type TFT element P113 is connected between the power supply node Vdd and the output node 236, and a gate is connected to the node 232. When the voltage level of the output node 236 is lower than that of the node 138, the voltage level of the node 232 decreases, so that the current flowing through the P-type TFT element P113 increases, and the amount of charge supplied from the power supply node Vdd to the output node 236 increases. Increases. Thus, the voltage level of the output node 236 rises.

The constant current circuit 152 includes an N-type TFT element N134, a capacitor C134, switches S101 to S103, a resistor element R134, and nodes 222 and 224. The N-type TFT element N134 is a transistor for flowing a constant current, and is connected between the node 222 and the ground node Vss, and a gate is connected to the node 224. The capacitor C134 is a voltage holding capacitor that holds the gate voltage of the N-type TFT element N134 and is connected between the node 224 and the ground node Vss.

The switches S101 to S103 are switched at the time of voltage setting and current driving for setting the gate voltage of the N-type TFT element N134, and the switch S101 is connected between the resistor element R134 and the node 222, and the switch S102 is provided with a differential circuit. It is connected between the connected node 230 and the node 222, and the switch S103 is connected between the node 222 and the node 224. The resistance element R134 is provided to allow a predetermined current to flow in the node 222 at the time of voltage setting, and is connected between the power supply node Vdd and the switch S101.

This constant current circuit 152 has the same configuration as the constant current circuit 1 described in the first embodiment. Therefore, even if the transistor which flows a constant current is comprised by the N type TFT element N134, since a constant current can flow to a differential circuit without being influenced by the fluctuation of the threshold voltage, a differential circuit does not malfunction.

At this time, in the constant current circuits 150a, 150b in the first amplifier circuit 132 and the constant current circuit 152 in the second amplifier circuit 134, resistors R132a, R132b, and R134 are used, respectively. As described in Example 3, a depletion-type N-type TFT element may be used instead of the resistor elements R132a, R132b, and R134. Thus, as described in the third embodiment, the first and second amplifier circuits ( The operation of the 132 and 134, that is, the operation of the voltage generation circuit 114 including them, is more stable.

In addition, although the above-mentioned liquid crystal display device 100 sets gradation display in each pixel to 64 levels, gradation display is not limited to 64 levels, More than that may be at least. Depending on the number of levels of gradation display, the number of bits of the pixel data DATA and the number of resistance elements and buffer circuits of the voltage generating circuit 114 are different. However, the overall configuration is not substantially different from the above configuration, and the number of levels of gradation display is different. The configuration in other cases is omitted because it overlaps with the above description.

As described above, according to the liquid crystal display device 100 according to the fifth embodiment, when the voltage generation circuit is integrally formed on the same glass substrate as the image display unit, the operation of the constant current circuit composed of the TFTs is stabilized. The malfunction of the voltage generating circuit caused by the variation of the threshold voltage of? Can be prevented.

Example 6

In Embodiment 6, the case where the constant current circuits according to Embodiments 1 and 2 is applied to the EL display device is shown.

In the EL display device, the display luminance of the organic light emitting diode is changed by changing the current applied to the organic light emitting diode, which is a current drive type light emitting element provided for each pixel, by changing the voltage applied to the pixel. The peripheral circuit including the voltage generating circuit for generating a plurality of voltage levels corresponding to the display luminances of the plurality of levels in each pixel can be configured in the same way as the liquid crystal display device.

The EL display device 100A according to the sixth embodiment has the same configuration as the liquid crystal display device 100 according to the fifth embodiment except for the pixel. Therefore, the description of the configuration other than the pixels of the EL display device 100A is not repeated.

17 is a circuit diagram showing a configuration of a pixel 118A of the EL display device 100A according to the sixth embodiment. In FIG. 17, the pixel 118A connected to the data line DL (R) and the scan line SL (n) is shown. However, the configuration is the same for the other pixels.

Referring to FIG. 17, the pixel 118A includes an N-type TFT element N21, a P-type TFT element P21, an organic light emitting diode OLED, a capacitor C21, and a node 250.

The N-type TFT element N21 is connected between the data line DL (R) and the node 250 and a gate is connected to the scanning line SL (n). The P-type TFT element P21 is connected between the power supply node Vdd and the organic light emitting diode OLED, and a gate is connected to the node 250. The organic light emitting diode OLED is connected between the P-type TFT element P21 and the common electrode Vss. The capacitor C21 is connected between the node 250 and the common electrode Vss.

In the organic light emitting diode OLED, the display luminance of the organic light emitting diode changes depending on the current supplied thereto. In Fig. 17, the cathode of the organic light emitting diode OLED is in a "cathode common configuration" to which the common electrode Vss is connected. A ground voltage or a predetermined negative voltage is applied to the common electrode Vss.

In the pixel 118A, the P-type TFT element P21 changes the amount of current supplied to the organic light emitting diode OLED in accordance with the level of the driving voltage applied from the data line DL (R) through the N-type TFT element N21. Therefore, the display luminance of the organic light emitting diode OLED changes according to the level of the driving voltage applied from the data line DL (R).

Then, the scanning line SL (n) is activated, a driving voltage is applied from the data line DL (R) to the gate of the P-type TFT element P21, and a driving current is supplied to the organic light emitting diode OLED, and then the next scanning line SL (n + 1). The scanning line SL (n) is deactivated and the N-type TFT element N21 is turned off in order to shift to the image display, but the capacitor C21 maintains the potential of the node 250 even in the OFF period of the N-type TFT element N21. The light emitting diode OLED can maintain the luminance according to the pixel data.

Also in the sixth embodiment, as described in the fifth embodiment, it is used in the constant current circuits 150a and 150b in the first amplifier circuit 132 and the constant current circuit 152 in the second amplifier circuit 134, respectively. Instead of the resistive elements R132a, R132b, and R134, a depletion type N-type TFT element or a P-type TFT element in which a gate is connected to a source may be used. As a result, the operation of the first and second amplifier circuits 132 and 134, that is, the operation of the voltage generation circuit 114 including them, is more stable.

Also, in the above description, the EL display device 100A is set to 64 levels of gradation display in each pixel. However, the gradation display is not limited to 64 levels. Is the same as the liquid crystal display device 100.

As described above, according to the EL display device 100A according to the sixth embodiment, when the voltage generation circuit is integrally molded on the same glass substrate as the image display unit, the operation of the constant current circuit composed of the TFTs is stabilized. The malfunction of the voltage generating circuit caused by the variation of the threshold voltage of? Can be prevented.

Example 7

In the seventh embodiment, in the liquid crystal display device 100 according to the fifth embodiment, the constant current circuit according to the first embodiment is also applied to an analog amplifier for outputting the display voltage corresponding to the selected gray scale voltage to the data line DL.

18 is a schematic block diagram showing an overall configuration of a color liquid crystal display device according to a seventh embodiment of the present invention.

Referring to Fig. 18, in the configuration of the color liquid crystal display device 100 according to the fifth embodiment shown in Fig. 11, the color liquid crystal display device 100B is provided with 104A in horizontal scan instead of 104 in horizontal scan. The horizontal scanning unit 104A includes a data line driver 116A instead of the data line driver 116 shown in FIG. 11, and the data line decode driver 116A includes a decode circuit 122 and an analog amplifier 124.

The decode circuit 122 receives the pixel data for one line output from the second data latch circuit 112 and the gradation voltages V1 to V64 output from the voltage generation circuit 114, and selects the gradation voltage for each pixel in accordance with the pixel data. The decode circuit 122 outputs the tone voltages for the selected one line to the analog amplifier 124 at the same time.

The analog amplifier 124 receives the gradation voltage for one line output from the decode circuit 122 at high impedance, and outputs the same display voltage as the received gradation voltage to the corresponding data line DL at low impedance.

The rest of the configuration of the color liquid crystal display device 100B is the same as that of the color liquid crystal display device 100 shown in Fig. 11, and the description thereof will not be repeated.

FIG. 19 is a circuit diagram showing the configuration of the analog amplifier 124 shown in FIG. Here, an analog amplifier which receives the gray scale voltage selected by the decoding circuit 122 and outputs a display voltage corresponding thereto is provided for each data line DL, and in Fig. 19, it corresponds to the jth (j is a natural number) data line DL. Analog amplifier 124.j is shown, and the analog amplifier corresponding to the other data lines DL also has the same circuit configuration.

Referring to FIG. 19, the analog amplifier 124.j includes an N-type TFT element N200, a constant current circuit 300, switches S200 to S206, capacitors C200 and C202, power supply voltages VH2, VL2) includes power nodes 380 and 382 and nodes 350 to 360 respectively. The node 360 is connected to the corresponding data line DL (not shown).

The N-type TFT element N200 is connected between the power supply node 380 and the node 356, and a gate is connected to the node 352. For example, a power supply voltage VH2 of 10 V is applied to the power supply node 380. A constant current circuit 300 is connected to a node 356 to which the source of the N-type TFT element N200 is connected, and the N-type TFT element N200 receives a voltage corresponding to the input voltage Vinj at a gate with high impedance, and outputs the output voltage Voutj at a low impedance node. The source follower outputs to 360.

The constant current circuit 300 includes an N-type TFT element N202, a capacitor C204, switches S208 to S212, a resistance element R200, a power node 384, and nodes 362 to 366. . The N-type TFT element N202 is a transistor for flowing a constant current, and is connected between the node 364 and the power supply node 382, and a gate is connected to the node 366. The capacitor C204 is a voltage holding capacitor that holds the gate voltage of the N-type TFT element N202 and is connected between the node 366 and the power supply node 382. For example, a power supply voltage VH2 of 10V and a power supply voltage VL2 of 0V are applied to the power supply nodes 384 and 382, respectively.

The switches S208 to S212 are switched at the voltage setting for setting the gate voltage of the N-type TFT element N202 and at the time of current driving. The switch S208 is connected between the resistor R200 and the node 362, the switch S210 is connected between the node 356 and the node 364, and the switch S212 is connected between the node 362 and the node 366. The resistance element R200 is provided for flowing a predetermined current to the N-type TFT element N202 at the time of voltage setting, and is connected between the power supply node 380 and the switch S208.

This constant current circuit 300 has the same configuration as that of the constant current circuit 1 described in the first embodiment. Therefore, even if the transistor for flowing a constant current is constituted by the N-type TFT element N202, a constant current can flow to the N-type TFT element N200 which is a driver transistor without being affected by the variation in the threshold voltage. j does not malfunction.

The switches S200 to S204 and the capacitor C200 constitute an offset compensation circuit that compensates for the offset between the input voltage Vinj and the output voltage Voutj generated by the threshold voltage Vthn in the N-type TFT element N200. The switch S200 is connected between the input node 350 and the node 352 which receive the input voltage Vinj. The switch S202 is connected between the node 354 and the node 358. The switch S204 is connected between the input node 350 and the node 354.

The operation of this offset compensation circuit will be described. In the predetermined setting mode, the switches S200, S202, and S204 are turned ON, ON, and OFF, respectively.

Then, the gate voltage of the N-type TFT element N200 becomes the input voltage Vinj, and the potentials of the nodes 3 56 and 358 become Vinj-Vthn. Therefore, the capacitor C200 is charged with the potential difference Vthn between the input potential Vinj and the potential of the node 358.

When charging ends, the setting mode ends, and the switches S200, S202, and S204 are turned OFF, OFF, and ON, respectively. If so, the potential of the node 354 becomes Vinj, and accordingly the potential of the node 352, that is, the gate potential of the N-type TFT element N200, becomes Vinj + Vthn. Therefore, the potentials of the nodes 356 and 358 become Vinj. That is, output voltage Voutj = input voltage Vinj, and the offset voltage is erased.

In this analog amplifier 124.j, by using the constant current circuit 300, the above-described offset compensation circuit operates stably and with high accuracy. That is, since the constant current circuit 300 can stably and flow a constant current without malfunction, the capacitor C200 in the offset compensation circuit has a stable and highly accurate charge corresponding to the threshold voltage Vthn for generating the offset. Is charged. Therefore, the gate voltage of the N-type TFT element N200 in the operation mode is stabilized and high precision, and as a result, the high precision output voltage Voutj without offset is output.

At this time, the capacitor C202 indicates the capacity of the node 360 to which the data line DL is connected, and the switch S206 is provided to insulate the capacitor C200 from the node 360 so that charging to the capacitor C200 is terminated early in the setting mode. At this time, when the capacitance of the capacitor C202 is small, it is not necessary to particularly provide the switch S206.

As described above, according to the seventh embodiment, since the analog amplifier 124 includes the constant current circuit 300, the malfunction of the analog amplifier 124 due to the variation in the threshold voltage of the TFT can be prevented. In addition, since the analog amplifier 124 includes an offset compensation circuit that operates simultaneously with the constant current circuit 300, there is no offset with respect to the gradation voltage received from the decode circuit 122, and it is possible to output a high-precision display voltage.

Therefore, even if the peripheral circuit including the analog amplifier 124 is integrally molded on the same glass substrate as the image display unit, the color liquid crystal display device 100B operates stably and with high accuracy.

Example 8

The color liquid crystal display device according to the eighth embodiment includes the analog amplifier 124A in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

20 is a circuit diagram showing the configuration of the analog amplifier 124A in the eighth embodiment. Here, also in the eighth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 20, the analog amplifier 124A.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to Fig. 20, analog amplifier 124A.j is composed of constant current circuit 300A instead of constant current circuit 300 in the configuration of analog amplifier 124.j in the seventh embodiment shown in Fig.19. The constant current circuit 300A includes N-type TFT elements N202 to N210, a capacitor C204, switches S208 to S212, resistance elements R202 to R206, a power node 384, and nodes 362 to 372). The power supply potential VH2 is applied to the power supply node 384.

The N-type TFT element N204 is connected between the power supply node 384 and the switch S208, and a gate is connected to the node 372. The N-type TFT elements N206, N208, and N210 are connected in series between the resistance element R202 and the power supply node 382. Each of the N-type TFT elements N206, N208, and N210 constitutes an enhancement type transistor in which a gate is connected to a drain.

The resistors R204 and R206 are connected in series between the node 368 and the node 370, and divide the voltage between the drain and the source of the N-type TFT element N206 based on the resistance ratios of the resistors R204 and R206. The gate of the N-type TFT element N204 is connected to a node 372 connecting the resistors R204 and R206.

At this time, since the other circuits have already been described with reference to FIG. 19, the description thereof will not be repeated.

Hereinafter, the characteristic of this constant current circuit 300A is demonstrated. At this time, below, the threshold voltage Vthn assumes that there is no variation between the N-type TFT elements N202 to N21O, and the variation of the threshold voltage below represents a variation with respect to the design value.

When the threshold voltages of the N-type TFT elements N202 to N210 constituting the constant current circuit 300A are set to Vthn, the resistances of the resistor elements R204 and R206 are set to R1 and R2, respectively, and the power supply voltage VL2 is set to ground level (0V). The potential of ie, the gate potential of the N-type TFT element N204 is as follows.

Vg = 2 × Vthn + Vthn × R1 / (R1 + R2)... (3)

Here, the resistance values R1 and R2 are set to a sufficiently large value compared to the ON resistance of the N-type TFT element N206. As shown in equation (3), the gate voltage of the N-type TFT element N204 depends on the threshold voltage Vthn. Therefore, in the N-type TFT element N204, even if the threshold voltage Vthn fluctuates, the gate voltage Vg also fluctuates with the fluctuation, so that the stable operating margin of the N-type TFT element N204 due to the fluctuation of the threshold voltage Vthn is improved.

In addition, as shown in equation (3), the gate voltage Vg can be adjusted by adjusting the resistance values R1 and R2. Therefore, the amount of current flowing through the N-type TFT element N204, that is, the amount of current flowing through the constant current circuit 300A can be adjusted by the values of the resistance values R1 and R2 of the resistance elements R204 and R206.

As described above, according to the eighth embodiment, the operation of the constant current circuit and the analog amplifier including the same is further stabilized, whereby the operation stability of the liquid crystal display device is further improved.

In addition, since the amount of current flowing through the constant current circuit 300A can be adjusted by appropriately adjusting the resistance values R1 and R2 of the resistance elements R204 and R206, the amount of current in the constant current circuit can be optimized and the power consumption can be reduced.

Example 9

Analogue amplifiers 124 and 124A in Embodiments 7 and 8 were full-type analogues in the ninth embodiment, whereas the analog amplifiers 124 and 124A were the push type in which the N-type TFT element N200 as the driver transistor was connected between the power supply node 380 and the output node. The amplifier appears.

The color liquid crystal display device according to the ninth embodiment includes the analog amplifier 124B in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

21 is a circuit diagram showing the configuration of the analog amplifier 124B according to the ninth embodiment. Here, also in the ninth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 21, the analog amplifier 124B.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to FIG. 21, the analog amplifier 124B.j includes a P-type TFT element P200, a constant current circuit 302, switches S220 to S226, capacitors C220 and C222, power nodes 380 and 382, and nodes 400 to 410. . The node 410 is connected to the corresponding data line DL (not shown).

The P-type TFT element P200 is connected between the node 406 and the power supply node 382, and a gate is connected to the node 402. For example, a power supply voltage VL2 of a ground potential (0 V) is applied to the power supply node 382. A constant current circuit 302 is connected to a node 406 to which the source of the P-type TFT element P200 is connected, and the P-type TFT element P200 receives a voltage corresponding to the input voltage Vinj at a gate with high impedance, and outputs an output voltage Voutj at a low impedance node. A source follower operation output to 410 is performed.

The constant current circuit 302 includes a P-type TFT element P202, a capacitor C224, switches S228 to S232, a resistor element R220, a power supply node 386, and nodes 412 to 416. The P-type TFT element P202 is a transistor for flowing a constant current, and is connected between the power supply node 380 and the node 414, and a gate is connected to the node 416. The capacitor C224 is a voltage holding capacitor that holds the gate voltage of the P-type TFT element P202 and is connected between the power supply node 380 and the node 416.

The switches S228 to S232 are switched at the time of voltage setting and current driving for setting the gate voltage of the P-type TFT element P202. The switch S228 is connected between the node 412 and the resistance element R220, the switch S230 is connected between the node 414 and the node 406, and the switch S232 is connected between the node 416 and the node 412. The resistance element R220 is provided to allow a predetermined current to flow in the P-type TFT element P202 at the time of voltage setting, and is connected between the switch S228 and the power supply node 386.

This constant current circuit 302 has the same configuration as the constant current circuit 1A described in the second embodiment. Therefore, even if the transistor which flows a constant current is comprised by the P-type TFT element P202, since a constant current can flow to the P-type TFT element P200 which is a driver transistor, without being influenced by the fluctuation of the threshold voltage, this analog amplifier 124B. j does not malfunction.

The switches S220 to S224 and the capacitor C220 constitute an offset compensation circuit for compensating the offset between the input voltage Vinj and the output voltage Voutj generated by the threshold voltage Vthp in the P-type TFT element P200. It is connected between the receiving input node 400 and the node 402. The switch S222 is connected between the node 408 and the node 404. The switch S224 is connected between the input node 400 and the node 404.

The operation of this offset compensation circuit will be described. In the predetermined setting mode, the switches S220, S222, and S224 are turned ON, ON, and OFF, respectively. If so, the gate voltage of the P-type TFT element P200 becomes the input voltage Vinj, and the potentials of the nodes 406 and 408 become Vinj + | is charged to vthp |

When charging ends, the setting mode ends, and the switches S220, S222, and S224 are turned OFF, OFF, and ON, respectively. If so, the potential of the node 404 becomes Vinj, and accordingly the potential of the node 402, that is, the gate potential of the P-type TFT element P200, becomes Vinj- | Vthp |. Therefore, the potentials of the nodes 406 and 408 become Vinj. That is, output voltage Voutj = input voltage Vinj, and the offset voltage is canceled.

In this analog amplifier 124B.j, the constant current circuit 302 is used, whereby the above-described offset compensation circuit operates stably and with high accuracy. That is, since the constant current circuit 302 is stable and can flow a stable current without malfunction, the capacitor C220 in the offset compensation circuit is charged with a stable and high precision charge corresponding to the threshold voltage Vthp for generating the offset. . Therefore, the gate voltage of the P-type TFT element P200 in the operation mode is stabilized and high precision, and as a result, the high precision output voltage Voutj without offset is output.

At this time, the capacitor C222 represents the capacity of the node 410 to which the data line DL is connected, and the switch S226 is provided to insulate the capacitor C220 from the node 410 so that charging to the capacitor C220 is terminated at the early stage in the setting mode. . At this time, when the capacitance of the capacitor C222 is small, the switch S226 may not be particularly provided.

As described above, the same effect as in the seventh embodiment can be obtained also by the liquid crystal display device according to the ninth embodiment including the full analog amplifier 124B.

Example 10

The color liquid crystal display device according to the tenth embodiment includes the analog amplifier 124C in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

Fig. 22 is a circuit diagram showing the configuration of the analog amplifier 124C in the tenth embodiment. Here, also in the tenth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 22, the analog amplifier 124C.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to Fig. 22, analog amplifier 124C.j is composed of constant current circuit 302A instead of constant current circuit 302 in the configuration of analog amplifier 124B.j in the ninth embodiment shown in Fig.21. The constant current circuit 302A includes the P-type TFT elements P202 to P21O, the capacitor C224, the switches S228 to S232, the resistance elements R222 to R226, the power supply node 386, and the nodes 412 to 412. 422). The power supply potential VL2 is applied to the power supply node 386.

The P-type TFT element P204 is connected between the switch S228 and the power supply node 386, and a gate is connected to the node 422. The P-type TFT elements P206, P208, and P210 are connected in series between the power supply node 380 and the resistor element R222. Each of the P-type TFT elements P206, P208, and P210 constitutes an enhancement type transistor in which a gate is connected to a drain.

The resistors R224 and R226 are connected in series between the node 418 and the node 420, and divide the voltage between the source and the drain of the P-type TFT element P206 based on the resistance ratios of the resistors R224 and R226. The gate of the P-type TFT element P204 is connected to the node 422 connecting the resistors R224 and R226.

At this time, since the other circuits have already been described with reference to FIG. 21, the description thereof will not be repeated.

Hereinafter, the characteristic of this constant current circuit 302A is demonstrated. Under the present circumstances, the threshold voltage Vthp does not have the fluctuation between P-type TFT elements P202-P21O, and the variation of the threshold voltage below has shown the fluctuation | variation with respect to a design value.

When the threshold voltages of the P-type TFT elements P202 to P210 constituting the constant current circuit 302A are set to Vthp and the resistance values of the resistor elements R224 and R226 are respectively R3 and R4, the potential of the node 422, that is, the gate potential of the P-type TFT element P204, is , As follows:

Vg = VH2-2 x Vthp-Vthp x R3 / (R3 + R4). (4)

Here, the resistance values R3 and R4 are set to a sufficiently large value as compared with the ON resistance of the P-type TFT element P206. As shown in equation (4), the gate voltage of the P-type TFT element P204 depends on the threshold voltage Vthp. Therefore, in the P-type TFT element P204, even if the threshold voltage Vthp fluctuates, the gate voltage Vg also fluctuates with the fluctuation, so that the stable operation margin of the P-type TFT element P204 due to the fluctuation of the threshold voltage Vthp improves.

Further, as shown in equation (4), the gate voltage Vg can be adjusted by adjusting the resistance values R3 and R4. Therefore, the amount of current flowing through the P-type TFT element P204, that is, the amount of current flowing through the constant current circuit 302A can be adjusted by the values of the resistance values R3 and R4 of the resistance elements R224 and R226.

As described above, the same effect as in the eighth embodiment can be obtained also by the liquid crystal display device according to the tenth embodiment including the full-type analog amplifier 124C.

Example 11

The color liquid crystal display device according to the eleventh embodiment includes the analog amplifier 124D in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

Fig. 23 is a circuit diagram showing the configuration of the analog amplifier 124D in the eleventh embodiment. Here, also in the eleventh embodiment, the analog amplifier is provided for each data line DL, and in Fig. 23, the analog amplifier 124D.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to Fig. 23, the analog amplifier 124D.j is a level shift provided between the gate electrode of the N-type TFT element N200 and the node 352 in the configuration of the analog amplifier 124.j according to the seventh embodiment shown in Fig.19. It further includes a circuit 500. The level shift circuit 500 includes a P-type TFT element P250, a constant current circuit 302, and power supply nodes 388 and 390 to which power supply voltages VH1 and VL1 are applied, respectively.

The P-type TFT element P250 is connected between the node 374 and the power supply node 390, and a gate is connected to the node 352. The constant current circuit 302 is a constant current circuit shown in FIG. 21 and is connected between the power supply node 388 and the node 374. The node 374 is connected to the gate of the N-type TFT element N200. The P-type TFT element P250 performs a source follower operation. At this time, the other structure is as already demonstrated in FIG.

The operation of the analog amplifier 124D.j is described below. If the gate potential of the P-type TFT element P250 is set to Vg and the threshold voltage is set to Vthp, the potential of the node 374 becomes vg + | Vthp |. Therefore, the level shift circuit 500 outputs a potential obtained by shifting the potential input to the level shift circuit 500 by | Vthp |.

In the predetermined setting mode, when the switches S200, S202, and S204 are ON, ON, and OFF, respectively, the gate voltage of the P-type TFT element P250 becomes the input voltage Vinj, and the potential of the node 374 becomes Vinj + │Vthp│. The potentials of the nodes 356 and 358 become Vinj + | Vthp | -Vthn. Therefore, the capacitor C200 is charged with the potential difference Vthn- | Vthp | between the input potential Vinj and the potential of the node 358.

When charging ends, the setting mode ends, and the switches S200, S202, and S204 are turned OFF, OFF, and ON, respectively. If so, the potential of the node 354 becomes Vinj, and accordingly the potential of the node 352, that is, the gate potential of the P-type TFT element P250 becomes Vinj + Vthn- | Vthp |. Therefore, the potential of the node 374 becomes Vinj + Vthn, and the potentials of the nodes 356 and 358 become Vinj. That is, output voltage Voutj = input voltage Vinj, and the offset voltage is erased.

At this time, the reason for providing the level shift circuit 500 is that, according to the analog amplifier 124.j in the seventh embodiment shown in Fig. 19, even if the offset compensation circuit is installed, it cannot be ignored depending on the size of the parasitic capacitance of the node 352. There is a possibility that an offset error may occur. If the magnitude of the threshold voltage of the P-type TFT element P250 included in the level shift circuit 500 can be designed at a level close to the threshold voltage of the N-type TFT element N200, This is because the generated offset voltage itself can be made small.

As described above, also in the eleventh embodiment, the same effect as in the seventh embodiment can be obtained.

Example 12

The color liquid crystal display device according to the twelfth embodiment includes the analog amplifier 124E instead of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

24 is a circuit diagram showing the configuration of the analog amplifier 124E in the twelfth embodiment. Here, also in the twelfth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 24, the analog amplifier 124E.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to FIG. 24, the analog amplifier 124E.j includes the constant current circuit 300A shown in FIG. 20 instead of the constant current circuit 300 in the configuration of the analog amplifier 124D.j shown in FIG. And a level shift circuit 500A. The level shift circuit 500A consists of the constant current circuit 302A shown in FIG. 22 instead of the constant current circuit 302 in the structure of the level shift circuit 500. As shown in FIG.

At this time, the other configuration of analog amplifier 124E.j is the same as that of analog amplifier 124D.j in the eleventh embodiment.

According to the twelfth embodiment, similarly to the eleventh embodiment, the same effects as those of the seventh embodiment can be obtained, and the operation of the analog amplifier is further stabilized by the constant current circuits 300A and 302A, further improving the operational stability of the liquid crystal display device. do.

Example 13

The color liquid crystal display device according to the thirteenth embodiment includes the analog amplifier 124F in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

25 is a circuit diagram showing the configuration of the analog amplifier 124F according to the thirteenth embodiment. Here, also in the thirteenth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 25, the analog amplifier 124F.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to Fig. 25, the analog amplifier 124F.j is a level shift provided between the gate electrode of the P-type TFT element P200 and the node 402 in the configuration of the analog amplifier 124B.j according to the ninth embodiment shown in Fig.21. It further includes a circuit 502. The level shift circuit 502 consists of an N-type TFT element N250, a constant current circuit 300, and power supply nodes 388 and 390 to which the power supply voltages VH1 and VL1 are applied, respectively.

The N-type TFT element N250 is connected between the power supply node 388 and the node 424, and a gate is connected to the node 402. The constant current circuit 300 is a constant current circuit shown in FIG. 19 and is connected between the node 424 and the power supply node 390. The node 424 is connected to the gate of the P-type TFT element P200. The N-type TFT element N250 performs a source follower operation. At this time, the other structure is as already demonstrated in FIG.

The operation of the analog amplifier 124F.j is described below. If the gate potential of the N-type TFT element N250 is Vg and the threshold voltage is Vthn, the potential of the node 424 is Vg-Vthn. Therefore, the level shift circuit 502 outputs a potential obtained by shifting the potential input to the level shift circuit 502 by -Vthn.

In the predetermined setting mode, when the switches S220, S222, and S224 are ON, ON, and OFF, respectively, the gate voltage of the N-type TFT element N250 becomes the input voltage Vinj, and the potential of the node 424 becomes Vinj-Vthn. The potentials of the nodes 406 and 408 become Vinj-Vthn + | Vthp |. Therefore, the capacitor C220 is charged with the potential difference Vthn- | Vthp | between the input voltage Vinj and the potential of the node 408.

When charging ends, the setting mode ends, and the switches S200, S202, and S204 are turned OFF, OFF, and ON, respectively. If so, the potential of the node 404 becomes Vinj, and accordingly, the potential of the node 402, that is, the gate potential of the N-type TFT element N250 becomes Vinj + Vthn- | Vthp |. Therefore, the potential of the node 424 becomes Vinj- | Vthp |, and the potentials of the nodes 406 and 408 become Vinj. That is, output voltage Voutj = input voltage Vinj, and the offset voltage is erased.

At this time, the reason for providing the level shift circuit 502 is the same as the reason for providing the level shift circuit 500 in the eleventh embodiment, and the description is repeated.

As mentioned above, also with Example 13, the same effect as Example 9 can be acquired.

Example 14

The color liquid crystal display device according to the fourteenth embodiment includes the analog amplifier 124G in place of the analog amplifier 124 in the configuration of the color liquid crystal display device 100B according to the seventh embodiment.

Fig. 26 is a circuit diagram showing the configuration of the analog amplifier 124G in the fourteenth embodiment. Here, also in the fourteenth embodiment, the analog amplifier is provided for each data line DL, and in Fig. 26, the analog amplifier 124G.j corresponding to the j-th data line DL is shown, and the analog amplifier corresponding to the other data line DL is shown. Is made of the same circuit configuration.

Referring to FIG. 26, in the configuration of the analog amplifier 124F.j shown in FIG. 25, the analog amplifier 124G.j includes the constant current circuit 302A shown in FIG. 22 instead of the constant current circuit 302, and instead of the level shift circuit 502. And a level shift circuit 502A. The level shift circuit 502A consists of the constant current circuit 300A shown in FIG. 20 instead of the constant current circuit 300 in the structure of the level shift circuit 502. As shown in FIG.

At this time, the other configuration of analog amplifier 124G.j is the same as that of analog amplifier 124F.j in the thirteenth embodiment.

According to the fourteenth embodiment, similarly to the thirteenth embodiment, the same effects as in the ninth embodiment can be obtained, and the constant current circuits 302A and 300A further stabilize the operation of the analog amplifier and further improve the operation stability of the liquid crystal display device. do.

At this time, in the above-described Embodiments 7 to 14, the case where the constant current circuits according to Embodiments 1 and 2 is applied to the analog amplifier in the liquid crystal display device has been described, but in the same manner as in Embodiment 6 corresponding to Embodiment 5, The analog amplifier described in Examples 7 to 14 can also be applied to the EL display device described in the sixth embodiment.

The presently disclosed embodiments are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is not described in the above embodiments, but is indicated by the scope of the claims, and is intended to include the scope and equivalents of the claims and all modifications within the scope.

The constant current circuit according to the present invention includes a voltage holding circuit that maintains a voltage set according to a threshold voltage of a driving transistor through which current flows, and the driving transistor receives a voltage held by the voltage holding circuit at a gate to receive a current. Since it is made to flow, even if there is a manufacturing variation in the threshold voltage of a drive transistor, the influence is excluded and the operation | movement of a constant current circuit is stable.

As the operation of the constant current circuit stabilizes, the operation of the drive circuit and the image display device including the constant current circuit is also stabilized.

Claims (19)

Transistors N1 and P1 connected between the first node 10, 20 and the second node 8, 16; Voltage holding circuits (C1, 4; C2, 14) which are determined according to threshold voltages of the transistors (N1, P1) and which hold a first voltage for turning on the transistors (N1, P1); The transistors N1 and P1 receive the first voltage at a gate and make the current at the first nodes 10 and 20 constant, A constant current circuit, characterized in that the first node (10, 20) is connected with a differential circuit (30, 30A). A plurality of image display elements 118 and 118A arranged in a matrix; A plurality of scan lines SL disposed corresponding to the rows of the plurality of image display elements 118 and 118A and sequentially selected at predetermined cycles, A plurality of data lines DL disposed corresponding to the columns of the plurality of image display elements 118 and 118A, A voltage generating circuit 114 for generating at least one voltage level corresponding to the display luminance in each of the plurality of image display elements 118 and 118A; At least one buffer circuit 130 which maintains the at least one voltage level generated by the voltage generation circuit 114 and amplifies and outputs the current; The voltage level indicated by the pixel data corresponding to each of the image display elements 118 and 118A of the scanning target row is selected from the at least one voltage level for each of the image display elements 118 and 118A of the scanning target row, and the selected A data line driver 116 for activating the plurality of data lines DL at a voltage level, Each of the at least one buffer circuit 130, An internal circuit which inputs any one of said at least one voltage level, amplifies and outputs the current; It consists of a constant current circuit (150a, 150b, 152) for flowing a constant current to the internal circuit, The constant current circuit (150a, 150b, 152), Transistors P132a, P132b, and N134 connected between the internal circuit and the first node; Voltage holding circuits C132a, 204; C132b, and 208, which are determined according to threshold voltages of the transistors P132a, P132b, and N134, and which hold a first voltage for turning on the transistors P132a, P132b, and N134; C134, 224), And said transistors (P132a, P132b, N134) receive said first voltage at a gate and make a current in said internal circuit constant. The method of claim 2, In the voltage holding circuits C132a, 204; C132b, 208; C134, and 224, drains of the transistors P132a, P132b, and N134 are connected to gates, and current is flowing through the transistors P132a, P132b, and N134. And a gate voltage at the same time as the first voltage. The method of claim 3, wherein The constant current circuits 150a, 150b, and 152 further include: Current supply circuits R132a, R132b, and R134 for supplying a current for setting the first voltage; When the first voltage is set, the internal circuits are insulated from the transistors P132a, P132b, and N134, and the voltage holding circuits C132a, 204; C132b, 208; C134, 224, and the transistors P132a, P132b, And an switching circuit (S104a to S106a; S104b to S106b; S101 to S103) for connecting N134 to the current supply circuits (R132a, R132b, and R134). The method of claim 4, wherein The voltage holding circuits C132a, 204; C132b, 208; C134, and 224 have one end connected to a gate of the transistors P132a, P132b, and N134, and the other end connected to the first node. C132a, C132b, C134), The switch circuits S104a to S106a; S104b to S106b; S101 to S103 include first to third switches, Upon setting the first voltage, The first switches S105a, S105b, and S102 insulate the internal circuit from the transistors P132a, P132b, and N134, The second switches S104a, S104b, and S101 connect the current supply circuits R132a, R132b, and R134 to drains of the transistors P132a, P132b, and N134, And said third switch (S106a, S106b, S103) connects the drain of said transistor (P132a, P132b, N134) to said one end of said capacitor (C132a, C132b, C134). The method of claim 2, The transistors included in each of the plurality of image display elements 118 and 118A, the voltage generation circuit 114, the at least one buffer circuit 130, and the data line driver 116 are thin film transistors. An image display device. The method of claim 6, The plurality of image display elements 118 and 118A, the voltage generating circuit 114, the at least one buffer circuit 130 and the data line driver 116 may be formed on any one of a glass substrate and a resin substrate. An image display device, characterized in that formed integrally. The method of claim 2, Each of the plurality of image display elements (118) includes a liquid crystal display element (PX). The method of claim 2, Each of the plurality of image display elements (118A) includes an electroluminescent element (OLED). In a driving circuit for outputting an output voltage according to the input voltage, First transistors N200 and P200 connected between the first power source nodes 380 and 382 and the output nodes 356 and 406; Constant current circuits 300 and 302 connected between the output nodes 356 and 406 and the second power node 382 and 380; An offset compensation circuit for compensating an offset voltage generated according to threshold voltages of the first transistors N200 and P200, The offset compensation circuit maintains the offset voltage and outputs a first voltage obtained by shifting the input voltage by the maintained offset voltage to the gate electrodes of the first transistors N200 and P200. The constant current circuit 300, 302, Second transistors N202 and P202 connected between the output nodes 356 and 406 and the second power node 382 and 380; First voltage holding circuits C204 and C224 that are determined according to threshold voltages of the second transistors N202 and P202 and also hold a second voltage for turning on the second transistors N202 and P202. and, The second transistors N202 and P202 receive the second voltage at the gate electrode and make the currents in the first transistors N200 and P200 connected to the output nodes 356 and 406 constant, The first transistors N200 and P200 receive the first voltage output from the offset compensation circuit to a gate electrode, and output the input voltage and the output voltage of the coin to the output nodes 360 and 410. A drive circuit, characterized in that. The method of claim 10, The offset compensation circuit, Second voltage holding circuits C200 and C220 charged in the setting mode and holding the offset voltage in the operation mode; In the setting mode, first nodes 352 and 402 connected to one end of the second voltage holding circuits C200 and C220 and the gate electrodes of the first transistors N200 and P200, and the second voltage holding circuit. The other ends of the C200 and C220 are connected to the input nodes 350 and 400 and the output nodes 358 and 408, respectively, and in the operation mode, the first node 352 and 402 and the second voltage holding circuit. First switch circuits S200 to which the other end of C200 and C220 are insulated from the input nodes 350 and 400 and the output nodes 358 and 408, respectively, to connect the other end to the input nodes 350 and 400. A driving circuit comprising S204, S220 to S224. The method of claim 10, The constant current circuit 300A, 302A, A current supply circuit for supplying a current for setting the second voltage; When the second voltage is set, the second transistors N202 and P202 are insulated from the output nodes 356 and 406, and the first voltage holding circuits C204 and C224 and the second transistors N202 and P202 are separated from each other. ) Further comprises second switch circuits (S208 to S212, S228 to S232) for connecting the current supply circuit, The current supply circuit, A voltage generator for generating a gate voltage determined according to a threshold voltage of a transistor constituting the current supply circuit; A third transistor connected between a third power supply node 384 and 386 and the second switch circuits S208 to S212 and S228 to S232, and receiving the gate voltage generated by the voltage generator at a gate electrode; A driving circuit comprising (N204, P204). The method of claim 12, The voltage generator, A plurality of enhancement type transistors N206 to N21O and P206 to P210 connected in series between the third power node 384 and 386 and the second power node 382 and 380; A voltage divider circuit connected in parallel with enhancement type transistors N206 and P206 connected to the third power source nodes 384 and 386 and having first and second resistors R204, R206; R224, and R226 connected in series. Done, The gate electrode of the third transistors N204 and P204 is connected to the nodes 372 and 422 connecting the first resistors R204 and R224 to the second resistors R206 and R226. in. In a driving circuit for outputting an output voltage according to the input voltage, First transistors N200 and P200 of a first conductivity type connected between the first power source nodes 380 and 382 and the output nodes 356 and 406, First constant current circuits 300 and 302 connected between the output nodes 356 and 406 and second power nodes 382 and 380; Level shift circuits 500 and 502 for receiving a first voltage and outputting a second voltage obtained by shifting the received first voltage by a predetermined amount; An offset compensation circuit for compensating an offset voltage generated according to threshold voltages of the first conductivity type first transistors N200 and P200, The level shift circuits 500 and 502 Second constant current circuits 302 and 300 connected between the third power supply nodes 388 and 390 and the gate electrodes of the first conductivity type first transistors N200 and P200; And first second transistors P250 and N250 of a second conductivity type connected between the gate electrodes of the first transistors N200 and P200 of the first conductivity type and the fourth power nodes 390 and 388. The offset compensation circuit maintains a voltage difference between the threshold voltages of the first transistors N200 and P200 of the first conductivity type and the threshold voltages of the first transistors P250 and N250 of the second conductivity type. A voltage obtained by shifting the input voltage by the voltage difference maintained is output as the first voltage to the gate electrodes of the first transistors P250 and N250 of the second conductivity type. The first constant current circuit (300, 302), Second transistors N202 and P202 of a first conductivity type connected between the output nodes 356 and 406 and the second power node 382 and 380; A first voltage determined according to the threshold voltages of the second transistors N202 and P202 of the first conductivity type, and maintaining a third voltage for turning on the second transistors N202 and P202 of the first conductivity type; Including voltage holding circuits C204 and C224, The second transistors N202 and P202 of the first conductivity type receive the third voltage to the gate electrode and are connected to the output nodes 356 and 406. Constant current at P200), The second constant current circuit (302, 300), Second transistors P202 and N202 of a second conductivity type connected between the third power node 388 and 390 and the gate electrode of the first transistors N200 and P200 of the first conductivity type, A second voltage determined according to threshold voltages of the second transistors P202 and N202 of the second conductivity type, and holding a fourth voltage for turning on the second transistors P202 and N202 of the second conductivity type; Voltage holding circuits (C224, C204), The second transistors P202 and N202 of the second conductivity type receive the fourth voltage to the gate electrode and are connected to the gate electrodes of the first transistors N200 and P200 of the first conductivity type. The current in the first transistors P250 and N250 of the conductive type is made constant, The first transistors P250 and N250 of the second conductivity type receive the first voltage output from the offset compensation circuit to a gate electrode, and threshold values of the first transistors P250 and N250 of the second conductivity type. Outputting the second voltage obtained by shifting the first voltage by a voltage to the gate electrodes of the first transistors N200 and P200 of the first conductivity type, The first transistors N200 and P200 of the first conductivity type receive the second voltage output from the level shift circuits 500 and 502 at a gate electrode, and receive the input voltage and the output voltage of the coin. Drive circuit, characterized in that output to the output node (360, 410). The method of claim 14, The offset compensation circuit, Third voltage holding circuits C200 and C220 charged in the setting mode and maintaining the voltage difference in the operation mode; In the setting mode, first nodes 352 and 402 to which one end of the third voltage holding circuits C200 and C220 and the gate electrodes of the first transistors P250 and N250 of the second conductivity type are connected. The other ends of the third voltage holding circuits C200 and C220 are connected to the input nodes 350 and 400 and the output nodes 358 and 408, respectively, and in the operation mode, the first node 352 and 402 and the second node. A first switch circuit which insulates the other ends of the third voltage holding circuits C200 and C220 from the input nodes 350 and 400 and the output nodes 358 and 408, respectively, and connects the other ends with the input nodes 350 and 400, respectively. A driving circuit comprising (S200 to S204, S220 to S224). The method of claim 14, The first constant current circuit (300A, 302A), A first current supply circuit for supplying a current for setting the third voltage; When the third voltage is set, the second transistors N202 and P202 of the first conductivity type are insulated from the output nodes 356 and 406, and the first voltage holding circuits C204 and C224 and the first voltage are formed. And further comprising second switch circuits S208 to S212 and S228 to S232 connecting the second transistors N202 and P202 of the conductive type to the first current supply circuit. The first current supply circuit, A first voltage generator for generating a gate voltage determined according to a threshold voltage of the first conductivity type transistor constituting the first current supply circuit; A fifth power node 384 or 386 connected to the second switch circuits S208 to S212 and S228 to S232 to receive the gate voltage generated by the first voltage generator to a gate electrode; It is made of a first conductive third transistor (N204, P204), The second constant current circuit 302A, 300A, A second current supply circuit for supplying a current for setting the fourth voltage; In setting the fourth voltage, the second transistors P202 and N202 of the second conductivity type are insulated from the gate electrodes of the first transistors N200 and P200 of the first conductivity type, and the second voltage maintaining circuit is performed. (C224, C204) and third switch circuits (S228 to S232, S208 to S212) for connecting the second transistors (202 and N202) of the second conductivity type to the second current supply circuit, The second current supply circuit, A second voltage generator for generating a gate voltage determined according to a threshold voltage of a second conductivity type transistor constituting the second current supply circuit; A sixth power node 386 or 384 connected to the third switch circuits S228 to S232 and S208 to S212, and receiving the gate voltage generated by the second voltage generator at a gate electrode; A driving circuit comprising a second conductive third transistor (P204, N204). A plurality of image display elements 118 and 118A arranged in a matrix; A plurality of scan lines SL disposed corresponding to the rows of the plurality of image display elements 118 and 118A and sequentially selected at predetermined cycles, A plurality of data lines DL disposed corresponding to the columns of the plurality of image display elements 118 and 118A, A voltage generating circuit 114 for generating at least one voltage corresponding to the display luminance in each of the plurality of image display elements 118 and 118A; A decode circuit 122 for selecting a voltage indicated by the pixel data corresponding to each of the image display elements 118 and 118A of the scanning target row from the image display elements 118 and 118A of the scanning target row and the at least one voltage. Wow, The driving circuits 124, 124A to Claims 10 or 14 which receive the voltage selected by the decoding circuit 122 from the decoding circuit 122 and activate the plurality of data lines DL to the corresponding voltages. 124G). The method of claim 17, The transistors included in each of the plurality of image display elements 118 and 118A, the voltage generation circuit 114, the decode circuit 122, and the driving circuits 124, 124A to 124G are thin film transistors. An image display device. The method of claim 17, The plurality of image display elements 118 and 118A, the voltage generating circuit 114, the decode circuit 122, and the driving circuits 124, 124A to 124G may be formed on any one of a glass substrate and a resin substrate. An image display apparatus, characterized in that formed integrally.