KR20040057471A - Method for manufacturing a transistor in a semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a transistor of a semiconductor device is provided to prevent the ions for a shallow junction region of a source/drain electrode from diffusing into an unwanted portion by sequentially forming a deep junction region and the shallow junction region. CONSTITUTION: A gate oxide layer(12) and a gate poly(14) are sequentially deposited on a substrate(10). An anti-reflective coating(16a) is formed on the gate poly. A spacer(18a) is formed at both sidewalls of the anti-reflective coating. A deep junction region(20a) is formed at both sides of the anti-reflective coating in the substrate by carrying out the first ion-implantation using the spacer as a mask. The spacer is removed. A gate electrode is formed by selectively etching the gate poly and the gate oxide layer using the anti-reflective coating as an etching mask. A shallow junction region is formed between the gate electrode and the deep junction region by carrying out the second ion-implantation using the gate electrode as a mask.

Description

Method for manufacturing a transistor in a semiconductor device

The present invention relates to a transistor manufacturing method of a semiconductor device, and more particularly to a method for manufacturing a source / drain (electrode) in the transistor of the semiconductor device.

In general, among semiconductor devices, a DRAM device includes one access transistor and one storage capacitor.

The transistor needs to be improved in speed in order to respond to a memory device requiring increased density. Therefore, transistors in recent semiconductor devices have metal silicides as electrode materials to reduce the resistance at the gate electrode and improve the operation speed. In addition, the operation speed of the transistor is improved by improving the source / drain electrodes.

The source / drain electrodes are formed through various methods. Examples of the method of forming the source / drain electrodes are disclosed in Korean Patent Publication No. 2001-113838, Korean Patent Publication No. 2000-39716, and Korean Patent Publication No. 2001-78557.

A general method of manufacturing the source / drain electrodes is as follows. First, a gate electrode is formed on a substrate. Then, ion implantation using the gate electrode as a mask is performed to form a source / drain electrode with a shallow junction. Subsequently, after forming a spacer on the sidewall of the gate electrode, ion implantation using the spacer as a mask is performed to form a source / drain electrode of a deep junction. Thus, the formation of the source / drain electrodes having the shallow junction and the deep junction is completed.

However, when the source / drain electrodes are formed through the above method, the source / drain electrodes are formed to have a broad profile. This is because after forming the shallow junction source / drain electrodes, spacers are formed. That is, due to the thermal characteristics applied to the substrate when forming the spacer, the ions forming the source / drain electrode of the shallow junction cause a diffusion reaction.

Therefore, when the source / drain electrodes are formed by the conventional method, formation of the source / drain electrodes having an ideal profile is not easy. Therefore, there is a disadvantage that is not suitable for the manufacture of recent semiconductor devices.

It is an object of the present invention to provide a method for significantly reducing the diffusion of impurities introduced into a substrate by a shallow junction into a source / drain electrode due to thermal properties.

1A to 1I are cross-sectional views illustrating a method of manufacturing a transistor in a semiconductor device according to an embodiment of the present invention.

The present invention for achieving the above object, the step of sequentially stacking a gate oxide film and a gate poly on a substrate, forming an anti-reflection film pattern on the gate poly, and forming a spacer on the sidewall of the anti-reflection film pattern Forming a first ion implantation region on the substrate by performing a first ion implantation using the spacer as a mask, removing the spacer, and etching using the anti-reflection film pattern as a mask Forming a gate electrode having a gate oxide pattern and a gate poly pattern by sequentially removing the gate poly and the gate oxide layer; And a second ion implantation using the gate electrode as a mask to form a second ion implantation region in contact with the gate electrode and the first ion implantation region, thereby forming a source comprising the first ion implantation region and the second ion implantation region. / Forming a drain electrode.

As described above, according to the present invention, the spacer formed on the sidewall of the gate electrode can be omitted. Therefore, the thermal characteristics applied to the substrate when forming the spacers on the sidewalls of the gate electrodes can prevent diffusion of ions forming the shallow junction source / drain electrodes. Therefore, the performance of the semiconductor device can be improved, and in particular, short channel characteristics can be improved.

Hereinafter, a transistor manufacturing method of a semiconductor device according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

1A to 1I illustrate a method of manufacturing a transistor of a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 1A, the gate oxide layer 12 and the gate poly 14 are sequentially stacked on the substrate 10. The substrate is divided into an active region and an inactive region. It is preferable that a trench structure (not shown) is formed as the device isolation layer for the separation. This is because the area occupied by the trench structure is smaller than that of the field oxide film.

An anti-reflection film 16 is formed on the gate poly 14. In this case, an example of the anti-reflection film 16 may be a silicon oxynitride layer (SiON layer).

Referring to FIG. 1B, the antireflection film 16 is patterned to form an antireflection film pattern 16a. The patterning is accomplished by conventional photolithography processes. Thus, the patterning is accomplished by an etching process using a photoresist pattern as an etching mask.

Referring to FIG. 1C, an insulating film 18 is formed on the substrate 10 having the anti-reflection film pattern 16a. In other words, the antireflection film pattern 16a and the gate poly oxide film 14 are continuously formed. As an example of the said insulating film 18, an oxide film, a nitride film, etc. are mentioned.

Referring to FIG. 1D, spacers 18a are formed on sidewalls of the anti-reflection film pattern 16a. That is, the spacer 18a is formed by removing the insulating film 18 through the entire surface etching and leaving the insulating film 18 only on the sidewall of the anti-reflection film pattern 16a. In this case, the front surface etching is achieved by dry etching.

Referring to FIG. 1E, ion implantation using the spacer 18a as a mask is performed. At this time, the target of the ion implantation is the lower portion of the surface of the substrate 10. Therefore, the energy in the ion implantation is preferably adjusted to the extent that ions are implanted into the lower portion of the surface of the substrate 10. As such, the ion is implanted into the outer portion of the spacer 18a based on the ion implantation. Accordingly, the first preliminary source / drain electrodes 20a are formed on the substrate 10 by the ion implantation. In addition, examples of the implanted ions include ions of P + type.

Referring to FIG. 1F, the spacer 18a is removed. Removal of the spacer 18a is accomplished by wet etching. For example, when the spacer 18a is made of an oxide film, it is achieved by wet etching using a LAL solution, and when the spacer 18a is made of nitride film, it is achieved by wet etching using a phosphoric acid solution.

Referring to FIG. 1G, the gate poly 14 and the gate oxide layer 12 are removed by etching using the anti-reflection film pattern 16a as an etching mask. In other words, the gate poly 14 and the gate oxide layer 12 are patterned. Accordingly, each of the gate poly 14 and the gate oxide layer 12 is formed of the gate poly pattern 14a and the gate oxide layer pattern 12a.

Referring to FIG. 1H, the anti-reflection film pattern 16a used as the etching mask is removed. Removal of the anti-reflection film pattern 16a is achieved by wet etching. As such, by removing the anti-reflection film pattern 16a, the gate electrode 30 including the gate oxide film pattern 12a and the gate poly pattern 14a is formed on the substrate 10.

Referring to FIG. 1I, ion implantation using the gate electrode 30 as a mask is performed. As such, the ion is implanted into the lower portion of the substrate 10 adjacent to the gate electrode 30, that is, connected to the gate electrode 30. Accordingly, a second preliminary source / drain electrode 20b is formed on the substrate 10 by the ion implantation. Examples of the implanted ions include P-type ions.

Therefore, by forming the second preliminary source / drain electrode 20b, a source / drain electrode including the first preliminary source / drain electrode 20a and the second preliminary source / drain electrode 20b on the substrate 10 ( 40) is formed. Here, the source / drain electrode 40 has an LED structure, wherein each of the first preliminary source / drain electrode 20a and the second preliminary source / drain electrode 20b has a shallow source / drain electrode and a shallow junction. Corresponds to the source drain electrode of the junction.

Thus, the transistor of the semiconductor device can be obtained by forming the source / drain electrodes 40.

In this method, a source / drain electrode with a shallow junction is formed after forming a source / drain electrode with a deep junction. Therefore, a situation in which the ions implanted into the substrate do not occur to form the source / drain electrodes of the shallow junction. Therefore, the profile of the source / drain electrodes can be ideally formed.

In addition, since the ion implantation for forming the first preliminary source / drain electrode is performed at high energy, the concentration of the gate poly oxide film may be further increased. Therefore, performance improvement of the transistor can be obtained incidentally.

As described above, according to the present invention, since the ideal profile of the source / drain electrodes can be realized, and the gate poly pattern of the gate electrode has a high concentration, the performance improvement of the transistor can be expected.

Therefore, the present invention can be expected to improve the reliability of the manufacturing of the semiconductor device.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Claims (4)

Sequentially depositing a gate oxide film and a gate poly on the substrate; Forming an anti-reflection film pattern on the gate poly; Forming a spacer on sidewalls of the anti-reflection film pattern; Performing first ion implantation using the spacer as a mask to form a first ion implantation region in the substrate; Removing the spacers; Forming a gate electrode having a gate oxide pattern and a gate poly pattern by sequentially removing the gate poly and the gate oxide layer by performing etching using the anti-reflection layer pattern as a mask; And A second ion implantation region using the gate electrode as a mask to form a second ion implantation region in contact with the gate electrode and the first ion implantation region, thereby forming a source / drain region formed of the first ion implantation region and the second ion implantation region; A method for manufacturing a transistor in a semiconductor device, comprising the step of forming a drain electrode. The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein said anti-reflection film is a silicon oxynitride layer. The method of manufacturing a transistor of a semiconductor device according to claim 1, wherein said spacer is a silicon nitride film. The method of claim 1, wherein the spacer is removed by wet etching using a phosphoric acid solution.