KR20050049582A - Method for manufacturing recess channel transistor - Google Patents

Abstract

The present invention discloses a method of fabricating a transistor having a recess channel that can reduce or minimize the gate loading capacitor. The method includes forming a trench in an active region of a semiconductor substrate, forming an impurity ion implantation region in a sidewall of the trench, and selectively in the trench sidewall in which the impurity ion implantation region is formed rather than a bottom of the trench. Forming a thicker gate insulating film, and forming a gate stack on the semiconductor substrate on which the gate insulating film is formed.

Description

Method for manufacturing a transistor having a recess channel TECHNICAL FIELD

The present invention relates to a method for manufacturing a transistor used in a semiconductor memory device, and more particularly, to a method for manufacturing a transistor having a recess channel.

In recent years, as the integration of semiconductor devices has increased, the size of MOS devices has gradually decreased. In addition, the channel length has been reduced to deep sub-microns to improve the device's operating speed and current drive capability.

As the length of the channel gradually decreases, the depletion region of the source and drain penetrates into the channel, thereby reducing the effective channel length and decreasing the threshold voltage, thereby shortening the gate control function of the MOS transistor. short channel effect).

In order to overcome this short channel effect, an attempt was made to solve the problem by ion implanting an opposite conductivity type dopant into the lower portion of the channel region together with a shallow junction. (hot carrier) occurs. Since the hot carriers cause collision ionization and the hot carriers penetrate into the oxide film, the oxide film may deteriorate and may cause device defects.

In order to reduce such hot carriers, most transistor manufacturing processes adopt a lightly doped drain (LDD) structure, which forms a low concentration buffer region between a gate region and a high concentration drain region.

However, the transistor length of the above-described LDD structure is also limited in reducing the short channel phenomenon and the hot carrier phenomenon because the channel length becomes shorter due to the continuous integration requirements of semiconductor devices. In addition, there is a problem in that a punchthrough effect in which impurities of the source and the drain are diffused laterally during the transistor operation.

In order to solve this problem and reduce the size of the high density packing memory cell formed inside the semiconductor substrate, a transistor having a recess or groove channel having a longer gate channel length than a planar type per unit area is developed. The need for this is emerging.

The transistor having the recess channel increases the effective channel length by forming a trench in the region where the channel is to be formed, thereby improving the punch through of the source and the drain and substantially increasing the distance between the source and the drain. It can help in high integration of the device.

Hereinafter, a manufacturing method of a transistor having a recess channel according to the related art will be described with reference to the accompanying drawings.

1A to 1J are cross-sectional views illustrating a method of manufacturing a transistor having a recess channel of the prior art. The process cross-sectional views shown in FIGS. 1A to 1J each show a cut portion along a bit line and a cut portion along a word line, and an enlarged cross section cut along the line II ′ on the left is shown on the right portion.

As shown in FIG. 1A, the pad oxide film 14 and the hard mask film 16 are sequentially formed on a P-type (called first impurity) semiconductor substrate 12 in which an active region is defined in the device isolation film 10. The photoresist is deposited on the hard mask film 16 and the photoresist pattern 18 is formed using a photo process.

As shown in FIG. 1B, a portion of the hard mask layer 16 is etched using the photoresist pattern 18 as an etching mask to expose the pad oxide layer 14. In addition, the photoresist pattern 18 is removed.

As illustrated in FIG. 1C, the pad oxide layer 14 is removed to expose the semiconductor substrate 12 using the hard mask layer 16 as an etching mask.

As shown in FIG. 1D, a trench 20 is formed by etching the surface of the semiconductor substrate 12 to a predetermined depth by using the mask film 16 and the pad oxide film 14 as an etch mask layer. .

As shown in FIG. 1E, the source and drain regions are separated by removing the semiconductor substrate 12 inside the trench 20.

As shown in FIG. 1F, the hard mask layer 16 and the pad oxide layer 14 formed on the semiconductor substrate 12 may be removed by wet etching to remove the semiconductor substrate 12 and the device isolation layer 10. Expose the front. In this case, the wet etching method may be performed using an etchant capable of selectively etching the hard mask layer 16 or the pad oxide layer 14.

As shown in FIG. 1G, the gate insulating layer 26 is formed on the entire surface of the semiconductor substrate 12 including the trench 20. In this case, the gate insulating film is formed on the entire surface of the device isolation layer 10 and the semiconductor substrate 12 with the same thickness.

As shown in FIG. 1H, the gate electrode 28, the metal layer 30, and the gate upper insulating layer 32 are sequentially stacked on the semiconductor substrate 12 on which the gate insulating layer 26 is formed.

As shown in FIG. 1I, the gate stack 34 is sequentially formed by sequentially removing the source and drain regions and the gate upper insulating layer 32, the metal layer 30, and the gate electrode 28 on the device isolation layer 10. do.

As shown in FIG. 1J, spacers 36 are formed on sidewalls of the gate stack 34, and N-type (hereinafter referred to as second impurities) is formed in the source and drain regions around the gate stack 34. Ion implantation forms the second impurity region 38. In this case, the second impurity region 38 is formed by doping impurities of a conductivity type opposite to that of the first impurity.

Through this series of processes, a transistor having a recess channel according to the related art is completed, the gate insulating layer 26 on the source and drain regions is removed, and bit line contact and bit line contact and drain regions are formed on the source and drain regions. Storage node contacts may be formed.

However, the method of manufacturing a transistor having a recess channel according to the prior art has the following problems.

In a method of manufacturing a transistor having a recess channel according to the related art, when a gate voltage is applied to the gate electrode 28, the gate insulating layer 26 formed in the trench 20 has the same thickness, and the trench 20 is formed. Since the gate electrode 28 is formed to cover the second impurity region 38 at the upper corner, charge is concentrated in the second impurity region 38 adjacent to the gate electrode 28 so that the gate loading capacitance ( Gate loading capacitance was increased.

It is an object of the present invention to provide a method of manufacturing a transistor having a recess channel capable of reducing or minimizing the gate loading capacitance generated between the gate electrode and the second impurity region.

In accordance with an aspect of the present invention for achieving some of the above technical problems, a transistor having a recess channel includes forming a trench in an active region of a semiconductor substrate, and forming an impurity region in a sidewall of the trench. Forming a gate insulating film thicker on the sidewalls of the trench in which the impurity regions are formed than at the bottom of the trench; and forming a gate stack on the semiconductor substrate on which the gate insulating film is formed. It is done.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. The present invention is not limited to the embodiments disclosed below, but can be implemented in various different forms, only this embodiment to make the disclosure of the present invention complete, the scope of the invention to those skilled in the art It is provided to inform you. In the accompanying drawings, the thicknesses of the various films and regions have been emphasized for clarity, and may be present in direct contact with other layers or semiconductor substrates or between them when a layer is described as being on another layer or semiconductor substrate. There may be three layers.

2A to 2K are cross-sectional views illustrating a method of manufacturing a transistor having a recess channel of the present invention. In this case, the process cross-sectional views shown in FIGS. 2A to 2K represent portions cut along the bit lines, respectively, and portions cut along the word lines perpendicular to the bit lines. The part is enlarged and shown.

As shown in FIG. 2A, the pad oxide layer 54 and the hard mask layer 56 are sequentially stacked on the semiconductor substrate 52 doped with the first impurity in which the active region is defined by the device isolation layer 50. A photoresist is applied on the hard mask layer 56, and a photoresist pattern 58 is formed by using a photo process. Here, the pad oxide film 54 is formed to have a constant thickness (for example, about 200 kPa to about 500 kPa) by MTO (Medium Temperature Oxide) method, and the hard mask film 56 is chemical vapor deposition (Chemical Vapor Deposition): It is formed using a silicon oxynitride film (SiON) by a CVD method to have a predetermined thickness (for example, about 300 Pa to 1000 Pa).

As shown in FIG. 2B, a portion of the hard mask layer 56 is etched using the photoresist pattern 58 as an etching mask to expose the pad oxide layer 54. In this case, the hard mask layer 56 is etched using dry etching, and the etching of the hard mask layer 56 defines an open threshold of the trench (60 in FIG. 2D) in a subsequent process. In addition, the photoresist pattern 58 is removed.

As shown in FIG. 2C, the pad oxide layer 54 is removed to expose the semiconductor substrate 52 by the dry etching method using the hard mask layer 56 as an etching mask.

As illustrated in FIG. 2D, the surface of the semiconductor substrate 52 is etched to a predetermined depth by the dry etching method using the hard mask layer 56 and the pad oxide layer 54 as an etching mask layer, and the trenches 60 are removed. ). Here, the trench 60 is formed to have a constant open critical dimension because the depth profile may vary according to the open critical dimension. For example, the trench 60 is formed to have an open threshold of about 500 mW to 1000 mW and a depth of about 1000 mW to 1700 mW. In addition, the etching process of the pad oxide layer 54 and the formation of the trench 60 are performed in-situ (IN-SITU) using different reaction gases in one reaction chamber.

In this case, the hard mask layer 56 is a sacrificial layer, and part or all of the hard mask layer 56 is removed during the formation of the trench 60, and the pad oxide layer 54 is an etch stop layer when the hard mask layer 56 is etched. Serves as.

As illustrated in FIG. 2E, the semiconductor substrate 52 on which the trench 60 is formed is etched by a wet isotropic etching method to separate source and drain regions. In this case, the wet etching method isotropically etches the surface of the semiconductor substrate 52 inside the trench 60 using a predetermined etchant (for example, SC1), and thus not only the sidewall of the trench 60 but also the trench. The depth of 60 may be further increased.

As illustrated in FIG. 2F, fluorine (F) is ion-implanted into the sidewall of the trench 60 in which the source and drain regions are separated to form a third impurity region 62. In this case, the ion implantation of the fluorine is not vertically directed toward the semiconductor substrate 52 on which the trench 60 is formed, but constant in the semiconductor substrate 52 so as to be symmetrically formed on the inner wall of the trench 60. In the direction of the arrow at an angle (eg, about 20 degrees to about 50 degrees). As described above, since the ion implantation of the fluorine (F) is made at a predetermined angle in the semiconductor substrate 52, the hard mask film 56 formed at the corners of the upper portion of the trench 60 during the ion implantation of the fluorine (F) or The pad oxide layer 52 serves as an ion implantation mask that hides the ion implants from the bottom of the trench 60. In addition, when the hard mask layer 56 or the pad oxide layer 54 is excessively etched and thinned during the trench 60 forming process, the fluorine may extend to the bottom of the trench 60 as well as the sidewalls of the trench 60. (F) may be ion implanted. Therefore, the fluorine (F) is implanted at an angle from the semiconductor substrate 52 by using an ion implantation mask such as the hard mask film 56 or the pad oxide film 54. ) Is implanted into the sidewall of the trench 60, so that the concentration of fluorine (F) ion-implanted into the sidewall of the trench 60 is higher than the bottom of the trench 60. In this case, the ion implantation process has an energy of about 20 KeV to about 50 KeV and a concentration of about 1 × 10 ¹³ atoms / cm ² to 1 × 10 ¹⁴ atoms / cm ² . However, when fluorine (F) ion-implanted into the trench 60 sidewall is ion-implanted at a higher concentration, the shape or structure of the gate insulating film (66 in FIG. 2H) formed in the trench 60 in a subsequent process. (mopology) may be formed to be non-uniform, and the fluorine (F) may act as a channel impurity in the semiconductor substrate 52 may reduce the performance of the device.

As shown in FIG. 2G, the gate insulating film 66 is formed on the semiconductor substrate 52 on which the third impurity region 62 is formed using a silicon oxide film. For example, the gate insulating layer 66 may be formed by a thermal oxidation method, and may be formed on the semiconductor substrate 52 to have a thickness of about 30 GPa to 100 GPa. In this case, since the fluorine (F) acts as a catalyst in crystal growth when the silicon oxide film is formed on the sidewall of the trench 60 in which the third impurity region 62 is formed, the trench 60 is formed on the sidewall of the trench 60. Grow selectively thicker than at the bottom). For example, when the silicon oxide film is formed at about 30 to 100 microseconds at the bottom of the trench 60 or at the source and drain regions, the silicon oxide film is formed at about 70 microseconds to about 200 microseconds at the sidewall of the trench 60 to form the trench rather than the bottom of the trench 60. 60 is formed thicker in the side wall.

Accordingly, since the gate insulating layer 66 is formed thicker than the bottom of the trench 60 by fluorine ion implanted into the third impurity region 62 of the sidewall of the trench 60, the gate insulating layer may be formed in a subsequent process. The gate electrode (68 of FIG. 2I) and the gate loading capacitor generated at the corners of the upper portion of the trench 60 may be reduced.

As shown in FIG. 2I, a gate electrode 68 made of polysilicon is formed on the semiconductor substrate 52 on which the gate insulating layer 66 is formed, and the semiconductor substrate 52 on which the gate electrode 68 is formed. A metal layer 70 (for example, SiW) is formed on the conductive metal silicide on the substrate, and the gate upper insulating layer 72 is sequentially stacked on the entire surface of the semiconductor substrate 52 on which the metal layer is formed.

As illustrated in FIG. 2J, the gate stack 74 may be removed by sequentially removing the source and drain regions and a portion of the gate upper insulating layer 72, the metal layer 70, and the gate electrode 68 on the trench 60. Form. At this time, the threshold of the gate stack 74 is formed larger than the open threshold of the trench 60. Although not shown, the threshold of the gate stack 74 may be formed smaller than the open threshold of the trench 60 so as to enter the inside of the trench 60.

As shown in FIG. 2K, an insulating film, such as a silicon nitride film, a silicon oxynitride film, or a silicon oxide film, is formed on the semiconductor substrate 52 on which the gate stack 74 is formed by using chemical vapor deposition, and the insulating film is dry-etched. As a result, spacers 76 are formed on sidewalls of the gate stack 74. In this case, the spacer 76 may be formed to have excellent step coverage in the same groove as the sidewall of the gate stack 74 when the insulating film is formed, thereby forming the insulating film thicker than the flat surface in the groove. When the insulating layer is removed from the planar surface by using the perpendicularity and isotropy of the dry etching, an insulating layer that insulates the metal layer 70 and the gate electrode 68 from the sidewall of the gate stack 74 may be selectively left. .

In addition, a second impurity region 78 is formed by implanting a second impurity into the source and drain regions by a self-aligning method using the spacer 76 as an ion implantation mask.

In addition, after the manufacturing process of the recess transistor according to the present invention is completed, the gate insulating layer 66 on the source and drain regions is removed, an interlayer insulating layer is formed, and contact holes are formed in the source and drain regions, and a conductive metal is formed. The bit line contact and the storage node contact are formed using the C-type bit line contact and the storage node contact.

Accordingly, in the method of manufacturing a recess transistor according to the present invention, a third impurity region 62 is formed on sidewalls of the trench 60 to form a gate insulating layer 66 formed on the sidewalls of the trench 60. Since the gate insulating layer 66 can be formed to be thicker than the gate insulating layer 66 formed therein, a gate generated between the gate electrode 68 and the second impurity region 78 when a gate voltage is applied to the gate electrode 68. The gate loading capacitance can be reduced or minimized and the performance of the transistor can be improved.

In addition, the description of the above embodiment is merely given by way of example with reference to the drawings in order to provide a more thorough understanding of the present invention, it should not be construed as limiting the present invention. In addition, various changes and modifications are possible to those skilled in the art without departing from the basic principles of the present invention.

As described above, in the method of manufacturing a transistor having a recess channel of the present invention, the thickness of the gate insulating film formed on the trench bottom is formed by forming a third impurity region on the trench sidewall and forming the thickness of the gate insulating film formed on the trench sidewall. Since it can be made larger, the gate loading capacitance can be reduced or minimized.

1A to 1J are cross-sectional views illustrating a method of manufacturing a transistor having a recess channel of the prior art.

2A to 2K are cross-sectional views illustrating a method of manufacturing a transistor having a recess channel of the present invention.

* Description of the symbols for the main parts of the drawings *

50 device isolation layer 52 semiconductor substrate

54: pad oxide film 56: hard mask film

58: photoresist pattern 60: trench

62: third impurity region 66: gate insulating film

68 gate electrode 70 metal silicide layer

72: gate upper insulating film 74: gate stack

76 spacer 78 second impurity region

Claims (18)

Forming a trench in an active region of the semiconductor substrate, Forming impurity regions on sidewalls of the trenches; Forming a gate insulating film thicker on the sidewall of the trench where the impurity ion implantation region is formed than the bottom of the trench; And forming a gate stack on the semiconductor substrate having the gate insulating film formed thereon. The method of claim 1, Forming the trench is Sequentially depositing a pad oxide film and a hard mask film on the semiconductor substrate; Forming a photoresist pattern on the semiconductor substrate on which the hard mask film is formed; Etching the hard mask layer by using the photoresist pattern as an etching mask, and removing the photoresist pattern; Removing the pad oxide layer by using the hard mask layer as an etching mask; Etching the semiconductor substrate using the hard mask or pad oxide layer as an etching mask to form a trench; And etching the semiconductor substrate of the trench chuck wall to separate source and drain regions. The method of claim 2, And the pad oxide layer is formed to have a thickness of about 200 kPa to about 600 kPa. The method of claim 2, And the hard mask layer is formed to have a thickness of about 500 mW to about 1000 mW. The method of claim 2, And etching the pad oxide layer and forming the trench in-situ using different reaction gases in one reaction chamber. The method of claim 2, wherein the etching of the semiconductor substrate on the sidewalls of the trench is performed by a wet etching method. The method of claim 1, The trench is a method of manufacturing a transistor having a recess channel, characterized in that formed to have an open threshold of about 500 kHz to 1000 kHz. The method of claim 1, And the trench is formed to have a depth of about 1000 kW to 1700 kW. The method of claim 1, And the impurity region is formed by an ion implantation method. The method of claim 9, The ion implantation method is a method of manufacturing a transistor having a recess channel, characterized in that by implanting fluorine (fluorine) on the sidewall of the trench. The method of claim 10, The ion implantation method is a method of manufacturing a transistor having a recess channel, characterized in that by implanting the fluorine in the sidewalls of the trench at an angle of about 20 degrees to about 50 degrees in the semiconductor substrate. The method of claim 11, And the ion implantation method is symmetrically formed on the sidewalls of the trench. The method of claim 2 or 12, Wherein the ion implantation method uses the hard mask layer or the pad oxide layer adjacent to the trench as an ion implantation mask so that the fluorine does not ion implant into the bottom of the trench. The method of claim 10, Wherein the ion implantation method uses energy of about 20 KeV to about 50 KeV. The method of claim 10, And the ion implantation method is such that the fluorine has a concentration of about 1x10 ¹³ atoms / cm ² to 1x10 ¹⁴ atoms / cm ² . The method of claim 1, And the gate insulating film is formed by a thermal oxidation method. The method of claim 1, And the gate insulating film formed on the bottom of the trench is formed to have a thickness of about 30 kV to about 100 kPa. The method of claim 1, And a gate insulating layer formed on the sidewalls of the trench to have a thickness of about 70 kPa to about 200 kPa.