KR20040057145A - Tft-lcd panel with gate high level voltage and gate low level voltage lines - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) having gate high and low voltage wires is provided to apply gate high and low voltage to the LCD directly, not a gate driver, in a data driver, thereby preventing the values of the gate high and low voltage from reducing. CONSTITUTION: A plurality of gate drivers(300) are installed longitudinally to a side surface of the LCD panel. A plurality of data drivers(310) are installed transversely to another side surface, adjacent to the gate drivers, of the LCD panel. A plurality of data wires(330) and gate wires(320) are arranged at the TFT substrate of the LCD Panel lengthwise and crosswise. The data wire(330) is connected to an output terminal of the data driver(310) and the gate wire(320) is connected to an output terminal of the gate driver(300). A gate signal transfer wire(340) is formed at the corner of the LCD panel to which the gate and data drivers(300,310) are adjacent. A gate high voltage wire(350) and a gate low voltage wire(360) are arranged, in parallel to the data wire(330), between the data wire(330) and the gate driver(300). A switching circuit(370) is formed between the gate high voltage wire(350) and the gate low voltage wire(360).

Description

Liquid crystal display panel with gate high voltage wiring and gate low voltage wiring {TFT-LCD PANEL WITH GATE HIGH LEVEL VOLTAGE AND GATE LOW LEVEL VOLTAGE LINES}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display panel having a gate high voltage wiring and a gate low voltage wiring, and more particularly, to prevent attenuation of gate high voltage and gate low voltage in a line-on-glass type liquid crystal display panel. The present invention relates to a liquid crystal display panel formed in parallel with the data wirings.

TFT-LCD, the flagship product of flat panel displays, is now rapidly growing in size and resolution due to mass production technology and research and development. It is also being developed as an application product and gradually replaces existing cathode ray tube (CRT) products, and its portion in the display device industry is gradually increasing. In today's information society, the display device is more and more important as a visual information transmission medium. In particular, with the trend of light, thin, short, and small in all electronic products, the importance of low power consumption, thinness, light weight, high definition, and portability is increasing. Since the liquid crystal display device is a display device having not only the performance that can satisfy these conditions of the flat panel display but also mass production, various kinds of new products are rapidly created, and the electronic industry has a ripple effect over the semiconductor.

A liquid crystal display device includes: a TFT substrate having a gate line and a data line arranged in a matrix, and having a thin film transistor (TFT) formed at an intersection thereof, a color filter substrate bonded to the TFT substrate, And a data driver positioned at one side of the TFT substrate and connected to the data line to apply a signal, and a gate driver positioned at one side of the gate line and connected to the gate line to transfer a gate signal.

Recently, as the semiconductor thin film forming technology is advanced, the chipset of the gate signal processing controller and the data signal processing controller are highly integrated, the size is smaller and the function becomes more powerful. All drive controllers, including gate signal processing controllers and data signal processing controllers, can be mounted on the source printed circuit board without increasing their area.

As all the driving controllers can be mounted on the source printed circuit board, the gate printed circuit board simply acts as a signal transmission medium for transmitting the gate signal. There is still a need for a signal transmission cable for transmitting signals.

Therefore, a line-on-glass (LOG) type liquid crystal display device which does not require such a signal transmission cable has been developed.

1 is a plan view of a liquid crystal display device in which a gate signal transmission line is formed at an edge of a TFT substrate.

The data signal and the gate signal are input to the data driver 110 from the driving controller installed in the gate printed circuit board 100, and the gate signal is input to the gate driver 130 through the gate signal transmission wiring 120.

In the LOG type liquid crystal display device, a gate signal transmission line 120 for transmitting the gate signal is directly formed on the TFT substrate of the liquid crystal display panel 140 instead of the cable for the gate signal transmission.

As described above, the TFT substrate includes the gate wiring 150 and the data wiring 160 vertically and horizontally, and the thin film transistor 170 is formed at the intersection thereof.

FIG. 2 is an enlarged view of a portion A of FIG. 1 and illustrates a gate signal transmission wiring of a liquid crystal display using the LOG method.

The TFT substrate 220 and the color filter substrate 230 are shown bonded together. The TFT substrate 220 is made larger than the color filter substrate 230 for mounting the driver. The driver is mounted on the TFT substrate 220 to supply a signal to the source pad 240 and the gate pad 210.

The gate signal flows from the gate signal transmission source pad 200 through the gate signal transmission gate pad 210.

Signals such as V _GH , V _GL , G _SP , G _SC , G _OE , and V _COM are transmitted through the gate signal transmission wiring 120. V _GH and V _GL are gate on / off voltages that turn on / off the thin film transistors with gate high voltage and gate low voltage, and G _SC , G _OE, and G _SP control the gate on / off voltage applied to the gate wiring.

Since the gate high voltage V _GH and the gate low voltage V _GL of the signals transmitted through the wiring are analog signals, the gate high voltage V _GH and the gate low voltage V _GL are analog signals, and thus are sensitive to the distortion of the signal caused by the resistance, thereby lowering the voltage value. The TFT must have a current driving capability to sufficiently charge the liquid crystal capacity in a short turn-on time. However, when the voltage value of the gate high voltage V _GH or the gate low voltage V _GL falls, the current driving ability is lowered, so that the capacity of the liquid crystal cannot be sufficiently charged or a leakage current is generated. Therefore, the transmission wiring for the gate high voltage V _GH and the gate low voltage V _GL needs to form a relatively thick wiring to lower the resistance.

However, in the structure as described above, the gate signal transmission wiring 120 is installed at the edge of the TFT substrate 220. The space on the TFT substrate 220 is very narrow for this purpose. Therefore, the line width of the wiring becomes small and the wiring length becomes long for wiring in a narrow area. For this reason, the resistance of the gate high voltage (V _GH ) and gate low voltage (V _GL ) transmission wirings has increased, and thus there is a problem in that the voltage value cannot be maintained.

An object of the present invention is to prevent the reduction of the voltage values of the gate high voltage and the gate low voltage by applying the gate high voltage and the gate low voltage directly from the data driver to the liquid crystal display panel without transmitting the gate high voltage and the gate low voltage. Accordingly, an object of the present invention is to charge sufficient voltage in each pixel of the liquid crystal display panel and to prevent the occurrence of leakage current.

1 is a plan view of a liquid crystal display device in which a gate signal transmission line is formed at an edge of a thin film transistor substrate.

FIG. 2 is an enlarged view illustrating the gate signal transmission wiring of FIG. 1. FIG.

3 is a plan view illustrating a part of a line-on-glass type liquid crystal display panel according to an exemplary embodiment of the present invention.

4 is a circuit diagram showing a switching circuit according to an embodiment of the present invention.

Fig. 5A is a circuit diagram showing an operation when a high logic section of a clock is input to a switching circuit.

Fig. 5B is a circuit diagram showing an operation when a low logic section of the clock is input to the switching circuit.

*** Explanation of symbols for main parts of drawing ***

100: gate printed circuit board 110, 310: data driver

120,340: gate signal transmission wiring 130,300: gate driver

140: liquid crystal display panel 150, 320: gate wiring

160,330: data wiring 170: thin film transistor

200: data pad for gate signal transmission 210: gate pad for gate signal transmission

220: TFT substrate 230: color filter substrate

240: data pad 250: gate pad

350: gate high voltage wiring 360: gate low voltage wiring

370: switching circuit 400: inverter

410: first thin film transistor 420: second thin film transistor

Embodiments of the present invention to achieve the above object is a first substrate; A plurality of gate lines and data lines arranged vertically and horizontally on the first substrate; A thin film transistor formed at an intersection point of the gate line and the data line; A gate high voltage line and a gate low voltage line arranged at an outer side of the first substrate in parallel with the data line; A switching circuit electrically connecting the gate wiring to the gate high voltage wiring if the output pulse of the gate driver is high logic, and electrically connecting the gate wiring to the gate low voltage wiring if the output pulse of the gate driver is low logic; Provided is a liquid crystal display panel including a gate high voltage wiring and a gate low voltage wiring including a second substrate having a color filter bonded to the first substrate and a liquid crystal layer interposed therebetween.

The switching circuit may include an inverter to which an output pulse of a gate driver is input; A first thin film transistor having a gate connected to an input terminal of the inverter, a drain connected to the high voltage gate wiring, and a source connected to the gate wiring; It is preferable to include a second thin film transistor having a gate connected to the output terminal of the inverter, a drain connected to the low voltage gate wiring and a source connected to the gate wiring.

The liquid crystal display panel according to an exemplary embodiment of the present invention may further include a gate signal transmission line formed at an edge of the first substrate to apply a gate signal to the gate driver.

In addition, an embodiment of the present invention comprises the steps of receiving a clock from the switching circuit from the gate driver to achieve the above object; If the clock is high logic, receiving a gate high voltage from a data driver and applying the gate high voltage to a gate line; When the clock is low logic, the method provides a gate high voltage and a gate low voltage application method of a liquid crystal display panel including receiving a gate low voltage from a data driver and applying the same to a gate wiring.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view illustrating a part of a LOG type liquid crystal display device according to an exemplary embodiment of the present invention.

For convenience of description, the liquid crystal display device except for the gate driver and the data driver will be referred to as a liquid crystal display panel.

As shown in the drawing, a plurality of gate drivers 300 are disposed in the longitudinal direction, and on the other side of the liquid crystal display panel, a plurality of data drivers 310 are disposed in the horizontal direction.

A plurality of data lines 330 and gate lines 320 are vertically and horizontally arranged on the TFT substrate of the liquid crystal display panel. The data line 330 is connected to the output terminal of the data driver 310, and the gate line 320 is connected to the output terminal of the gate driver 300. A gate signal transmission line 340 is formed at an edge of the liquid crystal display panel adjacent to the gate driver 300 and the data driver 310.

In the liquid crystal display panel between the data line 330 and the gate driver 300, a gate high voltage line 350 and a gate low voltage line 360 are arranged in parallel with the data line 330.

The switching circuit 370 is formed between the gate high voltage line 350 and the gate low voltage line 360. The gate high voltage line 350 and the gate low voltage line 360 are electrically connected to the switching circuit 370, and an output of the switching circuit 370 is connected to the gate line 320.

The operation of the liquid crystal display device having the above configuration will be described below.

First, the gate driver 300 receives a gate signal from the data driver 310 through the gate signal transmission line 340.

As described above, the gate signal is composed of signals such as V _GH , V _GL , G _SP , G _SC , G _OE , and V _COM . However, in the exemplary embodiment of the present invention, the signals other than V _GH and V _GL are not included in the gate driver 300. Is entered.

When the gate signal is input to the gate driver 300, the gate driver 300 sets a clock having a high logic of one horizontal period by an internal shift register for each gate wiring 320. Output sequentially. One horizontal period refers to a time when a data voltage is applied to a pixel formed on one gate line. The clock output to each gate wiring 320 is shown on the output side of the gate driver 300 of FIG. 3.

In the case of an XGA-class liquid crystal display device, the gate driver 300 having 256 channels is used, and the gate signal transfer between the gate drivers 300 is performed by applying a CARRY signal.

The clock output from the gate driver 300 is input to the switching circuit 370.

When a clock having a high logic is input to the switching circuit 370, the switching circuit 370 connects the gate high voltage wiring 350 to the gate wiring 320. On the contrary, when a clock having a low logic is input to the switching circuit 370, the switching circuit 370 connects the gate low voltage wiring 360 to the gate wiring 320.

Therefore, the wiring for transmitting the gate high voltage and the gate low voltage may be formed in parallel with the data line 330 of the liquid crystal display without forming the wiring at the corner of the liquid crystal display. Since the space in the liquid crystal display for forming the gate high voltage wiring 350 and the gate low voltage wiring 360 is larger than the corners, the line width of the wiring can be arbitrarily adjusted in consideration of resistance.

In addition, a chip-on-glass (COG) method in which the gate driver and the data driver are mounted directly outside the TFT substrate without using a tape-carrier-package (TCP). In this case, a wiring for transmitting the gate signal should be formed on the substrate. Therefore, even in this case, according to the exemplary embodiment of the present invention, the gate high voltage wiring and the gate low voltage wiring are formed in the liquid crystal display panel, thereby reducing the voltage value.

4 is a circuit diagram illustrating the switching circuit of FIG. 3.

The switching circuit is composed of an inverter 400, a first TFT 410 and a second TFT 420.

The output terminal of the gate driver is connected to the input terminal of the inverter 400.

The gate terminal of the first TFT 410 is connected to the attraction terminal of the inverter 400 and the source terminal is connected to the gate high voltage wiring VGH. In addition, the drain terminal is connected to the gate wiring 320.

The gate terminal of the second TFT 420 is connected to the output terminal of the inverter 400 and the source terminal is connected to the gate low voltage wiring VGL. In addition, the drain terminal is connected to the gate wiring 320 similarly to the first TFT 410.

The detailed operation of the switching circuit will be described with reference to FIGS. 5A and 5B.

FIG. 5A shows the operation when the high logic section of the clock is input to the switching circuit.

When the high logic section of the clock is input to the input terminal of the inverter 400, the high logic voltage of the clock is applied to the gate of the first TFT 410 connected thereto. Accordingly, the first TFT 410 is turned on and the gate high voltage V _GH supplied to the source is applied to the gate line 320 through the drain. Therefore, all of the TFTs of the selected gate wiring 320 are turned on to charge the pixel voltage by the data wiring.

Meanwhile, the high logic section of the clock passing through the inverter 400 is changed to the low logic section. Accordingly, since the low logic voltage of the clock is applied to the gate of the second TFT 420 connected to the output terminal of the inverter 400, the second TFT 420 is not turned on. Therefore, since the gate low voltage V _GL supplied to the source of the second TFT 420 is not applied to the drain, it maintains an open state with the gate wiring 320.

5B illustrates an operation when a low logic section of the clock is input to the switching circuit.

When the low logic period of the clock is input to the input terminal of the inverter 400, the low logic voltage of the clock is applied to the gate of the first TFT 410 connected thereto. Therefore, the first TFT 410 cannot be turned on. Therefore, the gate high voltage V _GH supplied to the source of the first TFT 410 is not applied to the drain and thus remains open with the gate wiring 320.

On the other hand, the low logic section of the clock passing through the inverter 400 is changed to a high logic section. Therefore, since the high logic voltage of the clock is applied to the gate of the second TFT 420 connected to the output terminal of the inverter 400, the second TFT 420 is turned on. Therefore, the gate low voltage V _GL supplied to the source of the second TFT 420 is applied to the gate wiring 320 through the drain. Therefore, the TFT is not turned on in the gate wiring to which the gate low voltage is supplied.

It will be appreciated by those skilled in the art that the gate high voltage wiring, the gate low voltage wiring and the switching circuit according to the embodiment of the present invention can be manufactured together with the thin film transistor used as the switching element of each pixel.

Many details are set forth in the foregoing description, but they should be construed as preferred embodiments rather than limiting the scope of the invention.

For example, the above description has been given of the LOG type liquid crystal display device, but the present invention also applies to a liquid crystal display device that transmits a gate signal using a flexible printed circuit (FPC), which is a conventional signal transmission cable. It will be appreciated by those skilled in the art that this can be applied.

Therefore, the scope of the invention should not be defined by the described embodiments, but should be defined by the claims and the equivalents of the claims.

According to the present invention, since the wirings for the gate high voltage and the gate low voltage are directly formed in the liquid crystal display panel in parallel with the data lines, the gate high voltage and the gate low voltage can be directly applied to the source driver without the need to transfer the gate high voltage and the gate low voltage to the gate driver. Therefore, the line width design of the wiring is freer than in the corner area, which is a narrow space of the liquid crystal display panel, thereby preventing the reduction of the voltage value.

Claims (5)

A first substrate; A plurality of gate lines and data lines arranged vertically and horizontally on the first substrate; A thin film transistor formed at an intersection point of the gate line and the data line; A gate high voltage line and a gate low voltage line arranged at an outer side of the first substrate in parallel with the data line; A switching circuit electrically connecting the gate wiring to the gate high voltage wiring if the output pulse of the gate driver is high logic, and electrically connecting the gate wiring to the gate low voltage wiring if the output pulse of the gate driver is low logic; And a gate high voltage wiring and a gate low voltage wiring including a second substrate having a color filter bonded to the first substrate and the liquid crystal layer interposed therebetween. The method of claim 1, wherein the switching circuit, An inverter to which an output pulse of the gate driver is input; A first thin film transistor having a gate connected to an input terminal of the inverter, a drain connected to the high voltage gate wiring, and a source connected to the gate wiring; And a second thin film transistor having a gate connected to an output terminal of the inverter, a drain connected to the low voltage gate wiring, and a source connected to the gate wiring. The liquid crystal display panel of claim 1, further comprising a gate signal transmission line formed at an edge of the first substrate to apply a gate signal to the gate driver. 2. The liquid crystal display panel of claim 1, wherein the gate driver is mounted on a first substrate. The switching circuit receives a clock from the gate driver; If the clock is high logic, receiving a gate high voltage from a data driver and applying the gate high voltage to a gate line; And applying a gate low voltage from a data driver to the gate wiring when the clock is low logic.