KR20050066744A - Liquid crystal display device of line-on-glass type - Google Patents

Abstract

The present invention relates to a LOG type liquid crystal display device capable of preventing crosstalk and greenish.

The line-on-glass liquid crystal display according to an exemplary embodiment of the present invention compensates the voltage of the common electrode which is changed according to the data voltage supplied to the pixel electrode and supplies the compensated common voltage to both sides of the common electrode. Compensation unit is provided.

According to the present invention, since the compensation signal generated from the signal compensator is supplied to both sides of the common electrode, the compensation signal can be supplied to the liquid crystal panel even when only one of the signals is conducted. Accordingly, crosstalk or greenish phenomenon generated in the liquid crystal panel can be prevented.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY DEVICE OF LINE-ON-GLASS TYPE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a LOG type liquid crystal display device capable of preventing crosstalk and greenish.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

In the liquid crystal panel, the gate lines and the data lines are arranged to cross each other, and the liquid crystal cells are positioned in an area where the gate lines and the data lines cross each other. The liquid crystal panel is provided with pixel electrodes and a common electrode for applying an electric field to each of the liquid crystal cells. Each of the pixel electrodes is connected to any one of the data lines via source and drain terminals of a thin film transistor, which is a switching element. The gate terminal of the thin film transistor is connected to any one of the gate lines through which the pixel voltage signal is applied to the pixel electrodes of one line.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, and driving the liquid crystal panel and the driving circuits. And a power supply unit for supplying necessary power signals.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP by a chip on film (COF) method, and electrically connected to a liquid crystal panel by a tape automated bonding (TAB) method. Is connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub-PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

The drive ICs mounted on the liquid crystal panel in the COG method are control signals and pixels from the timing controller mounted on the main PCB through line on glass (LOG) signal lines formed on the FPC and the liquid crystal panel. Power signals from the data and the power supply are supplied.

Recently, even when the drive ICs are connected to the liquid crystal panel via TCP, the liquid crystal display device is made thinner by adopting LOG type signal lines to eliminate the PCB. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed on the liquid crystal panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied. In this case, the gate control signals and the gate power signals supplied to the gate drive IC are distorted by the line resistances of the LOG signal lines, thereby degrading the quality of the image displayed on the LCD panel.

In fact, the liquid crystal display device in which the gate PCB is removed by using the LOG signal signal lines has a gate for driving the liquid crystal panel 6 and the gate lines GL1 to GLn of the liquid crystal panel 6 as shown in FIG. 1. The drive IC 10, the data drive IC 14 for driving the data lines DL1 to DLm of the liquid crystal panel 6, the gate drive IC 10 and the data drive IC 14 for controlling the A timing controller 22, a power supply unit 24 for generating a driving voltage necessary for driving the liquid crystal display, and a signal compensator 27 for compensating for distortion of driving signals applied to the liquid crystal panel 6; .

The power supply unit 24 uses driving voltages (gate high voltage VGH, gate low voltage signal VGL, reference gamma voltage, and common voltage) required to drive the liquid crystal display using a voltage input from a system power supply (not shown). Voltage VCOM, etc.) are supplied to the timing controller 22, the data drive IC 14, the gate drive IC 10, and the like.

The timing controller 22 relays the video data R, G, and B from the graphics card and supplies the data drive IC 14 to the data drive IC 14. In addition, the timing controller 22 generates timing signals and control signals for controlling the timing of the data driver IC 14 and the gate drive IC 10 in response to a control signal from the graphics card.

The liquid crystal panel 6 is formed by bonding the lower substrate 2 and the upper substrate 4 with the liquid crystal interposed therebetween. The liquid crystal panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal panel 6. Here, the data drive ICs 14 are mounted in the IC area opened in the data TCP 12 or mounted on the base film of the data TCP 12 in a COF manner. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 receive data control signals, pixel data, and power signals from the timing controller 22 and the power supply unit 24 on the main PCB 20 through the data PCB 16.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal panel 6. Here, the gate drive ICs 10 are mounted in the IC region opened at the gate TCP 8 or mounted on the base film of the gate TCP 8 in a COF manner. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

For this purpose, the gate control signals and power signals from the timing controller 22 and the power supply unit 24 are supplied to the data TCP 12 via the FPC 18 and the data PCB 20. Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the lower substrate 2. Gate control signals and power signals supplied to the gate TCP 8 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10 so as to be mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 together with the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. DC drive voltages being; The signal line is configured to supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE. A plurality of silver dots are formed between the common voltage supply line LVCOM supplying the common voltage VCOM among the LOG signal line group 26 and the common electrode formed on the upper substrate 4. At this time, each of the plurality of silver dots 28a to 28d is positioned at an edge region of the liquid crystal panel 6.

The signal compensator 27 is positioned between the power supply 24 and the liquid crystal panel 8. In other words, the signal compensator 27 is positioned on any one of the main PCB 20, the data PCB 16, and the lower substrate 2. The signal compensator 27 includes a gate low voltage FVGL and a common voltage VCOM fed back through the gate low voltage supply line LVGL for supplying the gate low voltage VGL to the liquid crystal panel 6. At least one of the compensation common voltage BVCOM and the compensation gate low voltage BVGL is generated using at least one of the common voltage FVCOM fed back through the supplied common voltage supply line LVCOM.

In the LOG type liquid crystal display device, when a data voltage is applied to the liquid crystal panel 6, an impulse waveform such as (a) of FIG. 2 is generated due to the coupling phenomenon of the liquid crystal panel 6. Since the impulse waveform deteriorates the image quality of the liquid crystal panel 6, the signal is compensated by the signal compensator 27. That is, the signal compensator 27 inverts an impulse waveform and supplies it to the liquid crystal panel 6 as shown in FIG.

However, in the conventional LOG type liquid crystal display device, since the compensation signal generated from the signal compensator 27 is supplied to the liquid crystal panel 6 through the first silver dot 28a as shown in FIG. The energized (conductive) state of the silver dot 28a should be good. In other words, if the energization state of the first silver dot 28a is not good, the compensation signal generated from the signal compensator 27 is not smoothly supplied to the liquid crystal panel 6. In addition, since the impulse waveform generated in the liquid crystal panel 6 is fed back to the signal compensator 27 through the fourth silver dot 28d, the energized state of the fourth silver dot 28d should also be good. In other words, if the energized state of the fourth silver dot 28d is not good, the impulse waveform generated by the liquid crystal panel 6 is not supplied to the signal compensator 27 properly, so that the signal compensator 27 is a liquid crystal panel ( The compensation signal required in 6) cannot be supplied. As described above, in the conventional LOG type liquid crystal display device, if the energization state of any one of the first and fourth silver dots 28a and 28d is not good, the compensation signal from the signal compensator 27 is smoothly applied to the liquid crystal panel. Since it is not supplied, defects such as crosstalk and greenish may occur.

Accordingly, an object of the present invention is to provide a LOG type liquid crystal display device capable of preventing crosstalk and greenish phenomenon.

In order to achieve the above object, the line-on-glass type liquid crystal display according to an exemplary embodiment of the present invention compensates the voltage of the common electrode that is changed according to the data voltage supplied to the pixel electrode, and compensates the common voltage for the common voltage. A signal compensating part is provided to both sides of the electrode.

The common electrode is formed on an upper substrate, and the compensated common voltage is supplied through a silver dot formed between the upper substrate and the lower substrate.

A first common voltage supply line formed on the lower substrate to be connected to an output terminal of the signal compensator and a first silver dot connected to one side of the common electrode, and an output terminal of the signal compensator and the other side of the common electrode And a second common voltage supply line formed on the lower substrate to be connected to the connected second silver dot.

And a third common voltage supply line formed on the lower substrate to be connected to an input terminal of the signal compensator and the common electrode.

The third common voltage supply line is connected to any one of the first and second silver dots.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 and 5.

4 is a diagram illustrating a LOG type liquid crystal display device according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a detailed view of a common voltage supply line for supplying a common voltage to the liquid crystal panel illustrated in FIG. 4.

4 and 5, a LOG type liquid crystal display according to an exemplary embodiment of the present invention may include a gate drive IC for driving the liquid crystal panel 36 and gate lines GL1 to GLn of the liquid crystal panel 36. 40, a data drive IC 44 for driving the data lines DL1 to DLm of the liquid crystal panel 36, and a timing controller for controlling the gate drive IC 40 and the data drive IC 44. 52, a power supply unit 54 for generating a driving voltage required for driving the liquid crystal display, and a signal compensating unit 57 for compensating for distortion of driving signals applied to the liquid crystal panel 36.

The power supply unit 54 uses driving voltages (gate high voltage VGH, gate low voltage signal VGL), reference gamma voltage, and common voltages required to drive the liquid crystal display using a voltage input from a system power supply (not shown). Voltage VCOM, etc.) are supplied to the timing controller 52, the data drive IC 44, the gate drive IC 40, and the like.

The timing controller 52 relays video data (R, G, B) from the graphics card and supplies it to the data drive IC 44. In addition, the timing controller 52 generates timing signals and control signals for controlling the timing of the data and the gate drive IC 40 in response to the control signal from the graphics card.

The liquid crystal panel 36 is formed by bonding the lower substrate 32 and the upper substrate 34 with the liquid crystal interposed therebetween. The liquid crystal panel 36 is provided with liquid crystal cells independently driven by a thin film transistor in each region defined by the intersection of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 44 are connected to the data lines DL via the data TCP 42 and the data pad portion of the liquid crystal panel 36. Here, the data drive ICs 44 are mounted in the IC area opened in the data TCP 42 or mounted on the base film of the data TCP 42 in a COF manner. The data drive ICs 44 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 44 receive data control signals, pixel data, and power signals from the timing controller 52 and the power supply unit 54 on the main PCB 50 through the data PCB 46.

The gate drive ICs 40 are connected to the gate lines GL via the gate TCP 38 and the gate pad portion of the liquid crystal panel 36. Here, the gate drive ICs 40 are mounted in the IC region opened at the gate TCP 38 or mounted on the base film of the gate TCP 38 in a COF manner. The gate drive ICs 40 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 40 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate gate control signals and power signals from the timing controller 52 and the power supply 54 are supplied to the data TCP 42 via the FPC 48 and the data PCB 46. Gate control signals and power signals supplied through the data TCP 42 are supplied to the gate TCP 38 via the LOG signal line group 56 formed in the edge region of the lower substrate 32. Gate control signals and power signals supplied to the gate TCP 38 are input into the gate drive IC 40 through the input terminals of the gate drive IC 40 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 40, and the gate drive IC mounted on the next gate TCP 38 via the gate TCP 38 and the LOG signal line group. 40 is supplied.

The LOG signal line group 56 is formed on the lower substrate 34 and is usually formed of a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. DC drive voltages supplied from the power supply unit 54, such as; It is composed of signal lines for supplying each of the gate control signals supplied from the timing controller 52, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE. A plurality of silver dots 58a to 58d are formed between the common voltage supply line LVCOM supplying the common voltage VCOM among the LOG signal line group 56 and the common electrode formed on the upper substrate 34. . At this time, each of the silver dots 58a to 58d is positioned at an edge region of the liquid crystal panel 36. In addition, the common voltage supply line LVCOM is cut between a portion of the second silver dot 58b and the third silver dot 58c, and the common voltage supply line LVCOM of the cut portion is connected to the signal compensating portion 57. Connected. As a result, the signal compensator 57 receives the feedback signal through the common voltage supply line LVCOM of the cut portion.

The signal compensator 57 is positioned between the power supply 54 and the liquid crystal panel 36. In other words, the signal compensator 57 is positioned on any one of the main PCB 50, the data PCB 46, and the lower substrate 32. The signal compensator 57 has a gate low voltage FVGL and a common voltage VCOM fed back through the gate low voltage supply line LVGL for supplying the gate low voltage VGL to the liquid crystal panel 36. At least one of the compensation common voltage BVCOM and the compensation gate low voltage BVGL is generated using at least one of the common voltage FVCOM fed back through the supplied common voltage supply line LVCOM.

The LOG-type liquid crystal display device cuts between the second silver dot 58b and the third silver dot 58c when an impulse waveform such as (a) of FIG. 2 is generated due to the coupling phenomenon of the liquid crystal panel 36. The impulse waveform is fed back through the common voltage supply line LVCOM and the fed impulse waveform is supplied to the signal compensator 57. At this time, the signal compensator 57 inverts and amplifies the feedback impulse waveform as shown in FIG. 2 (b) to impinge on the first and fourth silver dots 58a and 58d.

As described above, the LOG type liquid crystal display according to the exemplary embodiment of the present invention supplies a compensation signal to the first and fourth silver dots 58a and 58d so that only one of the first and fourth silver dots 58a and 58d is conductive. Even if it is, the compensation signal from the signal compensator 57 is supplied to the liquid crystal panel 36. As a result, since the impulse waveform generated in the liquid crystal panel 36 is compensated, crosstalk or greenish phenomenon can be prevented.

As described above, in the LOG type liquid crystal display according to the exemplary embodiment of the present invention, since the compensation signal generated from the signal compensator is supplied to both sides of the common electrode, the compensation signal may be supplied to the liquid crystal panel even if only one of the conductive signals is conducted. Accordingly, crosstalk or greenish phenomenon generated in the liquid crystal panel can be prevented.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a view showing a conventional LOG type liquid crystal display device.

FIG. 2 is a diagram illustrating input and output waveforms of the signal compensator shown in FIG. 1.

FIG. 3 is a diagram illustrating in detail a common voltage supply line for supplying a common voltage to the liquid crystal panel shown in FIG. 1.

4 is a diagram illustrating a LOG type liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 5 is a diagram illustrating in detail a common voltage supply line for supplying a common voltage to the liquid crystal panel illustrated in FIG. 4.

<Description of main parts of drawing>

2, 32: lower substrate 4, 34: upper substrate

6, 36: liquid crystal panel 8, 38: gate TCP

10, 40: gate drive IC 12, 42: data TCP

14, 44: data drive IC 16, 46: data PCB

18, 48: FPC 20, 50: Main PCB

22, 52: timing control unit 24, 54: power supply unit

26, 56: LOG type signal line group 27, 57: signal compensator

28a-28d, 58a-58d: silver dot

Claims (5)

In a liquid crystal display device having a pixel electrode and a common electrode for applying an electric field to a liquid crystal cell, And a signal compensator for compensating the voltage of the common electrode which is changed according to the data voltage supplied to the pixel electrode and supplying the compensated common voltage to both sides of the common electrode. . The method of claim 1, And the common electrode is formed on an upper substrate, and the compensated common voltage is supplied through a silver dot formed between the upper substrate and the lower substrate. The method of claim 1, A first common voltage supply line formed on the lower substrate to be connected to an output terminal of the signal compensator and a first silver dot connected to one side of the common electrode; And a second common voltage supply line formed on the lower substrate to be connected to an output terminal of the signal compensator and a second silver dot connected to the other side of the common electrode. . The method of claim 1, And a third common voltage supply line formed on the lower substrate so as to be connected to an input terminal of the signal compensating unit and the common electrode. The method of claim 4, wherein And the third common voltage supply line is connected to any one of the first and second silver dots.