KR20050001064A - Liquid crystal display of line-on-glass type - Google Patents

Abstract

PURPOSE: A line-on-glass type LCD device is provided to obtain a thin size by removing a gate PCB(printed circuit board) and a data PCB. CONSTITUTION: A line-on-glass type LCD device includes an LCD panel(106) having a plurality of gate and data lines(GL,DL), a plurality of data integrated circuits(114) supplying a pixel data voltage to the data lines, first signal lines formed on a substrate of the LCD panel, connected between the data integrated circuits, and transmitting a first driving signal to the data integrated circuits, and second signal lines formed to overlap the first signal lines, connected between the data integrated circuits, and transmitting second driving signals to the data integrated circuits. The first signal lines are overlapped with the second signal lines between an insulating film formed on the substrate.

Description

Line on glass type liquid crystal display device {LIQUID CRYSTAL DISPLAY OF LINE-ON-GLASS TYPE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a LOG type liquid crystal display device that can achieve a thinning.

The liquid crystal display displays an image by adjusting the light transmittance of the liquid crystal having dielectric anisotropy using an electric field. To this end, the liquid crystal display includes a liquid crystal display panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal display panel.

In the liquid crystal display panel, the liquid crystal cells display an image by adjusting the light transmittance according to the pixel signal.

The driving circuit includes a gate driver for driving the gate lines of the liquid crystal display panel, a data driver for driving the data lines, a timing controller for controlling the driving timing of the gate driver and the data driver, the liquid crystal display panel and the driving. And a power supply unit supplying power signals necessary for driving the circuits.

The data driver and the gate driver are separated into a plurality of integrated circuits (hereinafter, referred to as ICs) and manufactured in a chip form. Each of the integrated drive ICs is mounted on an open IC area on a tape carrier package (TCP) or mounted on a base film of TCP in a chip on film (COF) method, and a liquid crystal display panel and a tape automated bonding (TAB) method. Electrically connected. In addition, the drive IC may be directly mounted on the liquid crystal panel using a chip on glass (COG) method. The timing control unit and the power supply unit are manufactured in a chip form and mounted on a main printed circuit board (PCB).

The drive ICs connected to the liquid crystal display panel by TCP are connected to the timing control part and the power supply part of the main PCB through the flexible printed circuit (FPC) and the sub PCB. Specifically, the data drive ICs receive data control signals and pixel data from the timing controller mounted on the main PCB through the FPC and the data PCB, and power signals from the power supply. The gate drive ICs receive gate control signals from the timing controller mounted on the main PCB and power signals from the power supply through the gate FPC and the gate PCB.

The drive ICs mounted on the liquid crystal display panel in the COG method are control signals from the timing controller mounted on the main PCB through line-on-glass signal lines formed on the FPC and the liquid crystal display panel. And power signals from the pixel data and the power supply unit.

Recently, even when the drive ICs are connected to the liquid crystal display panel via TCP, the LOG type signal lines are adopted to eliminate the PCB, thereby making the liquid crystal display device even thinner. In particular, signal lines for removing gate PCBs that transmit relatively few signals and supplying gate control signals and power signals to gate drive ICs are formed in a LOG type on the liquid crystal display panel. Accordingly, the gate drive ICs mounted in TCP are gate control signals from the timing controller and power signals from the power supply via the main PCB-> FPC-> data PCB-> data TCP-> LOG signal line-> gate TCP. Will be supplied.

In detail, the LOG type liquid crystal display device in which the gate PCB is removed includes the main PCB 20 including the timing controller 22 and the power supply unit 24 and the main PCB (FPC 18) as shown in FIG. 1. A data PCB 16 connected to the 20, a data drive IC 14 mounted thereon, a data TCP 12 connected between the data PCB 16 and the liquid crystal display panel 6, and a gate drive IC 10; And a gate TCP 8 connected to the liquid crystal display panel 6.

The liquid crystal display panel 6 is formed by bonding the lower array substrate 2 and the upper array substrate 4 with the liquid crystal interposed therebetween. The liquid crystal display panel 6 includes liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The data drive ICs 14 are connected to the data lines DL via the data TCP 12 and the data pad portion of the liquid crystal display panel 6. The data drive ICs 14 convert the pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 14 transmit data control signals, pixel data, and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 via the data PCB 16 and the FPC 18. Will be supplied.

The gate drive ICs 10 are connected to the gate lines GL via the gate TCP 8 and the gate pad portion of the liquid crystal display panel 6. The gate drive ICs 10 sequentially supply scan signals of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 10 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing control unit 22 and the power supply unit 24 on the main PCB 20 are supplied to the data TCP 12 via the FPC 18 and the data PCB 16. . Gate control signals and power signals supplied through the data TCP 12 are supplied to the gate TCP 8 via the LOG signal line group 26 formed in the edge region of the lower array substrate 2. Gate control signals and power signals supplied to the gate TCP 12 are input into the gate drive IC 10 through the input terminals of the gate drive IC 10 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 10, and the gate drive mounted on the next gate TCP 8 via the gate TCP 8 and the LOG signal line group 26. It is supplied to the IC 10.

The LOG signal line group 26 is normally supplied from the power supply unit 24 such as the gate low voltage VGL, the gate high voltage VGH, the common voltage VCOM, the ground voltage GND, and the base driving voltage VCC. Direct current driving voltages; It is composed of signal lines that supply each of the gate control signals supplied from the timing controller 22, such as the gate start pulse GSP, the gate shift clock signal GSC, and the gate enable signal GOE.

As described above, since the number of gate supply lines for supplying gate signals including gate control signals and power signals necessary for the conventional gate drive ICs 10 is not large, the supply lines are formed on the liquid crystal display panel 6 in the form of LOG. Can be formed. As a result, since the gate PCB can be removed, the liquid crystal display device can be thinned.

However, although the gate PCB can be removed to make the liquid crystal display device somewhat thinner, there is still a need for thinning the liquid crystal display device since the data PCB exists.

Accordingly, it is an object of the present invention to provide a LOG type liquid crystal display device which can be thinned.

1 is a plan view illustrating a liquid crystal display device in which a conventional gate printed circuit board is removed.

2 is a plan view illustrating a liquid crystal display device with a data printed circuit board removed according to a first embodiment of the present invention.

3 is a plan view specifically illustrating the line-on-glass data signal line group shown in FIG. 2.

4 is a cross-sectional view illustrating in detail the line-on-glass data signal line group shown in FIG. 2.

5 is a cross-sectional view illustrating in detail the LOG type reference signal line and the LOG type high frequency signal line shown in FIGS. 3 and 4.

6 is a cross-sectional view illustrating a group of data signal lines in a liquid crystal display device with a data printed circuit board removed according to a second exemplary embodiment of the present invention.

<Description of main parts of drawing>

2,102: lower array substrate 4,104: upper array substrate

6,106: liquid crystal display panel 8,108: gate TCP

10110: Gate Drive IC 12112: Data TCP

14,114: Data Drive IC 16,116: Data PCB

18,118: FPC 20,120: Main PCB

22,122: timing controller 24,124: power supply

In order to achieve the above object, a line on glass type liquid crystal display according to the present invention includes a liquid crystal panel having a plurality of gate lines and a plurality of data lines, and a plurality of data for supplying pixel data voltages to the data lines. A first signal line formed on an integrated circuit, a substrate of the liquid crystal panel, and connected between the data integrated circuits to transmit a first driving signal to the data integrated circuits, and overlapping the first signal line; And a plurality of second signal lines connected between the data integrated circuits to transmit second driving signals to the data integrated circuits, wherein the first signal line and the second signal line are formed on the substrate. And an insulating film formed therebetween.

The second signal line is characterized in that for transmitting a signal of a high frequency component.

The second signal line may transmit at least one of a data and a clock signal.

The first signal line supplies at least one of ground power and digital power.

Each of the second signal lines may be formed to have the same width and height and maintain the same spacing as the adjacent second signal lines.

The first signal lines are formed of the same metal as the gate line, and the second signal lines are formed of the same metal as the data line.

The liquid crystal display further includes a shielding layer formed adjacent to the second signal lines.

Any one of a ground power source and a digital power source is applied to the shielding layer.

The liquid crystal display further includes a gate integrated circuit for supplying a gate signal to the gate line, and a third signal line formed on the liquid crystal panel to supply driving signals required by the gate integrated circuit. It is done.

The liquid crystal display further includes a power supply for generating a power signal for driving the data integrated circuit, and a timing controller for generating a data control signal for controlling the data integrated circuit.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 2 to 6.

2 is a view showing a LOG type liquid crystal display device according to the present invention.

Referring to FIG. 2, the LOG-type liquid crystal display according to the present invention includes a main PCB 120 including a timing controller 122 and a power supply unit 124, and a data drive IC 114 to mount the liquid crystal display panel 106. ) And a gate TCP 108 connected to the liquid crystal display panel 106 by mounting the data TCP 112 connected to each other and the gate drive IC 110.

The power supply unit 124 of the main PCB uses driving voltages for driving the liquid crystal display using voltages input from a system power supply unit (not shown), for example, a gate high voltage VGH and a gate low voltage signal VGL. The reference voltages VCC and VCC and the common voltage VCOM are generated and supplied to the data drive IC 114 and the gate drive IC 110.

The timing controller 122 of the main PCB 120 relays the video data R, G, and B from the graphics card to supply the data drive IC 114. In addition, the timing controller 122 generates timing signals and control signals for controlling the timing of the data and gate drive ICs 114 and 110 in response to a control signal from the graphics card.

The liquid crystal display panel 106 is formed by bonding the lower array substrate 102 and the upper array substrate 104 to each other with the liquid crystal interposed therebetween. The liquid crystal display panel 106 is provided with liquid crystal cells independently driven by thin film transistors in regions defined by intersections of the gate lines GL and the data lines DL. The thin film transistor supplies the pixel signal from the data line DL to the liquid crystal cell in response to the scan signal from the gate line GL.

The gate drive ICs 110 are connected to the gate lines GL via the gate TCP 18 and the gate pad portion of the liquid crystal display panel 106. The gate drive ICs 110 sequentially supply a scan signal of the gate high voltage VGH to the gate lines GL. In addition, the gate drive ICs 110 supply the gate low voltage VGL to the gate lines GL in a period other than the period in which the gate high voltage VGH is supplied.

To this end, gate control signals and power signals from the timing controller 122 and the power supply 124 on the main PCB 120 are supplied to the data TCP 112 via the FPC 118. Gate control signals and power signals supplied through the data TCP 112 are supplied to the gate TCP 108 via the LOG type gate signal line 126 formed in the edge region of the lower array substrate 102. Gate control signals and power signals supplied to the gate TCP 108 are input into the gate drive IC 110 through the input terminals of the gate drive IC 110 and used. The gate control signals and the power signals are output through the output terminals of the gate drive IC 110 to be mounted on the next gate TCP 108 via the gate TCP 108 and the LOG type gate signal line 126. It is supplied to the drive IC 110.

The LOG-type gate signal line 126 is typically provided from a power supply unit (not shown) such as a gate low voltage VGL, a gate high voltage VGH, a common voltage VCOM, a ground voltage GND, and a base driving voltage VCC. Supplied DC drive voltages; A signal line is provided to supply each of the gate control signals supplied from a timing controller (not shown), such as a gate start pulse GSP, a gate shift clock signal GSC, and a gate enable signal GOE.

The data drive ICs 114 are connected to the data lines DL via the data TCP 112 and the data pad portion of the liquid crystal display panel 106. The data drive ICs 114 convert pixel data into analog pixel signals and supply them to the data lines DL. To this end, the data drive ICs 114 receive data control signals, pixel data, and power signals from the timing controller 122 and the power supply unit 124 on the main PCB 120 through the FPC 118.

To this end, data control signals, pixel data and power signals from the timing controller 122 and the power supply unit 124 on the main PCB 120 are supplied to the first data TCP 112 via the FPC 118. Data control signals, pixel data and power signals supplied to the first data TCP 108 are input into the data drive IC 110 through the input terminals of the data drive IC 110 and used. The data control signals, pixel data, and power signals are output through the output terminals of the data drive IC 110 to the next data TCP 108 via the data TCP 108 and the LOG type data signal line 126. It is supplied to the mounted data drive IC 110.

The LOG data signal line may include driving voltages such as an analog voltage VDD, a digital power supply VCC, a common voltage VCOM, and a ground voltage GND generated by the power supply unit 124; Data control signals such as a source start pulse SSP, a source output enable SOE, a polarity control signal POL, a source shift clock SSC, etc. generated by the timing controller 122; The timing controller 122 includes signal lines for supplying the aligned pixel data, respectively.

Here, the first LOG data signal lines 94 supplying driving voltages such as an analog voltage VDD, a digital power supply VCC, a common voltage VCOM, and a ground voltage GND are shown in FIG. 3. A gate metal, which is the same metal as the gate line GL formed on the liquid crystal display panel, is formed on the lower substrate 90 of the liquid crystal display panel. In particular, the LOG type reference signal lines 80 for supplying the ground voltage GND or the digital power supply VCC are formed in a relatively wide width as shown in FIGS. 3 and 4 to form the second LOG data signal line. It is formed to overlap with the LOG type high frequency signal lines 82 for supplying a signal of a high frequency component of the 96.

The second LOG data signal lines 96 for supplying a low frequency control signal, a gamma signal, a pixel data, a clock signal, and the like are formed on the liquid crystal display panel on the lower substrate 90 on which the gate insulating film 92 is formed. It is formed of a data metal that is the same metal as the line DL. In order to prevent these corrosion, the protective film 98 is formed so that these may be covered.

Among the second LOG type data signal lines 96, the LOG type high frequency signal lines 82 supplying at least one of a signal including a high frequency component, for example, pixel data and a clock signal, satisfy Equation 1 below. As shown in FIG. 5, the LOG type reference signal line 80 and the gate insulating film 92 are formed to overlap each other so that their respective impedances Z are the same. Where h is the thickness of the gate insulating film 92, w is the width of the second LOG high frequency signal line 82, ε is the dielectric constant of the gate insulating film 92, and t is the thickness of the second LOG high frequency signal line 82. Represent each.

Accordingly, signal interference and electromagnetic shielding (hereinafter, referred to as "EMI") between the LOG data signal lines 98 and 94 may be prevented.

In addition, the LOG high frequency signal line 82 which transmits signals including high frequency components among the second LOG data signal lines 98 overlaps the LOG type reference signal line 80 of the first LOG data signal lines. Is formed. Accordingly, a capacitor is formed between the LOG type reference signal line 80 and the LOG type high frequency signal line 82. The capacitor significantly reduces EMI by bypassing an EMI signal, which is a high frequency component, from the second LOG data transmission lines.

6 is a cross-sectional view of a LOG type liquid crystal display device according to a second embodiment of the present invention.

Referring to FIG. 6, the LOG type liquid crystal display according to the second exemplary embodiment of the present invention is further provided with an electromagnetic shielding layer 88 as compared to the liquid crystal display shown in FIGS. 2 to 4. With the same components.

The electromagnetic wave shielding layer 88 is located outside the LOG type high frequency signal line 82 and is supplied with the ground voltage GND or the digital voltage VCC. A capacitor is formed between the electromagnetic shielding layer 88 and the LOG type high frequency signal line 82. By this capacitor, the EMI signal, which is a high frequency component from the LOG type high frequency signal lines 82, is significantly reduced.

Further, the LOG type reference signal line 80 and the plurality of LOG type high frequency signal lines 82 are formed to overlap each other with the gate insulating film 92 interposed therebetween. At this time, the LOG type high frequency signal lines 82 have the same width and height, and each LOG type high frequency signal lines 82 are formed to maintain the same interval as the adjacent LOG type high frequency signal lines 82. Accordingly, the LOG high frequency signal lines 82 satisfy Equation 1, and their respective impedances Z are equal.

Accordingly, signal interference and electromagnetic shielding (hereinafter referred to as "EMI") between the LOG data signal lines can be prevented.

Meanwhile, the LOG type low frequency signal line which supplies the low frequency signal among the second LOG type data signal lines 92 is also the LOG type reference signal lines 80 and the gate insulating film 92 together with the LOG type high frequency signal line 82. It may be formed so as to satisfy the equation (1) with the gap therebetween.

Further, in the present invention, the first LOG data signal lines are formed of the same gate metal as the gate lines, and the second LOG data signal lines are formed of the same data metal as the data lines. The lines may be formed of data metal, and the second LOG data signal lines may be formed of the same metal as the pixel electrode.

As described above, the LOG type liquid crystal display according to the present invention is formed by insulated overlapping of the first LOG type signal line supplied by the reference voltage and the second LOG type signal line supplying the driving signal including the high frequency component. . In addition, each of the second LOG type signal lines is formed to maintain the same impedance. Accordingly, EMI from the second LOG signal lines is bypassed to the first LOG signal lines, thereby reducing EMI.

In addition, since the electromagnetic shielding layer is formed outside the second LOG signal line, EMI signals from the second LOG signal lines are bypassed, thereby reducing EMI.

In addition, since the gate PCB and the data PCB are removed, the liquid crystal display device can be thinned.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (10)

A liquid crystal panel having a plurality of gate lines and a plurality of data lines; A plurality of data integrated circuits for supplying pixel data voltages to the data lines; A first signal line formed on a substrate of the liquid crystal panel and connected between the data integrated circuits to transmit a first driving signal to the data integrated circuits; A plurality of second signal lines formed to overlap the first signal line and connected between the data integrated circuits to transmit second driving signals to the data integrated circuits; And the first signal line and the second signal line overlap each other with an insulating film formed on the substrate therebetween. The method of claim 1, And the second signal line transmits a signal having a high frequency component. The method of claim 2, And the second signal line transmits at least one of a data and a clock signal. The method of claim 1, And the first signal line supplies at least one of a ground power source and a digital power source. The method of claim 1, And wherein each of the second signal lines has the same width and height and maintains the same spacing as the adjacent second signal lines. The method of claim 1, The first signal lines are formed of the same metal as the gate line, And the second signal lines are formed of the same metal as the data lines. The method of claim 1, And a shielding layer formed adjacent to the second signal lines, the shielding layer being adjacent to the plurality of second signal lines. The method of claim 7, wherein And one of a ground power source and a digital power source is applied to the shielding layer. The method of claim 1, A gate integrated circuit supplying a gate signal to the gate line; And a third signal line formed on the liquid crystal panel to supply driving signals required by the gate integrated circuit. The method of claim 1, A power supply unit generating a power signal for driving the data integrated circuit; And a timing controller for generating a data control signal for controlling the data integrated circuit.