KR20040056434A - Method for manufacturing a semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to improve stability of patterning a gate electrode of a CMOS(complementary metal oxide semiconductor) semiconductor device by preventing a source/drain region from being deteriorated and by guaranteeing a characteristic of the semiconductor device. CONSTITUTION: NMOS and PMOS gate electrodes(110,112) are formed on a semiconductor substrate(100) in which NMOS and PMOS regions are defined. Photoresist is formed on the resultant structure to cover the NMOS and PMOS gate electrodes. The photoresist is etched to expose the upper part of the NMOS and PMOS gate electrodes. A barrier layer is formed on the resultant structure to cover the NMOS and PMOS gate electrodes. The upper part of the NMOS gate electrode is exposed by an etch process using a mask whose NMOS region only is open. N¬+ ions are implanted into the exposed NMOS gate electrode. After the barrier layer and the photoresist are eliminated, a source/drain ion implantation process is performed to form a source/drain region in the semiconductor substrate exposed to both sidewalls of the NMOS and PMOS gate electrodes.

Description

Method for manufacturing a semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate electrode of a high density CMOS (Complementary Metal-Oxide-Semiconductor) semiconductor device.

A circuit for driving a semiconductor element is generally composed of a switching element, a capacitor, a resistor, or the like, which is composed of a transistor. Logic gate devices in a circuit include a complementary metal-oxide-semiconductor (CMOS) transistor that consists of an N-type MOS (NMOS) and a P-type MOS (PMOS) transistor on the same semiconductor substrate. More and more used than PMOS transistors.

This is because the output logic level, power dissipation, transition time, or precharge characteristics are relatively excellent. Typically, a CMOS transistor is an NMOS transistor having a high concentration N-type source / drain region on a P-type bulk and a gate electrode formed through a gate oxide film on a channel, and an N-type bulk ( It is formed of a PMOS transistor having a high concentration P-type source / drain region on the N-type bulk and a gate electrode formed through a gate insulating film on the channel.

Recently, in the case of manufacturing a CMOS transistor using a sub micron design rule, a lightly doped drain (LDD) junction is formed to improve the reliability of each of the NMOS and PMOS transistors. In addition, an n + doped polysilicon film is used as the gate electrode material of the NMOS, and a p + doped polysilicon film is used as the gate electrode material of the PMOS. This is to improve the short channel effect by forming both channels of the NMOS and PMOS transistors as surface channels.

1A to 1C are cross-sectional views illustrating a method of manufacturing a dual gate electrode of a conventional CMOS device. Here, the same reference numerals among the reference numerals shown in FIGS. 1A to 1C indicate the same components having the same function.

Referring to FIG. 1A, after forming a device isolation layer 12 by performing a shallow trench isolation (STI) process to define the P-type semiconductor substrate 10 as an NMOS region and a PMOS region, 'p ⁻ ' impurities are formed in the NMOS region. implanting the boron (boron) to form a P- well (P-well) and, PMOS region has 'n ^-' by implanting phosphorus (phosphorous) impurity to form the N- well (N-well).

Referring to FIG. 1B, a gate oxide film 14 is formed on an entire structure, and a polysilicon film 16 for a gate electrode is formed thereon. Subsequently, after forming the photoresist pattern 18 in the PMOS region so that the NMOS region is opened, the photoresist pattern 18 is used as a mask, and an 'n ⁺ ' ion implantation process (hereinafter referred to as 'pretreatment ion implantation') is performed. Process ”) to dope the polysilicon film 16 in the NMOS region with phosphorus ions.

Referring to FIG. 1C, a predetermined photoresist strip process is performed to remove the photoresist pattern 18, followed by an etching process using a mask for a gate electrode pattern to sequentially process the polysilicon layer 16 and the gate oxide layer 14. The NMOS gate electrode 20 is formed in the NMOS region and the PMOS gate electrode 22 is formed in the PMOS region.

As described above, in order to improve the doping efficiency of the NMOS gate electrode in the NMOS region, a pretreatment process of a patterning process for forming the NMOS gate electrode includes 'n ⁺ ' ions (for example, phosphorus) only in the polysilicon film of the NMOS region. A pretreatment ion implantation step is performed. Subsequently, a source / drain ion implantation process is performed on the PMOS region and the NMOS region, respectively, to implant ions into the region where the NMOS gate electrode, the PMOS gate electrode, and the source / drain region are to be formed.

However, the process of performing the pretreatment ion implantation process only on the NMOS gate electrode, as shown in FIG. 1C, causes various problems. First, a problem arises in that a critical dimension (CD) of the NMOS gate electrode and the PMOS gate electrode is different from each other in the patterning process for forming the gate electrode. This is because the etch rate of the NMOS gate electrode is higher than that of the PMOS gate electrode in which ions are not implanted, as the 'N ⁺ ' ions are previously injected into the NMOS gate electrode. As described above, as the etch rate of the NMOS gate electrode increases, the threshold dimension N-CD of the NMOS gate electrode becomes smaller than the threshold dimension P-CD of the PMOS gate electrode, and the profile becomes smaller. In general, the critical dimension (N-CD) of the NMOS gate electrode is 0.152 占 퐉, and the critical dimension (P-CD) of the PMOS gate electrode is 0.160 占 퐉. Second, when the etching rate of the polysilicon film in the NMOS region is faster and the semiconductor substrate on the NMOS gate side is exposed to the etching gas faster than the semiconductor substrate on the PMOS gate side, the gate oxide film of the semiconductor substrate does not sufficiently protect it. A trench such as is formed.

Accordingly, the present invention has been made to solve the above-described problems of the prior art, and omits the pretreatment ion implantation process performed on the gate electrode of the NMOS region, and additionally implants only the NMOS gate electrode region after NMOS gate electrode patterning. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device capable of performing the process to secure the characteristics of the semiconductor device and to solve the problems occurring during patterning of the gate electrode.

1A to 1C are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the prior art.

2A through 2N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10, 100: semiconductor substrate 12, 102: device isolation film

14, 104: gate oxide film 16, 106: polysilicon film

20, 110: NMOS gate electrode 22, 112: PMOS gate electrode

114: photoresist 116: barrier layer

122, 126: low concentration junction region 128: LDD spacer

132, 136: high concentration junction region

18, 108, 118, 120, 124, 130, 134: photoresist pattern

According to an aspect of the present invention, forming an NMOS gate electrode and a PMOS gate electrode on a semiconductor substrate defined as an NMOS region and a PMOS region, respectively, and covering the NMOS gate electrode and the PMOS gate electrode over an entire structure. Applying a photoresist, etching the photoresist to expose the top of the NMOS gate electrode and the PMOS gate electrode, and forming a barrier layer over the entire structure to cover the NMOS gate electrode and the PMOS gate electrode. Forming an upper surface of the NMOS gate electrode by performing an etching process using a mask that opens only the NMOS region, and implanting n ⁺ ions into the NMOS gate electrode exposed in the step; After removing all of the barrier layer and the photoresist, a source / drain ion implantation process is performed. Forming a source / drain region in the semiconductor substrate exposed by both sidewalls of the NMOS gate electrode and the PMOS gate electrode.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention and to those skilled in the art. It is provided for complete information.

2A through 2N are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with a preferred embodiment of the present invention. The same reference numerals among the reference numerals shown in FIGS. 2A to 2N indicate the same elements having the same functions.

Referring to FIG. 2A, a device isolation layer 102 is formed by performing a shallow trench isolation (STI) process to define the P-type semiconductor substrate 100 as an NMOS region and a PMOS region. Then, NMOS region 'p ^{-' -} N- well by injecting a (phosphorous) impurities impurities, and by implanting boron (boron) to form a P- well (P-Well), PMOS region has 'n' (N-Well) is formed.

2B and 2C, the gate oxide film 104 is formed on the entire structure, and then the polysilicon film 106 for the gate electrode is formed thereon. Subsequently, after forming the photoresist pattern 108 for the gate electrode pattern, an etching process using the photoresist pattern 108 is performed to form the NMOS gate electrode 110 in the NMOS region, and the PMOS gate electrode (in the PMOS region). 112).

Referring to FIG. 2D, a photoresist 114 is applied over the entire structure. At this time, the photoresist 114 is deposited using a spin on coating (spin on coating) method to a thickness of 3000 to 10000 Å, preferably deposited to a thickness of 5000 Å. In addition, the photoresist 114 is preferably applied so that the viscosity is sufficiently low during spin-on coating so that there is no step between the active region and the gate electrodes 110 and 112.

Referring to FIG. 2E, an etching process is performed by using a blanket or etch back method using a plasma asher, which is a dry apparatus, without an etching mask, thereby exposing upper portions of the gate electrodes 110 and 112. . In this case, the photoresist 114 may be etched during the etching process to expose the upper portions of the gate electrodes 110 and 112, but the photoresist 114 may remain thick in the active region. For example, during the etching process, the gate electrodes 110 and 112 may be exposed to about 100 to 500 kV from the top.

Referring to FIG. 2F, a barrier layer 116 is applied over the entire structure. In this case, an anti-reflection coating (ARC) film or a low temperature oxide (LTO) film is used as the barrier layer 116. For example, when the barrier layer 116 is formed using an ARC film, a spin on coating method is used. On the other hand, when the barrier layer 116 is formed using an LTO film, a plasma method is used, and the plasma method is performed at 120 to 180 ° C. using SiH ₄ and N ₂ O or SiH ₄ and N ₂ gases. Conduct.

Referring to FIG. 2G, the photoresist pattern 118 is formed only in the PMOS region so that the NMOS region is opened. Then, an etching process using the photoresist pattern 118 as an etching mask is performed to etch the barrier layer 116 remaining on the NMOS gate electrode 110 in the NMOS region to form an NMOS gate electrode such as '150'. The top of 110 is exposed. Also in this case, the gate electrodes 110 and 112 are exposed to about 100 to 500 mV from the top.

Referring to FIG. 2H, the 'n ⁺ ' ion implantation process is performed only on the NMOS region using the photoresist pattern 118 as an ion implantation mask. In this case, the 'n ⁺ ' ion implantation process uses phosphorus or arsenic (As) ions. As a result, phosphorus or arsenic (As) is implanted only into the NMOS gate electrode 110 opened in FIG. 2G.

Referring to FIG. 2I, a strip process is performed to remove the photoresist pattern 118. Then, an etching process is performed to sequentially remove the barrier layer 116 and the photoresist 114. As a result, both the gate electrodes 110 and 112 and the active region are exposed.

Referring to FIG. 2J, the photoresist pattern 120 is formed only in the PMOS region so that the NMOS region is opened, and then an 'n ⁻ ' ion implantation process using the photoresist pattern 120 is performed to form the P-well of the NMOS region. The lightly-concentrated junction region 122, which is a shallow junction, is formed on the substrate. Thereafter, the photoresist pattern 120 is removed by performing a strip process.

Referring to FIG. 2K, the photoresist pattern 124 is formed only in the NMOS region to open the PMOS region, and then a 'p ⁻ ' ion implantation process using the photoresist pattern 124 is performed to form an N-well in the PMOS region. The low concentration junction region 126 is formed in the shallow junction region. The photoresist pattern 124 is removed by performing a strip process.

Referring to FIG. 2L, in order to function as an ion implantation mask during LDD (Lightly Doped Drain) ion implantation processes on both sidewalls of the NMOS gate electrode 110 and the PMOS gate electrode 112 by sequentially performing a deposition process and an etching process. LDD spacer 128 is formed. In this case, the LDD spacer 128 is formed using high temperature low pressure dielectric (HLD).

Referring to FIG. 2M, the photoresist pattern 130 is formed only in the PMOS region so that the NMOS region is opened, and then an 'n ⁺ ' ion implantation process using the photoresist pattern 130 is performed to form the P-well of the NMOS region. The high concentration junction region 132, which is a deep junction region, is formed in the gap. Thereafter, the photoresist pattern 130 is removed by performing a strip process.

Referring to FIG. 2N, the photoresist pattern 134 is formed only in the NMOS region to open the PMOS region, and then a 'p ⁺ ' ion implantation process using the photoresist pattern 134 is performed to form an N-well in the PMOS region. The high concentration junction region 136 is formed in the deep junction region. Thereafter, a strip process is performed to remove the photoresist pattern 136. As a result, an NMOS source / drain region including a low concentration junction region 122 and a high concentration junction region 132 is formed in the P-well of the NMOS region, and a low concentration junction region 126 and a high concentration junction region are formed in the N-well of the PMOS region. A PMOS source / drain region consisting of 136 is formed.

Although the technical spirit of the present invention described above has been described in detail in a preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In particular, the pretreatment ion implantation process performed according to the preferred embodiment of the present invention is applied only to the NMOS gate electrode, but this may be applied to the PMOS gate electrode as it is. In addition, the present invention will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, in the present invention, the pre-treatment ion implantation step performed on the gate electrode of the NMOS region before the gate electrode patterning is omitted, and after the NMOS gate electrode patterning, the ion implantation process is additionally performed only on the NMOS gate electrode region. It is possible to prevent the deterioration of the source / drain regions caused by the semiconductor device to secure the characteristics of the semiconductor device and to solve the problem occurring during the gate electrode patterning. Accordingly, it is possible to increase the stability of the patterning of the gate electrode in the CMOS semiconductor device manufacturing process and ultimately improve the productivity.

Claims (6)

(a) forming an NMOS gate electrode and a PMOS gate electrode on a semiconductor substrate defined by an NMOS region and a PMOS region, respectively; (b) applying photoresist over the entire structure to cover the NMOS gate electrode and the PMOS gate electrode; (c) etching the photoresist to expose the top of the NMOS gate electrode and the PMOS gate electrode; (d) forming a barrier layer over the entire structure to cover the NMOS gate electrode and the PMOS gate electrode; (e) exposing an upper portion of the NMOS gate electrode by performing an etching process using a mask in which only the NMOS region is opened; (f) implanting n ⁺ ions into the NMOS gate electrode exposed in step (e); And (g) forming a source / drain region on the semiconductor substrate exposed by both sidewalls of the NMOS gate electrode and the PMOS gate electrode by performing a source / drain ion implantation process after removing the barrier layer and the photoresist. A method for manufacturing a semiconductor device comprising the. The method of claim 1, The photoresist is a semiconductor device manufacturing method characterized in that the coating by applying a thickness of 3000 to 10000Å using a spin on coating method. The method of claim 1, The etching process performed in the step (c) may be performed by a blanket or etch back method without an etching mask, and the NMOS gate electrode or the PMOS gate electrode may be exposed to about 100 to 500 m from the top. Manufacturing method. The method of claim 1, The barrier layer is a method for manufacturing a semiconductor device, characterized in that the ARC film or LTO film. The method of claim 4, wherein The ARC film is a semiconductor device manufacturing method characterized in that formed by using a spin on coating method. The method of claim 4, wherein The LTO film is formed using a plasma method, the plasma method is a semiconductor device manufacturing method, characterized in that carried out at 120 to 180 ℃ using SiH ₄ and N ₂ O or SiH ₄ and N ₂ gas.