KR20040038163A - Method for manufacturing full cmos sram cell - Google Patents

Abstract

PURPOSE: A method for manufacturing a full CMOS SRAM cell is provided to be capable of effectively restraining the leakage current of an access transistor. CONSTITUTION: Gates(120) of an access and driver transistor are formed on a semiconductor substrate(100). An anti-diffusion gate is formed. An LDD(Lightly Doped Drain)(160) is formed in the substrate by first ion-implantation. A gate spacer(180) is formed at both sidewalls of the gates and an anti-diffusion spacer(190) is formed. A gate edge junction region(210) with shallow depth and a node contact junction region with deep depth are formed by second ion-implantation using the gate spacer and the anti-diffusion spacer as a mask.

Description

Manufacturing method of full CMOS SRAM cell {METHOD FOR MANUFACTURING FULL CMOS SRAM CELL}

The present invention relates to a method for manufacturing a full CMOS SRAM cell, and more particularly, to a method for manufacturing a full CMOS SRAM cell capable of reducing leakage current of an access transistor.

Static random access memory (SRAM) is a volatile memory device such as dynamic random access memory (DRAM), and together with DRAM, forms a mainstream of semiconductor memory devices. In general, an SRAM includes one cell including two access transistors, two driver transistors, and two load transistors.

As such, since the SRAM is composed of a plurality of transistors, the density of the SRAM is inferior to that of the DRAM having one transistor and a capacitor. SRAM, on the other hand, has fast operating speed and low power consumption, and thus is mainly used as a cache memory of a CPU.

In particular, as a prerequisite for low power, high speed SRAM devices of 0.14 mu m or less, it is necessary to reduce the leakage current of the transistor. To this end, it is necessary to determine appropriate threshold voltages, reduce variations, and optimize junction implant conditions in the method of manufacturing full CMOS SRAM cells.

Here, the dose or energy increase of the junction implant increases the leakage depth by increasing the junction depth, and thus the dose and energy need to be minimized as long as the device characteristics allow.

In addition, the junction depth is preferably maintained at a sufficient depth so that the contact leakage is sufficiently small at the site where the contact is formed. On the other hand, at the gate edge of the transistor, it is ideal to make the junction depth shallow enough so that the leakage current of the transistor is sufficiently small.

FIG. 1 illustrates a planar view of an n + node region in a conventional full CMOS SRAM cell, in which a polysilicon layer 12 and a gate spacer 18 are formed in an active region A of a substrate 10. It can be seen.

The cross-section of the line I-I of FIG. 1 is formed by the method of manufacturing a full CMOS SRAM cell according to the prior art as follows.

According to the related art, a method of manufacturing a full CMOS SRAM cell, as illustrated in FIG. 2, may include a gate 12 and an oxide layer 14 as a deposition / etching process and an oxidation process of polysilicon in an active region of a silicon substrate 10. ).

Subsequently, as shown in FIG. 3, an LDD (16; lightly doped drain) is formed on the substrate 10 below the side of the gate 12 by an ion implantation process (LDD implant) using the gate 12 as a mask. do.

Next, as shown in FIG. 4, a gate spacer 18 is formed on the side of the gate 12, and then an ion implantation process (n + S / D) using the gate 12 and the gate spacer 18 as a mask. Implant) to form a junction region 20.

On the other hand, the manufacturing method of the full CMOS SRAM device according to the prior art has the following problems.

In the prior art, when the junction region is formed by an ion implantation process (n + S / D implant), when the junction depth becomes too low or the impurity concentration generated by the implant becomes too low, in the subsequent metal contact process, Silicon loss due to etching, silicon loss due to silicidation of a barrier metal, and the like occur. As a result, there is a problem that contact leakage increases.

In order to solve this problem, when the junction depth is deepened, the increase in contact leakage is suppressed, but there is a problem that the leakage current at the gate edge side of the transistor increases. In addition, in the process technology of 0.14㎛ or less, since the implant energy is already close to the minimum allowable energy considering the productivity of the implant equipment, there is a practical problem that a separate method other than the implant conditions should be found.

Accordingly, the present invention has been made to solve the above-mentioned problems in the prior art, an object of the present invention is to form a diffusion suppression spacer in the junction region of the access transistor of the full CMOS SRAM cell to form impurities in the junction region. The present invention provides a method of manufacturing a full CMOS SRAM cell capable of reducing the leakage current of an access transistor by reducing the concentration and depth.

1 is a plan view of an n + node region of a full CMOS SRAM cell according to the prior art;

2 to 4 is a cross-sectional view for each process showing a method for manufacturing a full CMOS SRAM cell according to the prior art.

5 to 7 is a cross-sectional view showing a process for manufacturing a full CMOS SRAM cell according to the present invention.

8 and 9 are cross-sectional views and graphs showing simulation results of changes in the joint implant window width and joint profile.

10 is a plan view of an n + node region of a full CMOS SRAM cell in accordance with the present invention.

11 is a layout diagram of a full CMOS SRAM cell according to the present invention.

Explanation of symbols on the main parts of the drawings

100; A semiconductor substrate 120; Access transistor gate

140; Oxide film 160; LDD

180; Gate spacer 190; Diffusion Suppression spacer

200; Node contact junction region 210; Gate edge junction area

220; Diffusion suppression gate 230; Driver transistor gate

A method for manufacturing a full CMOS SRAM cell according to the present invention for achieving the above object, in the method for manufacturing a full CMOS SRAM cell, forming an access and a driver transistor gate on a semiconductor substrate, In parallel to forming a diffusion suppression gate; Forming LDD on the substrate by first ion implantation; Forming a gate spacer on side surfaces of the gates, and forming a diffusion suppression spacer on the substrate in parallel with the gate spacers; And forming an access transistor gate edge junction region having a shallow depth and a low impurity concentration and a node contact junction region having a deep depth and a high impurity concentration by a second ion implantation using the gate spacer and the diffusion suppressing spacer as a mask. It is characterized by.

The diffusion suppressing spacer is formed of any one selected from oxide and nitride, and is formed in the middle portion of the n + node active region of the substrate.

According to the present invention, it is possible to effectively suppress the leakage current of the access transistor in a step of 0,14 µm or less.

Hereinafter, a method of manufacturing a full CMOS SRAM cell according to the present invention will be described in detail with reference to the accompanying drawings.

5 to 7 are cross-sectional views illustrating a method of manufacturing a full CMOS SRAM cell according to the present invention, and FIGS. 8 and 9 are cross-sectional views illustrating simulation results of changes in a joint implant window width and a joint profile. It is a graph.

10 is a plan view of an n + node region of a full CMOS SRAM cell according to the present invention, and FIG. 11 is a layout diagram of a full CMOS SRAM cell according to the present invention.

In the method of manufacturing a full CMOS SRAM cell according to the present invention, as illustrated in FIG. 5, an access transistor gate may be formed by, for example, deposition and etching of polysilicon on a semiconductor substrate 100 made of a semiconductor element such as silicon. An access transistor (120) and a driver transistor gate (not shown) are formed. In parallel with this, a diffusion suppression gate (not shown) is formed in the same process. In this case, an oxide film 140 is formed on the surface of the substrate 100 by an oxidation process.

Next, as shown in FIG. 6, the LDD 160, which is a low concentration impurity region, is formed in the substrate 100 by using a first ion implantation (LDD implant). In this case, for example, the first ion implantation proceeds using a pentavalent element such as phosphorus (P) or arsenic (As) to implement an access transistor as an NMOS.

Next, as shown in FIG. 7, a gate spacer 180 is formed on the side of the access transistor gate 120. In parallel with this, the diffusion suppression spacer 190 is formed of oxide or nitride on the substrate 100 under the side of the access transistor gate 120.

The diffusion suppression spacer 190 is formed at an intermediate portion of an n + node active region of the substrate 100.

Next, the junction regions 200 and 210 are formed using a second ion implantation (n + S / D implant) using the gate spacer 180 and the diffusion suppression spacer 190 as a mask. The junction regions 200 and 210 formed at this time may include an access and driver transistor gate edge junction 210 having a shallow depth and a low impurity concentration, and a node contact junction having a deep depth and a high impurity concentration. It is an area 200 (Node Contact Junction).

Simulation results of the change in the junction profile due to the difference in the window width of the junction implant are as follows.

As shown in FIG. 8, n + ions when the gates 810 are formed on both sides of the substrate 800, and the spacings W between the gates 810 are 1.0 / 0.44 / 0.29 / 0.20 μm, respectively. Injection was performed. The thickness of the gate spacer 820 at this time is 0.09 micrometer.

FIG. 9 illustrates the n + impurity concentration profile for each depth at the exact center position of the junction region 830. It can be seen that the concentration decreases when the distance W between the gates 810 is 0.22 μm or less. At this time, the junction depth is also reduced by offsetting with the p-type concentration.

The present invention utilizes the phenomenon of decreasing the implant concentration and the junction depth according to the shrinkage of the implant window. That is, as shown in FIG. 7, after the gate spacer 180 is formed by the diffusion suppressing spacer 190, the implant window of the second ion implantation (n + S / D implant) is reduced. When the implant window is small, diffusion by implants and subsequent thermal processes will change from planar type diffusion to spherical or cylindrical type diffusion. Therefore, even if the implant and subsequent thermal process conditions are the same, the final junction depth and concentration will decrease as the size of the implant window becomes smaller. This can be seen from FIG. 9.

Accordingly, the n + impurity concentration and junction of the junction region 210, that is, the access transistor gate edge junction region 210 formed by the diffusion suppression spacer 190 on the edge of the gate 120 of the access transistor, are formed. Depth is reduced. In addition, for the same reason, the n + impurity concentration and junction depth of the driver transistor gate edge junction region also decrease.

On the other hand, the junction 200 in which the node contact is formed, that is, the node contact junction 200, is equal to the concentration and depth of the conventional n + junction region.

As a result, the effective channel length of the access transistor increases, so that the leakage current decreases when the access transistor is in an off state. On the other hand, since the node contact junction region 200 is not affected by this, the contact leakage current does not increase.

Since the junction region is bisected by the diffusion suppressing spacer 190, electrical connection of the near ear can be possible by the LDD 160 formed by the first ion implantation (LDD implant). In this case, sufficient consideration is required in setting the size and position of the diffusion suppressing spacer 190 so that the junction resistance does not increase. In addition, since the effective window may vary due to the profile difference of the diffusion suppressing spacer 190, careful consideration thereof is also required.

10 illustrates an enlarged n + node region, in which an access transistor gate 120, a driver transistor gate 230, a diffusion suppression gate 220, and a diffusion suppression spacer 190 are illustrated.

FIG. 11 is a layout of a full CMOS CMOS cell fabricated according to the present invention, and an active region B, an access transistor gate 120, a driver transistor gate 220, and a diffusion on a substrate 100. The suppression spacer 190 is shown schematically. Reference numeral 300 denotes a metal contact.

Various embodiments can be easily implemented as well as self-explanatory to those skilled in the art without departing from the principles and spirit of the present invention. Accordingly, the claims appended hereto are not limited to those already described above, and the following claims are intended to cover all of the novel and patented matters inherent in the invention, and are also common in the art to which the invention pertains. Includes all features that are processed evenly by the knowledgeable.

As described above, according to the method of manufacturing the full CMOS SRAM cell according to the present invention, since the leakage current of the access transistor can be effectively suppressed in a process of 0,14 µm or less, it is expected to improve the performance of low power products. .

Claims (5)

In the method of manufacturing a full CMOS SRAM cell, Forming access and driver transistor gates on the semiconductor substrate, and in parallel forming diffusion suppression gates; Forming LDD on the substrate by first ion implantation; Forming a gate spacer on side surfaces of the access transistor gate and the driver transistor gate, and forming a diffusion suppression spacer on the substrate in parallel with the gate transistor; And Forming a shallow depth and low impurity access and driver transistor gate edge junction region with a second ion implantation using the gate spacer and the diffusion suppression spacer as a mask, and a node contact junction region having a deep depth and high impurity concentration; Method for producing a full CMOS SRAM cell, characterized in that. The method of claim 1, The diffusion suppressing spacer is a method of manufacturing a full CMOS SRAM cell, characterized in that formed by any one selected from oxide and nitride. The method of claim 1, And the diffusion suppressing spacer is formed at an intermediate portion of the n + node active region of the substrate. The method of claim 1, The first ion implantation method of manufacturing a full CMOS SRAM cell, characterized in that using a pentavalent element. The method of claim 4, wherein The pentavalent element is a method for producing a full CMOS SRAM cell, characterized in that any one of phosphorus (P) and arsenic (As).