JPH11135751A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form plural kinds of transistors of different characteristics at a peripheral circuit part. SOLUTION: A memory cell transistor is provided with a first channel ion- implanted layers 9, which is obtained by implanting boron for forming a channel- stopper layer under LOCOS film 4 at a deep position under a channel region, and second and third channel ion-implanted layers 9 and 11, which are obtained by injecting boron under the channel region on different implanting condition. The first transistor of a peripheral circuit part is provided with a first channel ion-implanted layer 8, which is obtained by implanting boron for forming the channel-stopper layer at a deep position under a channel region and a second channel ion-implanted layer 9, which is obtained by implanting boron for under a channel region. In addition, at a second transistor of the peripheral circuit part, boron for forming a channel-stopper layer is injected only under the film 4 and second and third channel ion-implanted layers 9 and 11 are provided under a channel region similarly under the channel region of the memory central transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a technique for reducing a substrate bias effect or reducing a substrate current, which is a problem in miniaturizing a chip size of a dynamic RAM. About.

[0002]

2. Description of the Related Art As a conventional technique for miniaturizing the chip size of such a dynamic RAM, for example, there is a method of reducing a gate length of a memory cell portion. In this case, an ion implantation layer for suppressing a short channel effect (see a first channel ion implantation layer 58 shown in FIG. 9) is provided below the channel region of the memory cell portion.

Hereinafter, a conventional method for manufacturing a semiconductor device will be described with reference to the drawings. First, as shown in FIG. 7, a semiconductor substrate 51 of one conductivity type, for example, a P type (memory cell transistor formation region A formed in a memory cell portion, first and second transistors formed in a peripheral circuit portion) Regions B and C are formed.) A pad oxide film 52 and a silicon nitride film 53 are stacked so as to have an opening on a region where a LOCOS oxide film 54 as an element isolation film described later is formed, as shown in FIG. The oxide film 52 and the silicon nitride film 5
By using the mask 3 as a mask, the surface layer of the substrate is thermally oxidized by the LOCOS method to form a LOCOS oxide film 54.

Then, the silicon nitride film 53 and the pad oxide film 52 are removed by etching using the LOCOS oxide film 54 as a mask. Then, as shown in FIG. 9, the substrate is thermally oxidized to form a scatter oxide film 55 on a channel formation region other than the LOCOS oxide film 54, and then the first and second scatter oxide films 55 formed on the peripheral circuit portion are formed. Using the photoresist film 56 formed on predetermined regions of the transistor forming regions B and C as masks, LOCOS oxide film 54 of boron ion (11B +) as one conductivity type, for example, a P-type impurity is used.
Inject below and deep below the channel region. Thus, the ions implanted under the LOCOS oxide film 54 form a channel stopper layer 57 for preventing inversion, and the ions implanted deep below the channel region are the first channel ions for suppressing the short channel effect. An injection layer 58 is formed.

Subsequently, as shown in FIG. 10, boron ions (11B +) are implanted below the channel region to form a second channel ion implantation layer 59 for adjusting the threshold voltage of the N-channel MOS transistor. I do. Further, in order to make the threshold voltage of the memory cell transistor formation region A higher than the threshold voltages of the first and second transistor formation regions B and C formed in other peripheral circuit portions, FIG. After the photoresist film 60 is formed on the first and second transistor forming regions B and C as described above, boron ions (11B +) are only applied to the channel region of the memory cell transistor forming region A using the resist film 60 as a mask. The third channel ion implantation layer 61 is formed by implantation.

Next, as shown in FIG. 12, the memory cell transistor forming region A formed in the memory cell portion and the first and second transistor forming regions B and C formed in the peripheral circuit portion are formed on the channel regions. To form a MOS transistor, first, the scatter oxide film is removed, a gate oxide film is formed, and then a first gate electrode 62A, a second gate electrode 62B, and a third gate electrode 62C are formed. Phosphorus ions (31P +) are implanted into the surface of the substrate as an N-type impurity so as to be adjacent to the ends of the gate electrodes 62A, 62B and 62C, so that the first source
Drain diffusion layers 63 and 64 are formed. Subsequently, after an oxide film is formed on the entire surface so as to cover the first, second, and third gate electrodes 62A, 62B, and 62C, anisotropic etching is performed, and as shown in FIG. A side wall spacer film 65 integrated with the gate oxide film is formed on the side wall portions of the second and third gate electrodes 62A, 62B, 62C. Then, after a photoresist film (not shown) is formed on the memory cell formation region A, the first and second transistor formation regions B and C formed in the peripheral circuit portion are formed using the photoresist film as a mask. , Arsenic ions (75As +) are implanted into the surface of the substrate as N-type impurities,
Second source / drain diffusion layers 66 and 67 are formed.
Thus, the first and second transistors formed in the peripheral circuit have an LDD structure.

As described above, the threshold voltage of the memory cell transistor formation region A is determined by the boron ion (11B
+) Is injected twice so as to be set higher than the threshold voltages of the other first and second transistor formation regions B and C, and formed in the memory cell transistor formation region A as shown in FIG. The gate length L1 of the gate electrode 62A is shorter than the gate length L2 of the gate electrode 62B formed in the first transistor formation region B of the peripheral circuit portion and the gate length L3 of the gate electrode 62C formed in the second transistor formation region C. Was able to reduce the chip size.

The gate length GL of the gate electrode 62C formed in the second transistor formation region C of the peripheral circuit portion
Is made longer than the gate length GL of the gate electrode 62B formed on the first transistor formation region B, so that two types of transistors adapted to different working voltages are formed in the same manufacturing process.

[0009]

However, in the above-described process, both the memory cell transistor formation region A and the first and second transistor formation regions B and C have the first channel ion implantation layer 58 for suppressing the short channel effect. Is formed, thereby increasing the substrate concentration, resulting in a problem that the substrate bias effect increases.

The substrate bias effect is obtained by applying a voltage to a semiconductor substrate on which a transistor is formed.
This means that the threshold voltage of the transistor changes. Since the threshold voltage is proportional to the square root of the substrate bias voltage, when the absolute value of the substrate bias potential increases,
For example, when the potential of the source electrode in the output transistor is high, there is a problem that the threshold voltage increases.
That is, at the time of the High level output, the High level is supplied to the source electrode of the output transistor, so that the potential difference between the source and the substrate of the output transistor becomes large. Therefore, in a transistor having a large substrate bias effect, the potential transmitted to the drain electrode is reduced by the threshold voltage, so that the smaller the substrate bias effect, the more stable the High level can be supplied. For the cause and problem of such a substrate bias effect, for example,
JP-A-6-45435 and JP-A-5-190781
No. 6,009,036.

[0011] Similarly, problems such as an increase in substrate current and deterioration of hot carrier resistance occur. For this reason, if the inside of the LSI is uniformly formed of the transistor having the above structure, the above problem has led to a decrease in the margin of the LSI characteristics. Therefore, an object of the present invention is to provide a semiconductor device in which transistors having a plurality of types of characteristics are formed without increasing the number of manufacturing steps, and a method for manufacturing the same.

[0012]

Therefore, in the semiconductor device according to the present invention, a memory cell transistor formed in a memory cell portion is formed under a LOCOS oxide film 4 for forming a channel stopper layer 7. The first channel ion implanted layer 8 in which an impurity of one conductivity type is implanted deep below the channel region, and the second and third channel ions in which impurities of one conductivity type are implanted under different implantation conditions under the channel region. The first transistor formed in the peripheral circuit portion having the injection layers 9 and 11 has one conductivity type impurity for forming the channel stopper layer 7 formed below the LOCOS oxide film 4 at a deep position below the channel region. A second channel ion implanted layer having an implanted first channel ion implanted layer and an impurity of one conductivity type below the channel region; Is implanted only under the LOCOS oxide film 4 with an impurity of one conductivity type for forming the channel stopper layer 7 and at the same implantation condition as under the channel region of the memory cell transistor under the channel region. Second and third channel ion implantation layers 9, 1
1 is provided.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, a memory cell transistor formed in a memory cell portion and a first transistor and a second transistor formed in a peripheral circuit portion are separated from each other. Do LO
After forming a COS oxide film 4 and forming a photoresist film 6 on a predetermined region of the first transistor and on a second transistor formation region, LOCOS oxidation of impurities of one conductivity type is performed using the photoresist film 6 as a mask. The channel stopper layer 7 is formed under the LOCOS oxide film 4 in the memory cell transistor formation region, the first transistor formation region, and the second transistor formation region by ion implantation under the condition of penetrating the film 4 and forming the memory cell transistor. A first channel ion implantation layer 8 is formed at a deep position below the channel region of the region and the first transistor formation region. Next, after removing the photoresist film 6, an impurity of one conductivity type is implanted into the entire surface to form a second channel ion implanted layer under each channel region of the memory cell transistor, the first transistor, and the second transistor. 9 is formed. Subsequently, after forming a photoresist film 10 on the first transistor formation region, the photoresist film 1 is formed.
Forming a third channel ion-implanted layer 11 under each channel region of the memory cell transistor and the second transistor by implanting one conductivity type impurity using 0 as a mask. It is.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to an embodiment of the present invention and a method for manufacturing the same will be described with reference to FIGS. First, as shown in FIG. 1, a semiconductor substrate 1 of one conductivity type, for example, a P-type (memory cell transistor formation region A formed in a memory cell portion, first and second transistor formation regions formed in a peripheral circuit portion) B and C are formed.) The pad oxide film 2 is formed so as to have an opening on a LOCOS oxide film 4 forming region as an element isolation film described later.
After stacking the silicon nitride film 3, as shown in FIG. 2, using the oxide film 2 and the silicon nitride film 3 as a mask, the surface layer of the substrate is thermally oxidized by the LOCOS method to form a LOCOS oxide film 4 having a thickness of about 4500 °. I do.

Next, the silicon nitride film 3 and the pad oxide film 2 are etched using the LOCOS oxide film 4 as a mask. Then, as shown in FIG. 3, the substrate is thermally oxidized to form a scatter oxide film 5 having a thickness of about 400 ° on the channel forming region other than the LOCOS oxide film 4. Then, after a photoresist film 6 is formed on a predetermined region of the first transistor formation region B formed on the peripheral circuit portion and on the entire surface of the second transistor formation region C,
Using the photoresist 6 as a mask, one conductivity type, for example, P
Boron ion (11B +) as the type impurity
LOCOS under the memory cell transistor formation region A, the first transistor formation region B, and the second transistor formation region C under the condition of penetrating the S oxide film 4, under an acceleration voltage of approximately 140 KeV, and an injection amount of approximately 5 × 10 12 / cm 2. In addition to the implantation below the oxide film 4, the implantation is deep below the channel regions of the memory cell transistor formation region A and the first transistor formation region B. Thus, the ions implanted under the LOCOS oxide film 4 form a channel stopper layer 7 for preventing inversion, and the ions implanted deep below the channel region are the first channel ions for suppressing the short channel effect. An injection layer 8 is formed.

Subsequently, as shown in FIG.
Using the oxide film 4 as a mask, boron ions (11B @ +) are implanted under the channel region at an acceleration voltage of about 50 KeV and an implantation amount of about 3.times.10@11 / cm @ 2 to form an N-channel type MO.
A second channel ion implantation layer 9 for adjusting the threshold voltage of the S transistor is formed. Further, as shown in FIG. 5, after a photoresist film 10 is formed on a first transistor formation region B formed in the peripheral circuit section, a memory cell transistor A formed in the memory cell section and a peripheral circuit section are formed. Boron ions (11B +) are added under the channel region of the formed second transistor formation region C by about 50 Ke.
The third channel ion-implanted layer 11 is formed by implantation at an acceleration voltage of V and an implantation amount of about 9 × 10 11 / cm 2.
Thereby, the threshold voltages of the memory cell transistor formation region A formed in the memory cell portion and the second transistor formation region C formed in the peripheral circuit portion are respectively:
By implanting boron ions (11B +) twice, the first transistor forming region B formed in another peripheral circuit portion is formed.
Is set higher than the threshold voltage. Further, in the second transistor formation region C formed in the peripheral circuit portion, since the ion implantation for forming the first channel ion implantation layer is not performed as described above, the substrate concentration which has conventionally been a problem is reduced. It does not increase, and the substrate bias effect can be reduced.

Therefore, according to the present invention, by changing the combination of the manufacturing steps of the memory cell transistor and the transistor formed in the peripheral circuit section, the manufacturing steps are not increased, and the formation of the peripheral circuit section as shown in FIG. The first transistor formation region B and the second transistor formation region C can be separately formed. Therefore, the threshold voltage of the second transistor can be set to a desired threshold voltage. In particular, when an output transistor is formed in the second transistor formation region C, the output transistor has the above-described structure. By doing so, the High level can be output stably.

Further, problems such as an increase in substrate current and deterioration of hot carrier resistance can be solved. Next, as shown in FIG. 6, MOS transistors are formed on the channel regions of the memory cell transistor formation region A formed in the memory cell portion and the first and second transistor formation regions B and C formed in the peripheral circuit portion. First, the scatter oxide film is removed, a gate oxide film is formed, a first gate electrode 12A, a second gate electrode 12B, and a third gate electrode 12C are formed. First source / drain diffusion layers 13 and 14 are formed by implanting phosphorus ions (31P +) as an N-type impurity into the surface of the substrate so as to be adjacent to the ends of 12A, 12B and 12C. . Subsequently, the first,
After an oxide film is formed on the entire surface so as to cover the second and third gate electrodes 12A, 12B, and 12C, the first, second, and third gate electrodes are anisotropically etched as shown in FIG. A side wall spacer film 15 integrated with the gate oxide film is formed on the side walls of 12A, 12B and 12C. Then, after a photoresist film (not shown) is formed on the memory cell formation region A, the first and second transistor formation regions B and C formed in the peripheral circuit portion are formed using the photoresist film as a mask. Then, arsenic ions (75 As +) are implanted into the surface of the substrate as N-type impurities to form second source / drain diffusion layers 16 and 17. Thus, the first and second transistors formed in the peripheral circuit have an LDD structure.

At this time, in the gate electrode 12A formed on the memory cell transistor formation region A formed in the memory cell portion, the threshold voltage of this portion is formed in the peripheral circuit portion as in the conventional case. 1 transistor formation region B
Is set higher than the threshold voltage of the gate electrode 12B formed in the first transistor formation region B.
Even if the gate length is made shorter than that of the first embodiment, the leak current can be prevented. For example, an output transistor formed in the second transistor formation region C is different from a memory cell transistor formed in another memory cell transistor formation region A and a transistor formed in the first transistor formation region B. Since the ion implantation for forming the first channel ion implantation layer is not performed, the substrate concentration does not increase, and therefore, the substrate bias effect is small and Hi
gh level can be output stably. Further, it is possible to suppress the deterioration of the substrate bias voltage level caused by the substrate current of the output transistor.

Further, since the threshold voltage of the second transistor is reduced without forming the first channel ion-implanted layer, the threshold of the memory cell transistor in the memory cell transistor formation region A is reduced. By performing ion implantation for forming the third channel ion implantation layer for value voltage adjustment, a substantially desired threshold voltage is ensured. In this way, two types of transistors can be formed without increasing the number of steps where the number of steps would normally be increased.

Although not shown, a storage electrode and a dielectric formed on the first drain diffusion layer 14 of the memory cell transistor formed in the memory cell transistor formation region A shown in FIG. A semiconductor device is manufactured by forming a capacitor including a body film and a counter electrode facing the storage electrode via the dielectric film.

Although the description of the present invention is omitted, the CMO
The same applies to the S semiconductor device.

[0023]

As described above, according to the semiconductor device and the method of manufacturing the same of the present invention, two types of transistors can be formed without increasing the number of manufacturing steps. That is, conventionally, both the memory cell transistor formation region A and the first and second transistor formation regions B and C formed in the peripheral circuit portion form the first channel ion implantation layer for suppressing the short channel effect. This increases the substrate concentration, resulting in problems such as an increase in the substrate bias effect, an increase in the substrate current, and a deterioration in hot carrier resistance. Utilizing the formation process of the formation region A, two types of transistors, that is, the first and second transistor formation regions B and C formed in the peripheral circuit portion can be separately formed. Furthermore, when an output transistor is formed in the second transistor formation region C, a High level can be output stably.

Further, the deterioration of the substrate bias voltage level caused by the substrate current of the output transistor can be suppressed.

[Brief description of the drawings]

FIG. 1 is a first sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention;

FIG. 2 is a second cross-sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 3 is a third sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 4 is a fourth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a fifth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 6 is a sixth sectional view illustrating the method for manufacturing the semiconductor device according to one embodiment of the present invention;

FIG. 7 is a first cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 8 is a second cross-sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 9 is a third cross-sectional view showing a conventional method for manufacturing a semiconductor device.

FIG. 10 is a fourth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 11 is a fifth sectional view showing the conventional method for manufacturing a semiconductor device.

FIG. 12 is a sixth sectional view showing the conventional method for manufacturing a semiconductor device.

Claims (2)

[Claims] 1. A semiconductor device having a memory cell transistor formed in a memory cell portion on a semiconductor substrate of one conductivity type and first and second transistors formed in a peripheral circuit portion, wherein the memory cell transistor is an element An impurity of one conductivity type for forming a channel stopper layer formed below the isolation film is implanted at a deep position below the channel region, and an impurity of one conductivity type is formed under different implantation conditions under the channel region. The first transistor has an impurity of one conductivity type for forming a channel stopper layer formed under an element isolation film at a deep position below a channel region. A second channel ion-implanted layer in which an impurity of one conductivity type is implanted below the channel region; In this transistor, one conductivity type impurity for forming the channel stopper layer 7 is implanted only under the LOCOS oxide film 4 and one conductivity type impurity is implanted under the channel region under the same implantation conditions as under the channel region of the memory cell transistor. A semiconductor device having second and third channel ion-implanted layers into which is implanted. 2. A method of manufacturing a semiconductor device having a memory cell transistor formed in a memory cell portion on a semiconductor substrate of one conductivity type and first and second transistors formed in a peripheral circuit portion, wherein: Forming an element isolation film for element isolation of each of the cell transistor, the first transistor, and the second transistor;
After a photoresist film is formed on the transistor formation region of FIG. 1, an impurity of one conductivity type is ion-implanted under the condition of penetrating the element isolation film using the photoresist film as a mask, and the memory cell transistor formation region, the first transistor formation region, and Forming a channel stopper layer below the element isolation film in the second transistor formation region and forming a first channel ion implantation layer at a deep position below the memory cell transistor formation region and the channel region in the first transistor formation region; Removing the photoresist film and implanting an impurity of one conductivity type over the entire surface to form a second channel ion-implanted layer under each channel region of the memory cell transistor, the first transistor, and the second transistor. Forming a photoresist film on the first transistor formation region Forming a third channel ion-implanted layer under each channel region of the memory cell transistor and the second transistor by implanting one conductivity type impurity using the photoresist film as a mask. Manufacturing method of a semiconductor device.