KR20040036002A - Printed Circuit Substrate for use in a Semiconductor Package with Locking-Holes and Semiconductor Package using the Substrate - Google Patents
Printed Circuit Substrate for use in a Semiconductor Package with Locking-Holes and Semiconductor Package using the Substrate Download PDFInfo
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- KR20040036002A KR20040036002A KR1020020064747A KR20020064747A KR20040036002A KR 20040036002 A KR20040036002 A KR 20040036002A KR 1020020064747 A KR1020020064747 A KR 1020020064747A KR 20020064747 A KR20020064747 A KR 20020064747A KR 20040036002 A KR20040036002 A KR 20040036002A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
본 발명은 반도체 패키지에 사용되는 인쇄회로기판에 관한 것으로서, 특히 복수의 로킹-홀(Locking-holes)을 구비한 인쇄회로기판과, 상기 인쇄회로기판을 사용한 볼 그리드 어레이 반도체 패키지에 관한 것이다.The present invention relates to a printed circuit board for use in a semiconductor package, and more particularly, to a printed circuit board having a plurality of locking-holes, and a ball grid array semiconductor package using the printed circuit board.
일반적으로, 반도체 패키지에는 네방향 리드형 패키지(Quad Flat Package; 이하, 'QFP'라 함), 멀티 칩 모듈(Multi Chip Module; 이하, 'MCM'이라 함), 볼 그리드 어레이(Ball Grid Array; 이하, 'BGA'라 함) 반도체 패키지 등이 있다. 이러한 반도체 패키지 중에서, BGA 반도체 패키지가 다른 패키지에 비해 열저항 및 전기적 특성 등이 우수하여, 현재 주로 사용되고 있다.In general, a semiconductor package includes a four-way lead flat package (QFP), a multi chip module (MCM), and a ball grid array; Hereinafter referred to as 'BGA'. Among these semiconductor packages, the BGA semiconductor package is superior in heat resistance and electrical characteristics to other packages, and is currently mainly used.
그러면, 첨부한 도1 및 도2를 참조하여 종래 기술에 따른 인쇄회로기판과 이를 사용한 BGA 반도체 패키지에 대하여 간략히 설명한다. 도1을 참조하면, 기존의 반도체 패키지용 인쇄회로기판(10)은 비티 수지(BT Resin; BismaleimidetraizineResin)재로 형성된 기판 몸체(11)와, 기판 몸체(11)의 상면에 형성된 다이 패드(13)와, 기판 몸체(11)의 상하면에 형성된 회로선(15, 15')과, 상기 상하면의 회로선(15, 15')을 전기적으로 연결시키는 비아 홀(17)을 구비한다. 여기서, 상기 기판 몸체(11)의 하면에 형성된 회로선(15')에는 솔더볼이 부착되는 패드가 형성된다. 이러한 인쇄회로기판(10)의 상면 및 하면에는 다이 패드(13)와 회로선(15, 15')의 일부분을 보호하기 위한 솔더 레지스트(19)가 도포된다.Next, a printed circuit board according to the related art and a BGA semiconductor package using the same will be briefly described with reference to FIGS. 1 and 2. Referring to FIG. 1, a conventional printed circuit board 10 for a semiconductor package includes a substrate body 11 formed of a BT Resin (Bismaleimidetraizine Resin) material, a die pad 13 formed on an upper surface of the substrate body 11, and And via lines 17 electrically connecting the circuit lines 15 and 15 'formed on the upper and lower surfaces of the substrate body 11 and the circuit lines 15 and 15' on the upper and lower surfaces. Here, a pad to which solder balls are attached is formed on the circuit line 15 ′ formed on the bottom surface of the substrate body 11. Solder resists 19 are applied to the upper and lower surfaces of the printed circuit board 10 to protect the die pad 13 and a part of the circuit lines 15 and 15 '.
한편, 상기와 같은 기존의 인쇄회로기판(10)을 사용하는 종래 기술의 BGA 반도체 패키지(20)는, 도2에 도시된 바와 같이, 기판(10)과, 기판의 다이 패드(13)상에 실장된 반도체 칩(22)과, 상기 반도체 칩(22)을 기판 상면의 회로선(15)에 전기적으로 연결시키기 위한 골드 와이어(24)와, 기판 하면의 회로선(15')상에 형성된 패드에 각각 부착되는 다수의 솔더볼(26)을 구비한다. 또한, 이러한 BGA 반도체 패키지(20)는 기판 상면에 소정의 봉지재로 몰딩(One-Side Molding)하여 형성된 인캡슐레이션층(28)이 구비된다. 여기서, 상기 인캡슐레이션층(28)은 반도체 칩(22) 및 골드 와이어(24) 등을 외부 환경으로부터 보호한다.On the other hand, the conventional BGA semiconductor package 20 using the conventional printed circuit board 10 as described above, as shown in Figure 2, on the substrate 10 and the die pad 13 of the substrate A semiconductor chip 22 mounted, a gold wire 24 for electrically connecting the semiconductor chip 22 to the circuit line 15 on the upper surface of the substrate, and a pad formed on the circuit line 15 'on the lower surface of the substrate. It is provided with a plurality of solder balls 26 attached to each. In addition, the BGA semiconductor package 20 includes an encapsulation layer 28 formed by molding a one-side mold on a substrate. Here, the encapsulation layer 28 protects the semiconductor chip 22 and the gold wire 24 from the external environment.
그러나, 전술한 종래 기술의 인쇄회로기판을 사용하는 BGA 반도체 패키지는, 인쇄회로기판과 인캡슐레이션층의 열팽창 계수 차이 및/또는 상기 기판과 인캡슐레이션층 사이의 접착력 약화로 인하여, 인쇄회로기판과 인캡슐레이션층 사이에 틈(Delamination)이 발생하거나 반도체 패키지 자체가 휘어지는 문제점이 있다. 심지어는, 상기한 이유로 인하여, 인쇄회로기판과 인캡슐레이션층이 분리될 수도 있다. 따라서, 기존의 인쇄회로기판을 사용한 반도체 패키지는 불량율이 높은 문제점이 있다.However, the BGA semiconductor package using the above-described prior art printed circuit board is a printed circuit board due to the difference in thermal expansion coefficient between the printed circuit board and the encapsulation layer and / or the weakening of the adhesive force between the substrate and the encapsulation layer. Delamination occurs between the encapsulation layer and the semiconductor package itself. Even for this reason, the printed circuit board and the encapsulation layer may be separated. Therefore, the semiconductor package using the conventional printed circuit board has a high defect rate problem.
이에 따라, 기존에는, BGA 반도체 패키지 제조시에, 플라즈마 에칭 공정을 사용하여 기판(10)과 인캡슐레이션층(28) 사이의 접착력을 강화시키고 있지만, 이러한 경우에는, 공정의 추가로 인해 반도체 패키지의 제조 비용 및 시간이 크게 증가하며, 생산수율이 저하되는 문제점이 발생한다.Accordingly, in the conventional manufacturing of BGA semiconductor packages, a plasma etching process is used to enhance the adhesion between the substrate 10 and the encapsulation layer 28. In this case, however, the semiconductor package is added due to the addition of the process. The production cost and time of the increase greatly, the problem occurs that the production yield is lowered.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위하여, 복수의 로킹-홀을 구비한 반도체 패키지용 인쇄회로기판 및 이를 사용한 반도체 패키지를 제공함에 그 목적이 있다.An object of the present invention is to provide a printed circuit board for a semiconductor package having a plurality of locking-holes and a semiconductor package using the same, in order to solve the above problems of the prior art.
본 발명의 상세한 설명에서 사용되는 도면을 보다 충분히 이해하기 위하여, 각 도면의 간단한 설명이 제공된다.In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.
도1은 종래 기술에 따른 반도체 패키지용 인쇄회로기판의 단면도이다.1 is a cross-sectional view of a printed circuit board for a semiconductor package according to the prior art.
도2는 도1의 인쇄회로기판을 사용하여 제조된 반도체 패키지의 단면도이다.FIG. 2 is a cross-sectional view of a semiconductor package manufactured using the printed circuit board of FIG. 1.
도3은 본 발명의 일실시예에 따른 복수의 로킹-홀을 구비한 반도체 패키지용 인쇄회로기판을 나타내는 평면도이다.3 is a plan view illustrating a printed circuit board for a semiconductor package having a plurality of locking holes according to an embodiment of the present invention.
도4는 도3의 4 - 4선을 따라 취한 인쇄회로기판의 단면도이다.4 is a cross-sectional view of the printed circuit board taken along line 4-4 of FIG.
도5는 본 발명에 따른 복수의 로킹-홀을 구비한 인쇄회로기판을 사용한 반도체 패키지를 나타내는 단면도이다.5 is a cross-sectional view showing a semiconductor package using a printed circuit board having a plurality of locking-holes according to the present invention.
도6a 내지 도6c는 본 발명에 따른 복수의 로킹-홀을 구비한 인쇄회로기판을 사용하여 반도체 패키지를 제조하는 방법을 설명하기 위한 단면도이다.6A to 6C are cross-sectional views illustrating a method of manufacturing a semiconductor package using a printed circuit board having a plurality of locking holes according to the present invention.
<도면의 주요부분에 대한 부호의 설명><Description of the symbols for the main parts of the drawings>
110 : 기판 몸체 120 : 비아 홀110: substrate body 120: via hole
130 : 로킹-홀 140 : 다이 패드130: locking-hole 140: die pad
152, 154 : 상,하부 회로선 160 : 솔더 레지스트152, 154: upper and lower circuit lines 160: solder resist
220 : 반도체 칩 230 : 골드 와이어220: semiconductor chip 230: gold wire
240 : 인캡슐레이션(Encapsulation) 250 : 솔더볼240: Encapsulation 250: Solder Ball
상기와 같은 기술적 과제를 달성하기 위한 본 발명의 일면은 소정의 봉지재로 몰딩되는 반도체 패키지의 인쇄회로기판에 관한 것이다. 본 발명의 일면에 따른 인쇄회로기판은 판상의 기판 몸체; 상기 기판 몸체의 상면에 형성된 상부 회로선; 상기 기판 몸체의 하면에 형성된 하부 회로선; 상기 기판 몸체를 관통하도록 형성되며, 상기 상부 회로선과 상기 하부 회로선을 전기적으로 연결시키기 위한 비아 홀; 및 상기 기판 몸체를 관통하도록 형성되며, 상기 반도체 패키지의 제조 공정시, 상기 봉지재로 충전되는 복수의 로킹-홀을 구비한다.One aspect of the present invention for achieving the above technical problem relates to a printed circuit board of a semiconductor package molded with a predetermined sealing material. The printed circuit board according to the aspect of the present invention is a plate-shaped substrate body; An upper circuit line formed on an upper surface of the substrate body; A lower circuit line formed on the bottom surface of the substrate body; A via hole formed to penetrate the substrate body and electrically connecting the upper circuit line and the lower circuit line; And a plurality of locking-holes formed through the substrate body and filled with the encapsulant during the manufacturing process of the semiconductor package.
상기와 같은 기술적 과제를 달성하기 위한 본 발명의 다른 일면은 복수의 로킹-홀을 구비한 인쇄회로기판을 사용한 반도체 패키지에 관한 것이다. 본 발명의 다른 일면에 따른 반도체 패키지는 반도체 칩; 상기 반도체 칩이 실장되며, 소정 패턴의 상부 회로선 및 하부 회로선이 상면 및 하면에 각각 형성되고, 상기 상부 회로선과 상기 하부 회로선을 전기적으로 연결하기 위한 비아 홀 및 복수의 로킹-홀이 형성된 인쇄회로기판; 상기 반도체 칩과 상기 상부 회로선을 전기적으로 연결시키는 다수의 와이어; 및 소정의 봉지재로 상기 반도체 칩과 상기 인쇄회로기판을 몰딩하여 형성된 인캡슐레이션층을 구비한다. 여기서, 상기 인쇄회로기판의 로킹-홀은 상기 인쇄회로기판을 관통하도록 형성되어, 상기 몰딩 공정시에, 상기 봉지재로 충전된다.Another aspect of the present invention for achieving the above technical problem relates to a semiconductor package using a printed circuit board having a plurality of locking-holes. According to another aspect of the present invention, a semiconductor package includes a semiconductor chip; The semiconductor chip is mounted, and upper and lower circuit lines of a predetermined pattern are formed on upper and lower surfaces, respectively, and via holes and a plurality of locking-holes for electrically connecting the upper and lower circuit lines are formed. Printed circuit board; A plurality of wires electrically connecting the semiconductor chip and the upper circuit line; And an encapsulation layer formed by molding the semiconductor chip and the printed circuit board with a predetermined encapsulation material. Here, the locking-hole of the printed circuit board is formed to penetrate the printed circuit board, and is filled with the encapsulant during the molding process.
본 발명과 본 발명의 동작상의 잇점 및 본 발명의 실시에 의하여 달성되는 목적을 충분히 이해하기 위해서는 본 발명의 바람직한 실시예를 예시하는 첨부 도면 및 첨부 도면에 기재된 내용을 참조하여야 한다.In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.
이하, 첨부한 도3 내지 도6c를 참조하여 본 발명의 바람직한 일실시예에 따른 복수의 로킹-홀을 구비한 반도체 패키지용 인쇄회로기판과, 상기 인쇄회로기판을 사용한 반도체 패키지에 대하여 상세히 설명한다.Hereinafter, a printed circuit board for a semiconductor package having a plurality of locking holes and a semiconductor package using the printed circuit board will be described in detail with reference to FIGS. 3 to 6C. .
도3은 본 발명의 일실시예에 따른 복수의 로킹-홀을 구비한 반도체 패키지용 인쇄회로기판을 나타내는 평면도이고, 도4는 도3의 4 - 4선을 따라 취한 인쇄회로기판의 단면도이다. 도3 및 도4를 참조하면, 본 발명의 인쇄회로기판은 기판 몸체(110), 복수의 비아 홀(Via Holes)(120), 복수(도시예에서는 12개)의 로킹-홀(Locking-holes)(130), 다이 패드(140), 상,하부 회로선(152, 154), 솔더레지스트(160)를 구비한다.3 is a plan view illustrating a printed circuit board for a semiconductor package having a plurality of locking holes according to an embodiment of the present invention, and FIG. 4 is a cross-sectional view of the printed circuit board taken along lines 4-4 of FIG. 3 and 4, the printed circuit board of the present invention includes a substrate body 110, a plurality of via holes 120, and a plurality of locking-holes (12 in the illustrated example). 130), a die pad 140, upper and lower circuit lines 152 and 154, and a solder resist 160.
상기 기판 몸체(110)는 비티 수지(BT Resin; Bismaleimidetraizine Resin), 섬유 강화재 및 폴리이미드 중 적어도 어느 하나로 형성된 판재이다. 이러한 기판 몸체(110)에는 복수의 비아 홀(120) 및 로킹-홀(130)이 두께 방향으로 관통되도록 소정 위치에 형성된다. 상기 각 비아 홀(120)의 내벽면에는 전기 신호의 흐름을 위한 전도성 물질(도시하지 않음)이 도포된다. 또한, 상기 기판 몸체(110)의 상면 및 하면의 소정 부분에는 구리(Cu) 등으로 전도성 박층을 형성하고 사진 식각(Photo Etching) 공정 또는 리소그래피(Lithography) 공정 등에 의하여, 상기 다이 패드(140) 및 상,하부 회로선(152, 154)이 형성된다. 상기 상,하부 회로선(152, 154)은 비아 홀(120)을 매개로 하여 전기적으로 연결되며, 상기 하부 회로선(154)에는 솔더볼을 부착하기 위한 패드가 형성된다. 여기서, 상기 복수의 로킹-홀(130)은, 반도체 패키지의 몰딩 공정시, 인캡슐레이션층을 형성하는 봉지재(Encapsulant)가 충전되어 인쇄회로기판과 인캡슐레이션층 사이의 접착력을 강화시키게 된다.The substrate body 110 is a plate formed of at least one of BT Resin (Bismaleimidetraizine Resin), a fiber reinforcing material, and a polyimide. The substrate body 110 is formed at a predetermined position such that the plurality of via holes 120 and the locking-holes 130 penetrate in the thickness direction. Conductive materials (not shown) for the flow of electrical signals are coated on the inner wall surface of each of the via holes 120. In addition, a conductive thin layer may be formed on a predetermined portion of the upper and lower surfaces of the substrate body 110 by copper or the like, and the die pad 140 may be formed by a photo etching process or a lithography process. Upper and lower circuit lines 152 and 154 are formed. The upper and lower circuit lines 152 and 154 are electrically connected to each other via the via hole 120, and pads for attaching solder balls are formed in the lower circuit lines 154. Here, the plurality of locking-holes 130 are filled with an encapsulant to form an encapsulation layer during molding of the semiconductor package, thereby enhancing adhesion between the printed circuit board and the encapsulation layer. .
상기 솔더 레지스트(160)는 다이 패드(140) 전체, 상부 및 하부 회로선(152, 154)의 일부분에 도포되어, 상기 다이 패드(140), 상부 및 하부 회로선(152, 154)의 일부분을 외부 환경으로부터 보호한다. 이 때, 상기 솔더 레지스트(160)는 복수의 로킹-홀(130) 이외의 영역에 도포되어, 복수의 로킹-홀(130)이 외부에 노출된 상태를 유지하도록 한다.The solder resist 160 is applied to the entirety of the die pad 140, and to portions of the upper and lower circuit lines 152 and 154, so that portions of the die pad 140, the upper and lower circuit lines 152 and 154 are removed. Protect from the external environment. In this case, the solder resist 160 is applied to a region other than the plurality of locking-holes 130 to maintain a state in which the plurality of locking-holes 130 are exposed to the outside.
도5는 본 발명에 따른 복수의 로킹-홀을 구비한 인쇄회로기판을 사용한 BGA반도체 패키지를 나타내는 단면도이다. 도5를 참조하면, 본 발명의 반도체 패키지는 인쇄회로기판(210), 반도체 칩(220), 다수의 골드 와이어(230), 인캡슐레이션층(240) 및 다수의 솔더볼(250)을 구비한다.5 is a cross-sectional view showing a BGA semiconductor package using a printed circuit board having a plurality of locking-holes according to the present invention. Referring to FIG. 5, the semiconductor package of the present invention includes a printed circuit board 210, a semiconductor chip 220, a plurality of gold wires 230, an encapsulation layer 240, and a plurality of solder balls 250. .
상기 인쇄회로기판(210)은, 도3 및 도4에 대해 설명한 바와 같이, 기판 몸체(110), 복수의 비아 홀(120), 복수의 로킹-홀(130), 다이 패드(140), 상,하부 회로선(152, 154) 및 솔더 레지스트(160)를 구비하므로, 이에 대한 상세한 설명은 생략하며, 동일한 도면를 사용한다.As described with reference to FIGS. 3 and 4, the printed circuit board 210 may include a substrate body 110, a plurality of via holes 120, a plurality of locking-holes 130, a die pad 140, and an upper portion. Since the lower circuit lines 152 and 154 and the solder resist 160 are provided, a detailed description thereof will be omitted and the same drawings will be used.
상기 반도체 칩(220)은 인쇄회로기판(210)의 다이 패드(140) 상에 접착제 등으로 부착된다. 상기 각각의 골드 와이어(230)는 와이어 본딩 작업에 의해 일단부가 반도체 칩(220)의 입출력 단자에 연결되고 타단부가 인쇄회로기판의 상부 회로선(152) 상에 장착되어, 반도체 칩(220)과 인쇄회로기판(210)을 전기적으로 연결시킨다.The semiconductor chip 220 is attached to the die pad 140 of the printed circuit board 210 with an adhesive or the like. Each of the gold wires 230 is connected to an input / output terminal of the semiconductor chip 220 by wire bonding, and the other end thereof is mounted on the upper circuit line 152 of the printed circuit board. And the printed circuit board 210 are electrically connected.
상기 인캡슐레이션층(240)은 에폭시 몰딩 합성물을 인쇄회로기판(210)의 상면에 도포하는 몰딩 공정에 의하여 형성되며, 상기 몰딩 공정시, 에폭시 몰딩 합성물 중 일부는 인쇄회로기판(210)의 로킹-홀들(130)로 유입된다. 이에 따라, 상기 인캡슐레이션층(240)과 인쇄회로기판(210)이 서로 견고하게 접착되어, 그 사이에 틈이 생기거나 휨이 발생하는 것을 방지할 수 있다. 한편, 인캡슐레이션층(240)을 형성하는 수지로 에폭시 몰딩 합성물이 사용되었으나, 본 발명의 다른 실시예에서는, 다른 열경화성 수지 또는 열가소성 수지 등이 인캡슐레이션층(240)을 형성할 몰딩 공정의 재료로서 채용될 수 있다.The encapsulation layer 240 is formed by a molding process in which an epoxy molding compound is applied to the upper surface of the printed circuit board 210. During the molding process, some of the epoxy molding compound is locked in the printed circuit board 210. Flows into the holes 130. Accordingly, the encapsulation layer 240 and the printed circuit board 210 may be firmly adhered to each other, thereby preventing gaps or warpage from occurring. Meanwhile, although an epoxy molding compound is used as the resin for forming the encapsulation layer 240, in another embodiment of the present invention, another thermosetting resin or thermoplastic resin may be used to form the encapsulation layer 240. It can be employed as a material.
상기 솔더볼(250) 각각은 인쇄회로기판(210)의 하부 회로선(154)에 형성된 패드에 부착된다.Each of the solder balls 250 is attached to a pad formed on the lower circuit line 154 of the printed circuit board 210.
이와 같은 BGA 반도체 패키지를 제작하는 방법에 대하여, 도6a 내지 도6c를 참조하여 설명한다. 먼저, 인쇄회로기판(210)의 상면 중앙에 형성된 다이 패드(140) 상에 반도체 칩(220)을 접착하여 고정시킨다(도6a 참조). 그런 다음, 다수의 골드 와이어(230)를 공지된 와이어 본딩 공정으로 인쇄회로기판의 상면에 형성된 상부 회로선(152) 및 반도체 칩(220)의 입출력 단자에 연결하여, 반도체 칩(220)과 상부 회로선(152)이 전기적으로 연결되도록 한다(도6b 참조).A method of manufacturing such a BGA semiconductor package will be described with reference to Figs. 6A to 6C. First, the semiconductor chip 220 is adhered and fixed on the die pad 140 formed at the center of the upper surface of the printed circuit board 210 (see FIG. 6A). Thereafter, the plurality of gold wires 230 are connected to the upper circuit line 152 formed on the upper surface of the printed circuit board and the input / output terminals of the semiconductor chip 220 by a known wire bonding process, thereby forming the semiconductor chip 220 and the upper portion. The circuit line 152 is electrically connected (see FIG. 6B).
이러한 상태에서, 에폭시 몰딩 합성물을 공지된 몰딩 공정으로 인쇄회로기판(210)의 도포하고 경화시켜, 인캡슐레이션층(240)을 형성한다(도6c 참조). 이 때, 상기 에폭시 몰딩 합성물 중 일부분은 인쇄회로기판(210)의 로킹-홀(130)내로 유입되어, 인캡슐레이션층(240)과 인쇄회로기판(210)의 결합이 견고하게 유지되도록 한다.In this state, the epoxy molding compound is applied and cured of the printed circuit board 210 by a known molding process to form an encapsulation layer 240 (see FIG. 6C). At this time, a portion of the epoxy molding compound is introduced into the locking-hole 130 of the printed circuit board 210, so that the coupling between the encapsulation layer 240 and the printed circuit board 210 is maintained firmly.
마지막으로, 상기 인쇄회로기판(210)의 하부 회로선(154) 상에 형성된 패드 각각에 솔더볼(250)을 부착하여 도5에 도시된 바와 같은 BGA 반도체 패키지를 제조한다.Finally, a solder ball 250 is attached to each pad formed on the lower circuit line 154 of the printed circuit board 210 to manufacture a BGA semiconductor package as shown in FIG. 5.
이와 같은 본 발명의 인쇄회로기판을 사용한 반도체 패키지는, 몰딩 공정시에 인쇄회로기판의 로킹-홀(130)내에 충전된 합성물에 의하여 인쇄회로기판(210)과 인캡슐레이션층(240)간의 결합력이 향상되어, 기판과 인캡슐레이션층 사이에 틈이 발생하거나 휘어짐이 방지되며, 결국 반도체 패키지의 불량율을 감소시킬 수 있다.The semiconductor package using the printed circuit board according to the present invention has a bonding force between the printed circuit board 210 and the encapsulation layer 240 by a compound filled in the locking-hole 130 of the printed circuit board during the molding process. This can be improved to prevent gaps or warpage between the substrate and the encapsulation layer, which in turn can reduce the failure rate of the semiconductor package.
본 발명은 도면에 도시된 일실시예를 참고로 설명되었으나 이는 예시적인 것에 불과하며, 본 기술 분야의 통상의 지식을 가진 자라면 이로부터 다양한 변형 및 균등한 타실시예가 가능하다는 점을 이해할 것이다. 예를 들면, 전술한 실시예에서는 복수의 로킹 홀(130)이 솔더 레지스트(160)를 도포하기 전에 형성되는 것으로 설명하였으나, 본 발명의 다른 실시예에서는, 상기 복수의 로킹 홀(130)이 솔더 레지스트(160)를 도포한 후에, 소정의 천공 작업에 의하여 형성될 수도 있다. 따라서, 본 발명의 진정한 기술적 보호범위는 첨부된 특허청구범위의 기술적 사상에 의해 정해져야 할 것이다.Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. For example, in the above-described embodiment, the plurality of locking holes 130 are described before the solder resist 160 is applied. In another embodiment of the present invention, the plurality of locking holes 130 are soldered. After applying the resist 160, it may be formed by a predetermined drilling operation. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.
전술한 바와 같은 본 발명에 따른 인쇄회로기판에 의하면, 반도체 패키지의 인쇄회로기판과 인캡슐레이션층간의 결합력이 향상되어, 기판과 인캡슐레이션층 사이에 틈이 발생하거나 휘어짐이 방지되어, 결국 반도체 패키지의 불량율을 감소시킬 수 있다.According to the printed circuit board according to the present invention as described above, the bonding force between the printed circuit board and the encapsulation layer of the semiconductor package is improved, so that gaps or warpage between the substrate and the encapsulation layer are prevented, and eventually, the semiconductor The failure rate of the package can be reduced.
또한, 본 발명에 의하면, 인쇄회로기판과 인캡슐레이션층 사이의 접착력을 증가시키기 위한 별도의 플라즈마 에칭 공정이 불필요하므로, 반도체 패키지의 생산수율을 향상시키면서도 소요 비용을 절감할 수 있게 된다.In addition, according to the present invention, a separate plasma etching process for increasing the adhesion between the printed circuit board and the encapsulation layer is unnecessary, and thus the required cost can be reduced while improving the production yield of the semiconductor package.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020064747A KR20040036002A (en) | 2002-10-23 | 2002-10-23 | Printed Circuit Substrate for use in a Semiconductor Package with Locking-Holes and Semiconductor Package using the Substrate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020064747A KR20040036002A (en) | 2002-10-23 | 2002-10-23 | Printed Circuit Substrate for use in a Semiconductor Package with Locking-Holes and Semiconductor Package using the Substrate |
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| KR20040036002A true KR20040036002A (en) | 2004-04-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101039441B1 (en) * | 2008-10-13 | 2011-06-08 | 주식회사 아토 | Wafer centering method |
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| US5557150A (en) * | 1992-02-07 | 1996-09-17 | Lsi Logic Corporation | Overmolded semiconductor package |
| JPH08316364A (en) * | 1995-05-16 | 1996-11-29 | Toshiba Corp | Semiconductor device |
| KR970030696A (en) * | 1995-11-08 | 1997-06-26 | 김광호 | Plastic Ball Grid Array Package with Printed Circuit Board with Locking Holes |
| US5773895A (en) * | 1996-04-03 | 1998-06-30 | Intel Corporation | Anchor provisions to prevent mold delamination in an overmolded plastic array package |
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| US5557150A (en) * | 1992-02-07 | 1996-09-17 | Lsi Logic Corporation | Overmolded semiconductor package |
| JPH08316364A (en) * | 1995-05-16 | 1996-11-29 | Toshiba Corp | Semiconductor device |
| KR970030696A (en) * | 1995-11-08 | 1997-06-26 | 김광호 | Plastic Ball Grid Array Package with Printed Circuit Board with Locking Holes |
| US5773895A (en) * | 1996-04-03 | 1998-06-30 | Intel Corporation | Anchor provisions to prevent mold delamination in an overmolded plastic array package |
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| KR101039441B1 (en) * | 2008-10-13 | 2011-06-08 | 주식회사 아토 | Wafer centering method |
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