KR20040034081A - Array substrate and method of manufacturing the same - Google Patents

Abstract

PURPOSE: An array substrate, and a method for manufacturing the same are provided to prevent data lines from being opened by alien substances, and prevent a cell reaction between a conductive film for a pad and a second metal film. CONSTITUTION: An array substrate(100) includes a display area(D) on which a plurality of unit pixels are formed, and a pad area(P) placed at an outline of the display area for receiving picture signals applied to the unit pixels. A wire layer includes first to third pad metal films(127a-127c) accumulated on the pad area, wherein the third metal film covers exposed surfaces of the first and second metal pad films. A passivation film(130) is formed on the substrate and the wire layer, and has contact holes(136) exposing a part of the third pad metal film. A conductive film(145) is formed on side walls of the contact holes and the exposed third metal film so that the conductive film is electrically connected with the wire layer.

Description

ARRAY SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

The present invention relates to an array substrate and a method for manufacturing the same, and more particularly, to an array substrate and a method for manufacturing the same that can reduce the defective rate.

Recently, an information processing device requires a display device that serves as an interface so that a user may visually check the information processed by the information processing device. A liquid crystal display is a typical display device. A liquid crystal display is a display device that uses a modulation of light by liquid crystal by applying a voltage to a specific molecular array of liquid crystal to convert it into another molecular array and converting a change in optical properties into a visual change. to be.

Specifically, a liquid crystal display device includes an array substrate on which a thin film transistor (TFT) and a pixel electrode are formed, a color filter substrate facing the array substrate, and a liquid crystal interposed between the array substrate and the color filter substrate. Consists of layers.

According to the structure of the TFT, the liquid crystal display includes an amorphous-silicon liquid crystal display (a-si LCD) and a polycrystalline-silicon liquid crystal display (hereinafter, poly-si LCD). Separated by. Specifically, the a-si LCD is made of TFT made of a-si, and the poly-si LCD is made of TFT made of poly-si.

The poly-si TFT has a disadvantage in that the manufacturing process is more complicated than that of the a-si LCD. However, since the poly-si TFT has a higher charge transfer rate than the a-si TFT, the poly-si TFT can be embedded on a substrate without separately mounting a driving circuit. Therefore, the poly-si LCD can realize a cost reduction effect, a thinner and lighter weight due to the built-in circuit than the a-si LCD. In addition, there is an advantage that it is suitable as a switching element used to implement a large screen and a high resolution screen has been recently developed a lot.

In the poly-si LCD, a gate wiring and a data wiring are generally formed of chromium (Cr). The gate line may include a gate line formed on the array substrate, a gate electrode branched from the gate line, and a gate pad electrode formed at one end of the gate line. The data line may include a data line formed on the array substrate, a source and drain electrode branched from the data line, and a data pad electrode formed at one end of the data line.

The gate pad electrode and the data pad electrode are electrically connected to a conductive film made of indium tin oxide (hereinafter referred to as ITO) with a protective film therebetween.

However, as the poly-si LCD becomes larger in size, in order to minimize delays in the gate and data lines, a material having a low resistance is applied to the materials constituting the gate and data lines. Therefore, recently, aluminum-neodymium (AlNd) having a lower resistance than chromium (Cr) is used for the gate wiring.

However, when the aluminum-neodymium (AlNd) is used for the data line, a battery effect is caused between aluminum and ITO as the data pad electrode is in contact with ITO used for the conductive film. As a result, the data pad electrode may be corroded. Therefore, the molybdenum tungsten (MoW) is applied to the data line with a higher resistance than the aluminum-neodymium (AlNd) but less risk of corrosion.

However, as the screen of the poly-si LCD increases in size, high-speed operation is required, and thus there is a greater demand for materials having less resistance to corrosion and less corrosion than the molybdenum tungsten (MoW). In addition, in the case of using the molybdenum tungsten (MoW), a foreign material is often generated in the process of forming the data line, so that the data line is often opened.

Accordingly, a first object of the present invention is to provide an array substrate for reducing the defective rate.

It is also a second object of the present invention to provide a method of manufacturing such an array substrate.

1 is a cross-sectional view showing in detail an array substrate according to an embodiment of the present invention.

2A to 2D are diagrams illustrating a manufacturing process of the array substrate illustrated in FIG. 1.

FIG. 3 is a cross-sectional view of a liquid crystal display having the array substrate shown in FIG. 1.

<Explanation of symbols for the main parts of the drawings>

100: array substrate 110: substrate

120: poly-si TFT 127c: third pad metal film

127: data pad electrode 127a: first pad metal film

127b: second pad metal film 130: protective film

140 pixel electrode 145 pad conductive film

200: color filter substrate 300: liquid crystal layer

400: liquid crystal display

According to another aspect of the present invention, there is provided an array substrate including: a substrate including a display area in which a plurality of unit pixels are formed and a pad area disposed outside the display area; A wiring layer formed of first to third metal films in the display area and the pad area, wherein the third metal film covers exposed surfaces of the first and second metal films in the pad area; A protective film formed on the substrate and the wiring layer and having a contact hole exposing a portion of the third metal film; And a conductive film formed on the sidewall of the contact hole and the exposed third metal film and electrically connected to the wiring layer.

In addition, a method of manufacturing an array substrate according to the present invention for achieving a second object of the present invention, the first substrate on a substrate divided into a display area in which a plurality of unit pixels are formed and a pad area located outside the display area Forming a wiring layer comprising a third metal film, wherein the third metal film surrounds exposed surfaces of the first and second metal films in the pad region; Forming a passivation layer on the substrate and the wiring layer, the passivation layer having a contact hole exposing a portion of the third metal layer; And forming a conductive film electrically connected to the wiring layer on the sidewall of the contact hole and the exposed third metal film.

According to such an array substrate and a method of manufacturing the same, the data pad electrode includes a first metal film, a second metal film stacked thereon, and a third metal film completely surrounding the exposed surfaces of the first and second metal films. The failure rate of the array substrate can be reduced by preventing the battery reaction generated between the conductive film and the second metal film.

Hereinafter, with reference to the accompanying drawings, it will be described in detail a preferred embodiment of the present invention.

1 is a cross-sectional view showing in detail an array substrate according to an embodiment of the present invention.

Referring to FIG. 1, an array substrate 100 according to an embodiment of the present invention is divided into a display area D displaying an image and a pad area P formed around the display area D. FIG. The display area D includes a poly-si TFT 120 connected to a gate line (not shown) and a data line (not shown) formed on the substrate 110 and a transparent pixel electrode connected to the poly-si TFT 120. A plurality of unit pixels consisting of 140 are provided. The unit pixel is formed in a matrix form on the substrate 110.

In detail, a poly-si layer 121, a gate insulating layer 122 formed on the gate insulating layer 122, and a gate electrode 123 formed on the gate insulating layer 122 are formed on the substrate 110 to correspond to the display area D. It is provided. Thereafter, the poly-si layer 121 is doped with boron (B) or phosphorus (P) to form an n or p channel. In addition, an interlayer insulating layer 126 having first and second contact holes 126a and 126b exposing portions of the poly-si layer 121 is formed on the gate insulating layer 122 on which the gate electrode 123 is formed. Are stacked. The poly-si layer on the interlayer insulating layer 126 through the source electrode 124 and the second contact hole 126b electrically connected to the poly-si layer 121 through the first contact hole 126a. A drain electrode 125 electrically connected to the 121 is formed.

Here, the source and drain electrodes 124 and 125 have a triple layer structure. That is, the source electrode 124 is formed of a first metal film 124a made of tungsten molybdenum (MoW), a second metal film 124b made of aluminum-neodymium (AlNd), and a tungsten made of tungsten molybdenum (MoW). Three metal films 124c are provided. In addition, the drain electrode 125 has a structure in which the fourth to sixth metal films 125a, 125b, and 125c are sequentially stacked. The fourth to sixth metal layers 125a, 125b, and 125c each include molybdenum tungsten (MoW), aluminum-neodymium (AlNd), and molybdenum tungsten (MoW).

Thereafter, a passivation layer 130 is formed on the substrate 110 on which the source and drain electrodes 124 and 125 are formed, and the third contact hole 135 is formed to expose a portion of the drain electrode 125. The passivation layer 130 is formed of an organic insulating layer such as a photosensitive acrylic resin. The pixel electrode 140 is formed on the passivation layer 130, which is a transparent electrode electrically connected to the drain electrode 125 through the third contact hole 135. The pixel electrode 140 is formed of indium tin oxide (ITO) or indium zinc oxide (IZO).

The pad region P may be formed at one end of the data line and receive an image signal from the outside of the array substrate 100, and may be formed at one end of the gate line, and the array substrate ( Each of the gate pads receives a driving signal from the outside. In the drawing of the present invention, the pad area P is a data pad area.

The first and second metal layers 124a and 124b or the fourth and fifth metal layers 125a constituting source and drain electrodes 124 and 125 on the substrate 110 corresponding to the pad region P. Referring to FIG. , The first and second pad metal films 127a and 127b formed on the same process as 125b are formed. Thereafter, on the second pad metal layer 127b and the substrate 100, a third pad metal layer 127c completely covering the exposed surfaces of the first and second pad metal layers 127a and 127b is formed. Is formed. As a result, the data pad electrode 127 is formed.

Thereafter, the passivation layer 130 formed in the display area D extends in the pad region P where the data pad electrode 127 is formed, and the third pad metal layer is formed on the passivation layer 130. A fourth contact hole 136 is formed to expose a portion of 127c. Next, a pad conductive layer 145 electrically connected to the data pad electrode 127 through the fourth contact hole 136 is formed on the passivation layer 130. Thus, the array substrate 100 used for the liquid crystal display device is completed.

As shown in the drawing, the third pad metal film 127c completely covers the second pad metal film 127b, so that the pad conductive film 145 and the second pad metal film 127b directly contact each other. No contact is made. Therefore, the battery reaction can be prevented from occurring between the pad conductive film 145 and the second pad metal film 127b due to penetration of chemical or moisture.

Although the pad region corresponding to the data pad region is illustrated in the above embodiment of the present invention, the same applies to the pad region corresponding to the gate pad region. That is, when the gate wiring is formed in a triple layer like the data wiring, the gate pad electrode may have the same structure as that of the data pad electrode 127.

2A to 2D are views illustrating a process of manufacturing the array substrate illustrated in FIG. 1.

Referring to FIG. 2A, the a-si layer is deposited on the display region D of the substrate 110 at about 540 ° C. by using Low Plasma Chemical Vapor Deposition (LPCVD). After that, the a-si layer is heat-treated at about 600 ° C. for a long time to form a poly-si layer. In order to increase crystallinity, silicon ion implantation may be performed before crystallization. Subsequently, the poly-si layer 121 is patterned through a dry etching process.

Next, the poly-si layer 121 is reacted with oxygen to form an oxide film. The oxide film is used as the gate insulating film 122. Thereafter, a gate electrode layer is formed on the gate insulating layer 122, and then patterned to form a gate electrode 123.

An ion implantation process for doping the poly-si layer 121 is performed on the substrate 110 on which the gate electrode 123 is formed. In other words, it is doped with boron (B) to make a p-type TFT, and doped with phosphorus (P) to make an n-type TFT. When the n or p channel is determined by injecting boron (B) or phosphorus (P), an interlayer insulating layer 126 is deposited on the substrate 110. First and second contact holes 126a and 126b exposing the n-channel layer or the p-channel layer are formed in the interlayer insulating layer 126.

2B, first and second metals electrically connected to the poly-si layer 121 doped through the first contact hole 126a may be formed in the display area D of the substrate 110. Films 124a and 124b are formed, and fourth and fifth metal films 125a and 125b electrically connected to the poly-si layer 121 doped through the second contact hole 126b are formed. Here, the first and fourth metal layers 124a and 125a are made of molybdenum tungsten (MoW), and the second and fifth metal layers 124b and 125b are made of aluminum-neodymium (AlNd).

Meanwhile, a first pad electrode layer 127a made of tungsten molybdenum (MoW) is formed in the pad region P of the substrate 110, and a second pad electrode layer 127b made of aluminum-neodymium (AlNd) is formed. Is formed. Thereafter, a first photoresist film 128 is formed on the second pad metal film 127b to pattern the first and second pad metal films 127a and 127b, and then the first photoresist film is formed. After patterning 128, the first and second pad metal films 127a and 127b are wet-viewed. In the wet vision process, the over-etching ratio is adjusted to about 10% to 60% to adjust the width of the first and second pad metal layers 127a and 127b to be 1 μm smaller than the width of the first photoresist layer 128. do.

For example, when the width of the first photoresist film 128 is 8.0 μm, the widths of the first and second pad metal films 127a and 127b are formed to 6.4 μm.

Next, referring to FIG. 2C, a third metal film 124c made of tungsten molybdenum (MoW) is formed on the second metal film 124b in the display area D of the substrate 110. A sixth metal film 125c made of tungsten molybdenum (MoW) is formed on the fifth metal film 125b. As a result, a source electrode 124 having a triple layer structure including the first to third metal layers 124a, 124b, and 124c is formed on the substrate 110, and the fourth to sixth metal layers 125a and 125b are formed. , A drain electrode 125 having a triple film structure consisting of 125c is formed. Thus, the poly-si TFT 120 is completed on the substrate 110.

In addition, a third pad metal layer 127c is formed on the first and second pad metal layers 127a and 127b in the pad region P, and then a second pad layer is formed on the third pad metal layer 127c. The photoresist film 129 is formed. The second photoresist layer 129 is patterned to be larger than the width of the first photoresist layer 128 by lowering an exposure amount than the first photoresist layer 129. For example, when the width of the first photoresist film 128 is 8.0 μm, the width of the second photoresist film 129 is preferably 9.0 μm.

When the third pad metal layer 127c is wet etched while the second photoresist layer 129 is formed, exposed surfaces of the first and second pad metal layers 127a and 127b are formed. The third pad metal film 127c is formed to completely cover. Here, the third pad metal film 127c has a width of about 8.4 μm. Subsequently, when the second photoresist layer 129 is removed, the pad region P of the substrate 110 includes data pad electrodes 127 including first to third pad metal layers 127a, 127b, and 127c. ) Is formed.

Referring to FIG. 2D, a passivation layer 130 made of an organic insulating layer is formed over the entire surface of the display area D in which the poly-si TFT 120 is formed and the pad area P in which the data pad electrode 127 is formed. Is formed. A third contact hole 135 exposing the drain electrode 125 of the poly-si TFT 120 is formed in the passivation layer 130, and a fourth contact hole exposing the data pad electrode 127. 136 is formed.

Accordingly, as shown in FIG. 1, the transparent electrode formed on the passivation layer 130 is connected to the drain electrode 125 through the third contact hole 135 and used as the pixel electrode 140. The pad is connected to the data pad electrode 127 through the fourth contact hole 136 and used as the pad conductive layer 145. Thus, the array substrate 100 used for the liquid crystal display device is completed.

FIG. 3 is a cross-sectional view of a liquid crystal display having the array substrate shown in FIG. 1.

Referring to FIG. 3, the liquid crystal display device 400 includes an array substrate 100, a color filter substrate 200 facing the array substrate 100, an array substrate 100, and a color filter substrate 200. It consists of a liquid crystal layer 300 interposed between. The liquid crystal display device 400 includes only the display area D and the array substrate 100 in which the array substrate 100 and the color filter substrate 200 face each other and the liquid crystal layer 300 is interposed therebetween. The pad area P is divided.

The array substrate 100 is a substrate on which a unit pixel including a poly-si TFT 120 and a pixel electrode 140 is formed in a matrix form on the first substrate 110 to correspond to the display area D. FIG. In detail, the poly-si layer 121, the gate insulating layer 122, and the gate electrode 123 are sequentially stacked on the substrate 110. An interlayer insulating layer 126 having first and second contact holes 126a and 126b exposing portions of the poly-si layer 121 is formed on the gate insulating layer 122 on which the gate electrode 123 is formed. . Thereafter, source and drain electrodes 124 and 125 electrically connected to the poly-si layer 121 are formed on the interlayer insulating layer 126 through the first and second contact holes 126a and 126b, respectively.

Here, the source and drain electrodes 124 and 125 have a triple layer structure. That is, the source electrode 124 is formed of a first metal film 124a made of tungsten molybdenum (MoW), a second metal film 124b made of aluminum-neodymium (AlNd), and a tungsten made of tungsten molybdenum (MoW). Three metal films 124c are provided. In addition, the drain electrode 125 has a structure in which the fourth to sixth metal films 125a, 125b, and 125c are sequentially stacked. The fourth to sixth metal layers 125a, 125b, and 125c each include molybdenum tungsten (MoW), aluminum-neodymium (AlNd), and molybdenum tungsten (MoW).

Thereafter, a passivation layer 130 is formed on the substrate 110 on which the source and drain electrodes 124 and 125 are formed, and the third contact hole 135 is formed to expose a portion of the drain electrode 125. Next, the pixel electrode 140 is formed on the passivation layer 130, which is a transparent electrode electrically connected to the drain electrode 125 through the third contact hole 135.

In addition, a data pad electrode 127 or a gate pad electrode is formed on the first substrate 110 to correspond to the pad region P. FIG. Here, only the data pad electrode 127 is shown. Specifically, the first and second pad metals are formed on the first substrate 110 in the same process as the first and second metal films 124a and 124b or the fourth and fifth metal films 125a and 125b. Films 127a and 127b are formed. Subsequently, a third pad metal layer (not shown) may completely cover exposed surfaces of the first and second pad metal layers 127a and 127b on the first substrate 100 on which the second pad metal layer 127b is formed. 127c) is formed. As a result, the data pad electrode 127 is formed.

Thereafter, a passivation layer 130 having a fourth contact hole 136 exposing a portion of the third pad metal layer 127c is formed in the pad region P on which the data pad electrode 127 is formed. Next, a pad conductive layer 145 electrically connected to the data pad electrode 127 through the fourth contact hole 136 is formed on the passivation layer 130. Thus, the array substrate 100 is completed.

As shown in the drawing, the third pad metal film 127c completely covers the second pad metal film 127b, so that the pad conductive film 145 and the second pad metal film 127b directly contact each other. No contact is made. Therefore, the battery reaction can be prevented from occurring between the pad conductive film 145 and the second pad metal film 127b due to penetration of chemical or moisture.

Meanwhile, the color filter substrate 200 is formed on the color filter 220 and the color filter 220 formed of R, G, and B color pixels corresponding to the display area D on the second substrate 210. The substrate is uniformly formed to form the common electrode 230 facing the pixel electrode 140.

When the array substrate 100 and the color filter substrate 200 are completed, the array substrate 100 and the color filter substrate 200 are coupled to face the pixel electrode 140 and the common electrode 230. do. Thereafter, the liquid crystal layer 300 is interposed between the array substrate 100 and the color filter substrate 200. As a result, the liquid crystal display device 400 is completed.

According to such an array substrate and a method of manufacturing the same, a data line including a data line, a source / drain electrode, and a data pad electrode may be configured to expose the first metal film, the second metal film stacked thereon, and the first and second metal films. And a third metal film completely surrounding the surface. In addition, the pad conductive film is connected to the third metal film through a pad contact hole exposing a portion of the third metal film.

Therefore, the phenomenon in which the data line is opened by the foreign matter can be prevented. In addition, a failure rate of the array substrate may be reduced by preventing a battery reaction between the pad conductive film and the second metal film.

Although described with reference to the embodiments above, those skilled in the art will understand that the present invention can be variously modified and changed without departing from the spirit and scope of the invention as set forth in the claims below. Could be.

Claims (6)

A substrate including a display area in which a plurality of unit pixels are formed and a pad area positioned outside the display area to receive an image signal applied to the unit pixels; A wiring layer including first to third metal films sequentially stacked in the display area and the pad area, wherein the third metal film is laminated on the pad area to cover the exposed surfaces of the first and second metal films; A passivation layer formed on the substrate and the wiring layer and having a contact hole exposing a portion of the third metal layer; And And a conductive film formed on the sidewalls of the contact hole and the exposed third metal film and electrically connected to the wiring layer. The array substrate of claim 1, wherein the first and third metal films are made of molybdenum tungsten (MoW), and the second metal film is made of aluminum-neodymium (AlNd). The display device of claim 1, wherein a polysilicon layer, a gate insulating film, a gate electrode, and an interlayer insulating film are sequentially provided in the display area, and a source / drain electrode connected to the polysilicon layer is formed of the first to third metal films. Equipped, And the wiring layer includes the source / drain electrode, the data pad electrode, and a data line for connecting the source electrode and the data pad electrode. A first to third metal film formed on a substrate divided into a display area in which a plurality of unit pixels are formed and a pad area positioned outside the display area, wherein the third metal film is formed in the pad area. Forming a wiring layer surrounding the exposed surface of the metal film; Forming a passivation layer on the substrate and the wiring layer, the passivation layer having a contact hole exposing a portion of the third metal layer; And Forming a conductive film electrically connected to the wiring layer on the sidewalls of the contact hole and the exposed third metal film. The method of claim 4, wherein the first and third metal films are made of tungsten molybdenum (MoW), and the second metal film is made of aluminum-neodymium (AlNd). The method of claim 4, wherein the forming of the wiring layer on the pad area comprises: Forming the first metal film; Forming the second metal film on the first metal film; Patterning the first and second metal films; And And forming the third metal film on the substrate on which the patterned first and second metal films are formed, surrounding the exposed surfaces of the first and second metal films.