KR20040031954A - Fabricating method of semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to prevent reverse micro loading effect by controlling the flow rate of CxFy gas and Ar gas according to RF power. CONSTITUTION: An interlayer dielectric(33) is formed on a silicon substrate(31). An etch stop layer(35), a core insulating layer(37) and a hard mask are sequentially stacked on the interlayer dielectric. A photoresist pattern(41) is formed on the hard mask to expose a storage node forming region of a cell region(I) and a guard ring forming region of a peripheral region(II). A hard mask pattern(39) is formed by etching the hard mask using the photoresist pattern as a mask. A core insulating layer is then etched by two-step etching processes, wherein the flow rate of an etching gas, such as CxFy and Ar is changed according to RF power.

Description

Fabrication method of semiconductor device

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to prevent the occurrence of reverse micro loading effect, which is an etch stop phenomenon occurring in a guard ring region of a peripheral circuit region having a large etching region during a trench etching intended as a storage electrode. A method for manufacturing a semiconductor device.

Recently, due to the trend toward higher integration of semiconductor devices, it is difficult to form capacitors with sufficient capacitance due to a decrease in cell size.

The capacitor mainly uses an oxide film, a nitride film, or an O.N.-O. (oxide) film as a dielectric with polysilicon as a conductor. Increasing the capacity is an important factor in the high integration of DRAM devices.

The capacitance (C) of the capacitor is proportional to the dielectric constant (ε0, permittivity of vacuum), dielectric constant (εr) of the dielectric film and the area (A) of the storage electrode, and is inversely proportional to the thickness (T) of the dielectric film. The capacitance can be increased by making the thickness thinner or increasing the surface area of the storage electrode.

As described above, efforts have been made to use a dielectric film having a high dielectric constant to increase the capacitance of the capacitor, or to form the storage electrode in a three-dimensional structure to increase the surface area of the capacitor.

Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

1A to 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.

First, a substructure such as an isolation layer, a word line and a bit line is formed on the silicon substrate 11.

Next, an interlayer insulating film 13 is formed over the entire surface. In this case, the interlayer insulating layer 13 is formed of an oxide-based thin film.

Next, an etch stop layer 15 is formed on the interlayer insulating layer 13. In this case, the etch stop layer 15 is formed of a nitride layer having an etch selectivity with respect to the interlayer insulating layer 13.

Next, a core insulating layer 17 is formed on the etch stop layer 15. The core insulating layer 17 is formed to have a height of a storage electrode to be formed, and is formed of an oxide-based material having an etching selectivity with respect to the etch stop layer 15.

Next, a thin film for hard mask (not shown) is formed on the core insulating layer 17. In this case, the hard mask thin film is formed of a polysilicon layer having an etch selectivity with respect to the core insulating layer 17 and used as a hard mask in a subsequent etching process, thereby reducing the thickness of the photoresist pattern.

Next, a first photoresist layer pattern 21 exposing a portion, which is intended as a storage electrode, in the cell region I and a portion, which is intended as a guard ring, in the peripheral circuit region II, on the core insulation layer 17. To form. At this time, the guard ring of the peripheral circuit region (II) prevents the core insulating layer 17 on the peripheral circuit region (II) from being lost during the wet etching process of removing the core insulating layer (17) after forming the storage electrode. And to prevent the storage electrode at the edge of the cell region (I) from falling over.

Next, the hard mask thin film is etched using the first photoresist pattern 21 as an etch mask to form a hard mask pattern 19. (See Figure 1A)

Thereafter, the core insulation layer 17 is etched using the first photoresist layer pattern 21 and the hard mask pattern 19 to form an first trench 23 and a second trench 24. In this case, the first trench 23 is a portion intended to be a storage electrode in the cell region I, and the second trench 24 is a portion intended to be a guard ring in the peripheral circuit region II and the second trench 24 is formed. ) Area is several hundred times larger than the area of the first trench 23.

In the etching process, a C ₄ F ₆ having a large CF ratio is applied to maintain the etch selectivity of the first photoresist pattern 21 or the hard mask pattern 19 with respect to the core insulation layer 17. It is carried out by a dry etching process using a mixed gas using each gas and using oxygen and argon as an additive gas as an etching gas. At this time, as the CF ratio of the C _x F _y- based gas used as the stock angle gas is greater than 1/2, a large amount of etch residue is generated.

For reference, the oxygen gas serves to remove the polymer, the argon gas serves to uniform the etching rate.

At this time, the etching process is a bias RF (Radio Frequency) power of 1500W or more in a Magnetically Enhanced Reactive Ion Etch (MERIE) or Inductively Coupled Plasma (ICP) device, the flow rate ratio of C ₄ F ₆ gas and oxygen and argon gas 1: 1: 1: It is performed on the conditions 20 or more.

In particular, in the etching process, the flow ratio of the C ₄ F ₆ gas and the argon gas is 1: 20 or more, so that the high selectivity ratio is increased between the hard mask pattern 19 and the core insulating layer 17 in the cell region (I). Eggplant can obtain etching conditions. (See FIG. 1B)

Next, the first photoresist film pattern 21 and the hard mask pattern 19 are removed.

Next, a conductive layer (not shown) for a storage electrode is formed on the entire surface to have a predetermined thickness. In this case, the storage electrode conductive layer is formed of a polycrystalline silicon layer.

Next, a sacrificial insulating film (not shown) is formed on the conductive layer for the storage electrode to be planarized. In this case, the sacrificial insulating film is formed of a photosensitive film or an oxide film-based material.

Next, the sacrificial insulating layer and the conductive layer for the storage electrode are planarized and etched to form the storage electrode 25 and the guard ring 26. In this case, the planarization etching process may be performed by chemical mechanical polishing (CMP) or full surface etching.

Then, the sacrificial insulating film is removed.

Thereafter, a second photoresist pattern 27 is formed on the structure to protect the peripheral circuit region II. (See Figure 1C)

Next, the core insulating layer 17 on the cell region I is removed using the second photoresist layer pattern 27 as an etch mask to expose the storage electrode 25.

Next, the second photoresist pattern 27 is removed. (See FIG. 1D)

After that, a dielectric film and a plate electrode are formed to complete the capacitor.

As described above, the semiconductor device manufacturing method according to the related art requires an etching condition in which the etching selectivity of the polysilicon layer, which is a photoresist film or a hard mask, to the oxide layer is 10: 1 or more when the contact hole is etched according to the high integration of the device. Therefore, C ₄ F _6, which has a large CF ratio, is used in the etching gas used in the contact hole etching. In this case, when the flow rate ratio of C ₄ F ₆ to argon is greater than 1:20, the etching speed of the exposed area is slowed down, so that the second trench 24 of the peripheral circuit area having a large exposed area and the portion (R) of FIG. Likewise, an etch stop phenomenon called reverse micro loading phenomenon occurs.

This is followed by forming a storage electrode in a subsequent process, and removing the core insulation layer to remove the core insulation layer to expose the storage electrode, and removing the core insulation layer on the peripheral circuit region. There is a problem in that the material and the metal wiring are shorted to each other to reduce the operation characteristics and reliability of the device.

In order to solve the above problems of the prior art, C ₄ F used as an etching gas until a normal bias RF power is applied in a process of forming trenches having different exposed areas on the cell region and the peripheral circuit region. _{6 After the} gas is removed or the flow rate is reduced and the normal bias RF power is applied, the flow rate is increased by increasing the flow rate of C ₄ F ₆ gas in the cell area with small etching area and the peripheral circuit area with large etching area. It is an object of the present invention to provide a method for manufacturing a semiconductor device such that there is no difference in etching speed.

1A to 1D are cross-sectional views illustrating a manufacturing process of a semiconductor device according to the prior art.

2A to 2D are sectional views showing the manufacturing process of the semiconductor device according to the present invention.

<Description of Symbols for Major Parts of Drawings>

11, 31: silicon substrate 13, 33: interlayer insulating film

15, 35: etching preventing film 17, 37: core insulating film

19, 39: hard mask pattern 21, 41: first photoresist pattern

23, 43: first trench 24, 44: second trench

25, 45: storage electrode 26, 46: guard ring

27, 47: second photosensitive film pattern

Ⅰ: Cell area Ⅱ: Peripheral circuit area

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming an interlayer insulating film on the silicon substrate;

Forming a stacked structure of an etch stop layer, a core insulating layer, and a hard mask thin film on the interlayer insulating layer;

Forming a photoresist pattern on the hard mask thin film to expose a portion intended as a storage electrode in a cell region of the silicon substrate and a portion intended as a guard ring in a peripheral circuit region;

Etching the thin film for hard mask using the photoresist pattern as an etch mask to form a hard mask pattern;

Etching the core insulation layer using the photoresist pattern and the hard mask pattern as an etch mask, and changing the flow rate of the etching gas before the normal bias RF power is applied and after the normal bias RF power is applied, thereby etching in two steps;

The etch stop layer is formed of a nitride film,

The core insulating film is formed of an oxide film,

The hard mask thin film is formed of a polysilicon layer,

The etching process is performed using a plasma including C _x F _y -based gas, oxygen gas, and argon gas, and the flow rate ratio of the C _x F _y -based gas and argon gas is 1:20 before being applied with normal bias RF power. Consisting of a one-step etching process performed as follows and a two-step etching process performed with a normal bias RF power and a flow rate ratio of the C _x F _y -based gas to argon gas of at least 1:20,

The normal bias RF power is 1500 to 1600W,

The etching process is performed by using a plasma containing a C _x F _y- based gas, oxygen gas and argon gas, but the first step etching process by removing the C _x F _y- based gas before applying the normal bias RF power And a two-step etching process performed by applying a normal bias RF power and performing a flow rate ratio of the C _x F _y -based gas to an argon gas of 1:20 or more,

The C _x F _y- based gas has a _first feature that one of C ₂ F ₆ gas, C ₄ F ₆ gas, C ₄ F ₈ gas, C ₅ F ₈ gas, and a combination thereof is used.

Method for manufacturing a semiconductor device according to the present invention for achieving the above object,

Forming an interlayer insulating film on the silicon substrate;

Forming a stacked structure of an etch stop layer, a core insulating layer, and a hard mask thin film on the interlayer insulating layer;

Forming a photoresist pattern on the hard mask thin film to expose a portion intended as a storage electrode in a cell region of the silicon substrate and a portion intended as a guard ring in a peripheral circuit region;

Etching the thin film for hard mask using the photoresist pattern as an etch mask to form a hard mask pattern;

The core insulation layer is etched using plasma including C _x F _y -based gas, oxygen gas, and argon gas using the photoresist pattern and the hard mask pattern as an etch mask, and the flow rate ratio of the C _x F _y -based gas and argon gas is reduced. 1: 20 or less after the one-step etching process to etch the core insulation film until the etching prevention film is exposed to maintain the flow rate ratio of C _x F _y- based gas, oxygen gas and argon gas at 1: 20 or more Forming trenches having different sizes by performing a two-step etching process for over-etching the insulating film;

The second step of etching the core insulation film over-etched is characterized by including the process performed while maintaining the bias RF power to 1500 ~ 1600W.

Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

2A through 2D are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

First, a substructure such as an isolation layer, a word line and a bit line is formed on the silicon substrate 31.

Next, an interlayer insulating film 33 is formed over the entire surface. In this case, the interlayer insulating film 33 is formed of an oxide-based thin film.

Next, an etch stop layer 35 is formed on the interlayer insulating layer 33. In this case, the etch stop layer 35 is formed of a nitride film having an etch selectivity with respect to the interlayer insulating layer 33.

Next, a core insulating layer 37 is formed on the etch stop layer 35. The core insulating layer 37 is formed at a height of a storage electrode to be formed, and is formed of an oxide-based material having an etching selectivity with respect to the etch stop layer 35.

Next, a thin film for hard mask (not shown) is formed on the core insulating layer 37. In this case, the hard mask thin film is formed of a polysilicon layer having an etch selectivity with respect to the core insulating layer 37 and used as a hard mask during the subsequent etching process, thereby reducing the thickness of the photoresist pattern.

Next, a first photoresist layer pattern 31 exposing a portion intended as a storage electrode in the cell region I and a portion intended as a guard ring in the peripheral circuit region II on the core insulating layer 37. To form. At this time, the guard ring of the peripheral circuit region (II) prevents the core insulating layer 37 on the peripheral circuit region (II) from being lost during the wet etching process of removing the core insulating layer 37 after forming the storage electrode. And to prevent the storage electrode at the edge of the cell region (I) from falling over.

Next, the hard mask thin film is etched using the first photoresist pattern 41 as an etch mask to form a hard mask pattern 39. (See Figure 2A)

Thereafter, the core insulation layer 37 is etched using the first photoresist layer pattern 41 and the hard mask pattern 39 as an etch mask to form the first trench 43 and the second trench 44. In this case, the first trench 43 is a portion intended to be a storage electrode in the cell region I, and the second trench 44 is a portion intended to be a guard ring in the peripheral circuit region II. ) Is formed several hundred times larger than the area of the first trench 43.

The etching process is a C _x F _y- based gas having a large CF ratio in order to maintain an etch selectivity of the first photoresist layer pattern 41 or the hard mask pattern 39 with respect to the core insulating layer 37. Is used as a stock angular gas, and a dry etching process using a mixed gas using oxygen and argon as an additive gas as an etching gas. At this time, the C _x F _y- based gas may be a gas consisting of C ₂ F ₆ gas, C ₄ F ₆ gas, C ₄ F ₈ gas, C ₅ F ₈ gas or a combination thereof.

The etching process is performed in two steps by changing the etching conditions before and after the bias RF power is applied to more than 1500W in the MERIE or ICP device and after applying more than 1500W.

First, the one-step etching process is performed until the bias RF power is applied to 1500W or more, and is performed for 3 to 10 seconds under the condition that the flow rate ratio of CF _x -based gas, oxygen gas, and argon gas is 1: 1: 20 or less. In this case, the C _x F _y -based gas may not be used.

In the one-step etching process, the core insulation layer 37 may be partially etched by not using a C _x F _y- based gas that generates an etch residue or by decreasing a flow rate.

Next, the two-step etching process is performed under the condition that the flow rate ratio of CF _x -based gas, oxygen gas, and argon gas is 1: 1: 20 or more after the bias RF power is applied at 1500W or more. The second step etching process may improve the etching selectivity of the first photoresist layer pattern 41 and the hard mask pattern 39 to etch the core insulation layer 37 to etch the first trench 43 and the second trench. Form 44. At this time, the two-step etching process is performed until the etching prevention layer 35 is exposed, but proceeds to the transient etching process. (See Figure 2b)

Next, the first photoresist layer pattern 41 and the hard mask pattern 39 are removed.

Next, a conductive layer (not shown) for a storage electrode is formed on the entire surface to have a predetermined thickness. In this case, the storage electrode conductive layer is formed of a polycrystalline silicon layer.

Next, a sacrificial insulating film (not shown) is formed on the conductive layer for the storage electrode to be planarized. In this case, the sacrificial insulating film is formed of a photosensitive film or an oxide film-based material.

Next, the sacrificial insulating layer and the conductive layer for the storage electrode are planarized and etched to form the storage electrode 45 and the guard ring 46. In this case, the planarization etching process is performed by a CMP process or an entire surface etching process.

Then, the sacrificial insulating film is removed.

Thereafter, a second photoresist layer pattern 47 is formed on the structure to protect the peripheral circuit region II. (See Figure 2c)

Next, the core insulating layer 37 on the cell region I is removed using the second photoresist layer pattern 47 as an etch mask to expose the storage electrode 45. In this case, the core insulation layer 37 is removed by a wet etching process using a solution containing hydrofluoric acid.

Next, the second photoresist pattern 47 is removed. (See FIG. 2D)

After that, a dielectric film and a plate electrode are formed in the cell region I to complete the capacitor.

Meanwhile, as another embodiment of the present invention, the core insulation layer may be formed using the first photoresist layer pattern 41 and the hard mask pattern 39 as etch masks regardless of the magnitude of the bias RF power during the first stage etching process. (37) is removed until the etch stop layer 35 is exposed, and the flow rate ratio of C _x F _y -based gas, oxygen gas, and argon gas is maintained at a bias RF power of 1500 W or more by a two-step etching process. The first trench 43 and the second trench 44 may be formed by over-etching the core insulating layer 37 to be 1:20 or more.

As described above, the method of manufacturing a semiconductor device according to the present invention prevents the reverse micro loading effect, which is an etch stop phenomenon, from occurring in a guard ring region of a peripheral circuit region having a large etching region during a photolithography process using a storage electrode mask. The present invention relates to a method for manufacturing a semiconductor device. That is, the etching process is performed while changing the flow ratio of C _x F _y gas and argon gas according to the normal bias RF power to prevent the etch stop phenomenon in the peripheral circuit region having a large etching region. There is an advantage in that the electrode and the metal wiring can be prevented from being shorted to each other.

Claims (10)

Forming an interlayer insulating film on the silicon substrate; Forming a stacked structure of an etch stop layer, a core insulating layer, and a hard mask thin film on the interlayer insulating layer; Forming a photoresist pattern on the hard mask thin film to expose a portion intended as a storage electrode in a cell region of the silicon substrate and a portion intended as a guard ring in a peripheral circuit region; Etching the thin film for hard mask using the photoresist pattern as an etch mask to form a hard mask pattern; Etching the core insulation layer using the photoresist pattern and the hard mask pattern as an etch mask, and changing the flow rate of the etching gas before the normal bias RF power is applied and after the normal bias RF power is applied, thereby etching in two steps. Method of manufacturing the device. The method of claim 1, The etch stop layer is a semiconductor device manufacturing method, characterized in that formed of a nitride film. The method of claim 1, And the core insulating film is formed of an oxide film. The method of claim 1, The hard mask thin film is a method of manufacturing a semiconductor device, characterized in that formed of a polysilicon layer. The method of claim 1, The etching process is performed using a plasma including C _x F _y -based gas, oxygen gas, and argon gas, and the flow rate ratio of the C _x F _y -based gas and argon gas is 1:20 before being applied with normal bias RF power. A semiconductor comprising a one-step etching process performed as follows and a two-step etching process performed by applying a normal bias RF power and having a flow rate ratio of the C _x F _y -based gas to an argon gas of 1:20 or more. Method of manufacturing the device. The method according to claim 1 or 5, The normal bias RF power is a manufacturing method of a semiconductor device, characterized in that 1500 ~ 1600W. The method of claim 1, The etching process is performed by using a plasma containing a C _x F _y- based gas, oxygen gas and argon gas, but the first step etching process by removing the C _x F _y- based gas before applying the normal bias RF power And a two-step etching process performed by applying a normal bias RF power and performing a flow ratio of the C _x F _y -based gas and the argon gas to 1:20 or more. The method of claim 1, The C _x F _y- based gas is used in the group consisting of C ₂ F ₆ gas, C ₄ F ₆ gas, C ₄ F ₈ gas, C ₅ F ₈ gas and combinations thereof. Manufacturing method. Forming an interlayer insulating film on the silicon substrate; Forming a stacked structure of an etch stop layer, a core insulating layer, and a hard mask thin film on the interlayer insulating layer; Forming a photoresist pattern on the hard mask thin film to expose a portion intended as a storage electrode in a cell region of the silicon substrate and a portion intended as a guard ring in a peripheral circuit region; Etching the thin film for hard mask using the photoresist pattern as an etch mask to form a hard mask pattern; The core insulation layer is etched using plasma including C _x F _y -based gas, oxygen gas, and argon gas using the photoresist pattern and the hard mask pattern as an etch mask, and the flow rate ratio of the C _x F _y -based gas and argon gas is reduced. 1: 20 or less after the one-step etching process to etch the core insulation film until the etching prevention film is exposed to maintain the flow rate ratio of C _x F _y- based gas, oxygen gas and argon gas at 1: 20 or more And forming trenches having different sizes by performing a two-step etching process for over-etching the insulating film. The method of claim 9, The second step of etching the core insulation film over-etching is performed while maintaining a bias RF power of 1500 ~ 1600W.