KR20040029789A - 고속 연산기를 위한 래딕스-4 부스 연산기 - Google Patents
고속 연산기를 위한 래딕스-4 부스 연산기 Download PDFInfo
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- KR20040029789A KR20040029789A KR1020020060203A KR20020060203A KR20040029789A KR 20040029789 A KR20040029789 A KR 20040029789A KR 1020020060203 A KR1020020060203 A KR 1020020060203A KR 20020060203 A KR20020060203 A KR 20020060203A KR 20040029789 A KR20040029789 A KR 20040029789A
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- Prior art keywords
- decoder
- booth
- radix
- encoder
- operator
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/52—Multiplying; Dividing
- G06F7/523—Multiplying only
- G06F7/533—Reduction of the number of iteration steps or stages, e.g. using the Booth algorithm, log-sum, odd-even
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/49—Computations with a radix, other than binary, 8, 16 or decimal, e.g. ternary, negative or imaginary radices, mixed radix non-linear PCM
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computational Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Nonlinear Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
- Complex Calculations (AREA)
Abstract
Description
Claims (3)
- 입력되는 3개의 비트를 이용해 Z0, Z1, S0, S1의 네 개의 제어신호를 부호화기에서 생성해주는 부호화기;부분 곱과 ADD의 두개의 결과 값을 생성하도록 되어 있는 복호기로 이루어짐을 특징으로 하는 고속 연산기를 위한 래딕스-4 부스 연산기.
- 제 1항에 있어서,상기 복호기는 결과 값이 "0"과 보수의 경우 +1 값을 생성하기 위해 Z0과 Z1 신호를 생성하는 것을 특징으로 하는 고속 연산기를 위한 래딕스-4 부스 연산기.
- 제 1항에 있어서,상기 복호기는 입력되는 신호 y값을 쉬프트할지 그대로 내려 보낼지 반전 시킬지를 판단하기 위해 S0과 S1을 생성하도록 하는 것을 특징으로 하는 고속 연산기를 위한 래딕스-4 부스 연산기.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0060203A KR100477509B1 (ko) | 2002-10-02 | 2002-10-02 | 고속 연산기를 위한 래딕스-4 부스 연산기 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0060203A KR100477509B1 (ko) | 2002-10-02 | 2002-10-02 | 고속 연산기를 위한 래딕스-4 부스 연산기 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040029789A true KR20040029789A (ko) | 2004-04-08 |
KR100477509B1 KR100477509B1 (ko) | 2005-03-17 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2002-0060203A KR100477509B1 (ko) | 2002-10-02 | 2002-10-02 | 고속 연산기를 위한 래딕스-4 부스 연산기 |
Country Status (1)
Country | Link |
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KR (1) | KR100477509B1 (ko) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101590019B1 (ko) | 2015-05-29 | 2016-02-01 | 충남대학교산학협력단 | 전력 효율 향상을 위한 멀티플렉서가 없는 바이패싱 구조를 구비한 연산기 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55105732A (en) * | 1979-02-08 | 1980-08-13 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier |
JP2970231B2 (ja) * | 1992-07-02 | 1999-11-02 | 日本電気株式会社 | 並列乗算回路 |
US6065032A (en) * | 1998-02-19 | 2000-05-16 | Lucent Technologies Inc. | Low power multiplier for CPU and DSP |
KR20010019351A (ko) * | 1999-08-26 | 2001-03-15 | 윤종용 | 부스 알고리즘을 이용한 곱셈기의 인코더 |
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2002
- 2002-10-02 KR KR10-2002-0060203A patent/KR100477509B1/ko active IP Right Grant
Also Published As
Publication number | Publication date |
---|---|
KR100477509B1 (ko) | 2005-03-17 |
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