KR20040013928A - Method for forming inductor of semiconductor device - Google Patents
Method for forming inductor of semiconductor device Download PDFInfo
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- KR20040013928A KR20040013928A KR1020020047074A KR20020047074A KR20040013928A KR 20040013928 A KR20040013928 A KR 20040013928A KR 1020020047074 A KR1020020047074 A KR 1020020047074A KR 20020047074 A KR20020047074 A KR 20020047074A KR 20040013928 A KR20040013928 A KR 20040013928A
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- 238000000034 method Methods 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 6
- 239000002184 metal Substances 0.000 claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 71
- 239000010410 layer Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000007789 sealing Methods 0.000 claims abstract description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 5
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 4
- 239000011241 protective layer Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 9
- 238000002161 passivation Methods 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 18
- 239000002356 single layer Substances 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000010931 gold Substances 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/10—Inductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
Abstract
Description
본 발명은 반도체 소자의 인덕터 형성방법에 관한 것으로, 보다 상세하게는, 양호도(Quality factor) 및 자기공진주파수(Self Resonant Frequency)가 큰 인덕터를 형성하는 방법에 관한 것이다.The present invention relates to a method of forming an inductor of a semiconductor device, and more particularly, to a method of forming an inductor having a high quality factor and a self resonant frequency.
인덕터(Inductor)는 고주파의 수신/발신을 위한 회로의 한 요소(element)로서, 무선 통신 시장의 확대와 더불어 부상하고 있는 RF 소자 및 아날로그 소자에 필수적으로 사용되고 있다.An inductor is an element of a circuit for high frequency reception / emission, and is indispensably used in an emerging RF device and analog device with the expansion of the wireless communication market.
이러한 인덕터는 현재 GaAs 및 실리콘 기판 상에 집적되고 있으며, 한정된 면적에서 큰 인덕턴스(Inductance)를 구현하기 위해 적층형 구조로 형성되고 있다.These inductors are currently integrated on GaAs and silicon substrates, and are formed in a stacked structure to realize large inductance in a limited area.
도 1은 종래 기술에 따라 형성된 인덕터를 도시한 단면도로서, 이를 참조하여 그 제조방법을 설명하면 다음과 같다.1 is a cross-sectional view showing an inductor formed according to the prior art, the method of manufacturing the same with reference to this as follows.
먼저, 실리콘 기판(1) 표면에 CMOS 구조의 능동소자를 형성할 영역과 인덕터를 형성할 영역을 한정하는 트렌치형의 소자분리막(2)을 형성한 후, 상기 기판(1) 상에 제1절연막(3)을 형성한다. 그런다음, 상기 제1절연막(3) 상에 패턴 형태로 제1금속막(4)을 형성하고, 이어서, 상기 제1금속막(4)을 덮도록 상기 제1절연막(3) 상에 제2절연막(5)을 형성한다.First, a trench type device isolation layer 2 is formed on the surface of the silicon substrate 1 to define a region for forming an active element having a CMOS structure and a region for forming an inductor, and thereafter, a first insulating layer is formed on the substrate 1. (3) is formed. Then, a first metal film 4 is formed on the first insulating film 3 in a pattern form, and then a second second film is formed on the first insulating film 3 to cover the first metal film 4. The insulating film 5 is formed.
다음으로, 상기 제2절연막(5)의 일부분을 선택적으로 식각하여 상기 제1금속막(4)을 노출시키는 콘택홀(6)을 형성하고, 이어서, 금속기둥(7)을 형성한다.Next, a portion of the second insulating film 5 is selectively etched to form a contact hole 6 exposing the first metal film 4, and then a metal pillar 7 is formed.
그 다음, 상기 기판 결과물 상에 제2금속막을 증착하고, 이어, 상기 제2금속막을 패터닝하여 소정 간격으로 이격 배치된 수 개의 금속 패턴들로 이루어진 인덕터(10)를 형성한다.Next, a second metal film is deposited on the substrate resultant, and then the second metal film is patterned to form an inductor 10 composed of several metal patterns spaced apart at predetermined intervals.
이후, 상기 인덕터(10)를 덮도록 상기 제2절연막(5) 상에 보호막(11)을 도포한다.Thereafter, a protective film 11 is coated on the second insulating film 5 to cover the inductor 10.
도 2는 종래의 다른 기술에 따라 형성된 인덕터를 도시한 단면도로서, 도시된 바와 같이, 인덕터(20)는 다층의 금속배선 구조, 즉, 적층 구조로 형성된다.Figure 2 is a cross-sectional view showing an inductor formed according to another conventional technique, as shown, the inductor 20 is formed of a multi-layered metal wiring structure, that is, a laminated structure.
즉, 종래 다른 기술에 따른 인덕터(20)는 전술한 종래 기술에 따른 그것이 단층의 금속배선 구조, 즉, 단층 구조로 형성되는 것과는 달리 적층 구조로 형성되며, 그 형성 공정은 이전의 그것과 유사하다.That is, the inductor 20 according to another prior art is formed in a laminated structure, unlike that according to the prior art described above, which is formed of a single layer metal wiring structure, that is, a single layer structure, and the formation process is similar to that before. .
도 2에서, 도 1로부터 설명되지 않은 도면부호 6a는 제1콘택홀, 6b는 제2콘택홀, 7a는 제1금속기둥, 7b는 제2금속기둥, 10a는 하층 인덕터, 10b는 상층 인덕터, 12는 제3절연막, 13은 제4절연막, 그리고, 20은 적층 구조의 인덕터를 각각 나타낸다.In FIG. 2, reference numeral 6a, which is not described from FIG. 1, denotes a first contact hole, 6b denotes a second contact hole, 7a denotes a first metal pillar, 7b denotes a second metal pillar, 10a denotes a lower layer inductor, and 10b denotes an upper layer inductor. Denoted at 12 is a third insulating film, 13 at a fourth insulating film, and 20 at a laminated structure.
그러나, 종래 기술에 따른 인덕터는 다음과 같은 문제점이 있다.However, the inductor according to the prior art has the following problems.
먼저, 단층 구조의 인덕터는 그 형성 면적의 제약으로 인해 큰 인덕턴스를 얻을 수 없으며, 기판과 금속 패턴간 및 금속 패턴들간의 기생 용량의 증가로 인해 양호도(Quality factor)가 낮아지고, 자기공진주파수(Self Resonant Frequency) 특성 또한 저하된다.First, the inductor of the single-layer structure cannot obtain a large inductance due to the limitation of the formation area, and the quality factor is lowered due to the increase of parasitic capacitance between the substrate and the metal pattern and between the metal patterns, and the magnetic resonance frequency. (Self Resonant Frequency) characteristics are also deteriorated.
반면, 적층 구조의 인덕터는 그 길이가 길어짐에 따라 상기 단층 구조의 인덕터에 비해 큰 인덕턴스를 갖지만, 길이가 증가함에 따라 기생 저항이 증가하게 되고, 특히, 단층 구조에 비해 금속 패턴들간의 기생 용량이 크게 증가함으로써 양호도 및 자기공진주파수 특성이 크게 저하되며, 그래서, RF 소자에서 요구하는 특성을 만족시키는데 어려움이 있다.On the other hand, the multilayer inductor has a larger inductance than the inductor of the single layer structure as the length thereof increases, but the parasitic resistance increases as the length increases, and in particular, the parasitic capacitance between the metal patterns is higher than that of the single layer structure. By greatly increasing, the goodness and magnetic resonance frequency characteristics are greatly degraded, and thus, there is a difficulty in satisfying the characteristics required by the RF element.
한편, 이와 같은 문제를 해결하기 위해서는 기생 용량 및 기생 저항을 감소시켜야 하는 바, 종래에는 상기 기생 저항을 감소시키기 위해 저저항 금속, 예컨데, 금(Au)을 금속배선의 재질로 사용하면서 금속막의 두께를 증가시키는 방법을 이용하고 있고, 아울러, 상기 기생 용량을 감소시키기 위해 기판과 금속 패턴 사이 및 금속 패턴들 사이의 유전체를 두껍게 하거나 유전상수가 낮은 유전체를 사용하는 방법을 이용하고 있다.Meanwhile, in order to solve such a problem, parasitic capacitance and parasitic resistance should be reduced. In the related art, in order to reduce the parasitic resistance, a low resistance metal, for example, gold (Au) is used as the material of the metal wiring and the thickness of the metal film In order to reduce the parasitic capacitance, a thicker dielectric or a dielectric having a low dielectric constant is used to reduce the parasitic capacitance.
그런데, 반도체 집적 공정에서는 배선 재료로서 취급이 용이한 알루미늄을 주로 사용하고 있는 바, 금(Au)의 적용에 어려움이 있고, 또한, 소자 특성을 고려할 때 유전체의 두께를 무한정 증가시킬 수 없음은 물론 현재 사용되고 있는 유전체 중에서 가장 낮은 유전상수를 갖는 FSG(Fluorine doped Silica Glass)막의 유전상수도 3.7 정도로 높기 때문에 기생 용량의 증가를 해결함에 어려움이 있는 바, 현재로서는 고성능 인덕터의 구현에 어려움이 있다.However, in the semiconductor integration process, aluminum, which is easy to handle as a wiring material, is mainly used, which makes it difficult to apply gold (Au). Moreover, in view of device characteristics, the thickness of the dielectric cannot be increased indefinitely. Since the dielectric constant of the FSG (Fluorine doped Silica Glass) film having the lowest dielectric constant among the currently used dielectrics is high as about 3.7, it is difficult to solve the increase of the parasitic capacitance.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로서, 큰 인덕턴스를 가지면서 양호도 및 자기공진주파수를 향상시킬 수 있는 반도체 소자의 인덕터 형성방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming an inductor of a semiconductor device capable of improving the goodness and the magnetic resonance frequency while having a large inductance.
도 1은 종래 기술에 따라 형성된 인덕터를 도시한 단면도.1 is a cross-sectional view showing an inductor formed according to the prior art.
도 2는 종래 다른 기술에 따라 형성된 인덕터를 도시한 단면도.Figure 2 is a cross-sectional view showing an inductor formed in accordance with another conventional technique.
도 3은 본 발명의 실시예에 따라 형성된 인덕터를 도시한 단면도.3 is a cross-sectional view illustrating an inductor formed in accordance with an embodiment of the present invention.
도 4는 본 발명의 다른 실시예에 따라 형성된 인덕터를 도시한 단면도.4 is a sectional view showing an inductor formed according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
31 : 실리콘 기판 32 : 소자분리막31 silicon substrate 32 device isolation film
33 : 제1절연막 34 : 제1금속막33: first insulating film 34: first metal film
35 : 제2절연막 36 : 콘택홀35: second insulating film 36: contact hole
36a : 제1콘택홀 36b : 제2콘택홀36a: first contact hole 36b: second contact hole
37 : 금속기둥 37a : 제1금속기둥37 metal pillar 37a: first metal pillar
37b : 제2금속기둥 38 : 인덕터37b: second metal pillar 38: inductor
38a : 하층 인덕터 38b : 상층 인덕터38a: lower layer inductor 38b: upper layer inductor
39 : 보호막 40 : 상부 밀폐용 웨이퍼39: protective film 40: wafer for upper sealing
41 : 제3절연막 42 : 제4절연막41: third insulating film 42: fourth insulating film
50 : 적층 구조의 인덕터50: laminated inductor
상기와 같은 목적을 달성하기 위하여, 본 발명은, 실리콘 기판 상에 제1절연막을 증착하는 단계; 상기 제1절연막 상의 소정 영역에 패턴 형태로 제1금속막을 형성하는 단계; 상기 제1금속막을 덮도록 기판 상에 제2절연막을 증착하는 단계: 상기 제2절연막을 식각하여 상기 제1금속막의 일부분을 노출시키는 콘택홀을 형성하는 단계; 상기 콘택홀 내에 금속기둥을 형성하는 단계; 상기 금속기둥을 포함한 제2절연막 상에 제2금속막을 증착하는 단계; 상기 제2금속막을 패터닝하여 소정 간격으로 이격 배치되는 수 개의 금속 패턴들을 형성하는 단계; 상기 금속 패턴들을 덮도록 상기 제2절연막 상에 보호막을 증착하는 단계; 상기 보호막 상에 상기 금속 패턴들의 상부 영역을 노출시키는 감광막 패턴을 형성하는 단계; 상기 금속 패턴들 및 그 주변이 노출되도록 상기 감광막 패턴을 이용해서 노출된 보호막 부분과 그 아래의 제2절연막 부분을 식각 제거하는 단계; 및 상기 금속 패턴들 주변이 진공 상태를 유지하도록 상기 기판 결과물 상에 상부 밀폐용 부재를 부착하는 단계를 포함하는 반도체 소자의 인덕터 형성방법을 제공한다.In order to achieve the above object, the present invention, the step of depositing a first insulating film on a silicon substrate; Forming a first metal film in a pattern form on a predetermined region on the first insulating film; Depositing a second insulating layer on the substrate so as to cover the first metal layer: forming a contact hole exposing a portion of the first metal layer by etching the second insulating layer; Forming a metal pillar in the contact hole; Depositing a second metal film on the second insulating film including the metal pillar; Patterning the second metal layer to form several metal patterns spaced apart from each other at a predetermined interval; Depositing a passivation layer on the second insulating layer to cover the metal patterns; Forming a photoresist pattern on the passivation layer to expose an upper region of the metal patterns; Etching away the exposed portion of the protective layer and the portion of the second insulating layer under the exposed portion by using the photosensitive layer pattern so that the metal patterns and the periphery thereof are exposed; And attaching an upper sealing member on the substrate resultant to maintain a vacuum around the metal patterns.
여기서, 상기 상부 밀폐용 부재는 바람직하게 웨이퍼이며, 상기 상부 밀폐용 부재를 부착하는 단계는 진공 챔버 내에 웨이퍼 레벨(wafer level)의 기판 결과물과 상부 밀폐용 부재를 장입시킨 후, 진공이 유지되는 조건하에서 상기 기판 결과물과 상부 밀폐용 부재간을 조립하는 방식으로 진행한다.Here, the upper sealing member is preferably a wafer, and the step of attaching the upper sealing member is a condition in which a vacuum is maintained after charging a wafer level substrate result and the upper sealing member in a vacuum chamber. In the process of assembling between the substrate resultant and the upper sealing member.
또한, 상기 금속 패턴들은 적어도 1층 이상의 구조로 형성한다.In addition, the metal patterns are formed in a structure of at least one layer.
본 발명에 따르면, 인덕터 주변의 절연막을 제거하면서 그 주변이 진공 상태가 되도록 함으로써 기생 용량을 극소화시킬 수 있으며, 이에 따라, 양호도 및 자기공진주파수 특성이 우수한 인덕터를 구현할 수 있다.According to the present invention, the parasitic capacitance can be minimized by removing the insulating film around the inductor while maintaining the vacuum around the inductor, thereby realizing an inductor having excellent goodness and self-resonant frequency characteristics.
(실시예)(Example)
이하, 첨부된 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 3은 본 발명의 실시예에 따른 인덕터를 도시한 단면도로서, 이를 참조하여 그 형성방법을 설명하면 다음과 같다.3 is a cross-sectional view showing an inductor according to an embodiment of the present invention, the method of forming the same with reference to the following.
도시된 바와 같이, 먼저, 실리콘 기판(31)의 표면 내에 STI(Shallow Trench Isolation) 공정에 따라 CMOS 구조의 능동소자 형성 영역과 인덕터 형성 영역을 한정하는 트렌치형의 소자분리막(32)을 형성한다. 그런다음, 상기 기판(31) 상에 제1절연막(33)을 증착한 후, 도시되지는 않았으나, 콘택을 형성한다.As shown, first, a trench type isolation layer 32 is formed in the surface of the silicon substrate 31 to define an active element formation region and an inductor formation region of a CMOS structure according to a shallow trench isolation (STI) process. Then, after depositing the first insulating film 33 on the substrate 31, a contact is formed, although not shown.
이어서, 상기 제1절연막(33) 상에 패턴의 형태로 제1금속막(34)을 형성하고, 그런다음, 상기 제1금속막(34)을 포함한 기판 결과물 상에 제2절연막(35)을 형성한다.Subsequently, a first metal film 34 is formed on the first insulating film 33 in the form of a pattern. Then, the second insulating film 35 is formed on the substrate product including the first metal film 34. Form.
다음으로, 상기 제2절연막(35)의 일부분을 선택적으로 식각하여 상기 제1금속막(34)을 노출시키는 콘택홀(36)을 형성하고, 이어, 상기 콘택홀(36) 내에 금속막을 매립시켜 금속기둥(37)를 형성한다.Next, a portion of the second insulating layer 35 is selectively etched to form a contact hole 36 exposing the first metal layer 34, and then a metal film is buried in the contact hole 36. A metal pillar 37 is formed.
그 다음, 상기 금속기둥(37)를 포함한 기판 결과물 상에 제2금속막을 증착하고, 이어서, 상기 제2금속막을 패터닝하여 소정 간격으로 이격 배치되는 수 개의 금속 패턴들로 구성된 인덕터(38)를 형성한 후, 상기 인덕터(38)를 덮도록 제2절연막(35) 상에 보호막(39)을 증착한다.Next, a second metal film is deposited on the substrate product including the metal pillars 37, and then the second metal film is patterned to form an inductor 38 composed of several metal patterns spaced apart at predetermined intervals. After that, the passivation layer 39 is deposited on the second insulating layer 35 to cover the inductor 38.
계속해서, 인덕터(38) 주변에서 발생되는 기생 용량을 감소시키기 위해 상기 보호막(39) 상에 상기 인덕터(38) 상부 영역을 노출시키는 감광막 패턴(도시안됨)을 형성하고, 그런다음, 제1금속막(34)이 노출될 때까지 BOE 또는 HF 용액을 이용한 습식 식각 공정으로 노출된 보호막 부분 및 그 아래의 제2절연막 부분을 식각 제거하며, 이 결과로서, 상기 인덕터(38) 주변의 절연막을 제거하여 기생 용량이 극소화되도록 만든다.Subsequently, in order to reduce the parasitic capacitance generated around the inductor 38, a photoresist pattern (not shown) is formed on the passivation layer 39 to expose the upper region of the inductor 38, and then the first metal The exposed portion of the protective film and the portion of the second insulating film under the wet etching process using a BOE or HF solution are etched away until the film 34 is exposed, and as a result, the insulating film around the inductor 38 is removed. To minimize parasitic capacity.
이후, 상기 기판 결과물 상에 상부 밀폐용 부재, 예컨데, 상부 밀폐용 웨이퍼(40)를 부착시켜 본 발명에 따른 인덕터의 형성을 완성한다.Thereafter, an upper sealing member, for example, an upper sealing wafer 40 is attached to the substrate resultant to complete the formation of the inductor according to the present invention.
이때, 상기 상부 밀폐용 웨이퍼(40)의 부착은 인덕터(38) 주변이 조립 후에도 진공을 유지하여 기생 용량이 극소화될 수 있도록 웨이퍼 레벨(wafer level)에서 진공 조립(hermetic packaging)으로 진행한다. 즉, 인덕터(38)가 형성된 기판 결과물과 상부 밀폐용 웨이퍼(40)를 진공 챔버 내에 장입시킨 후, 진공이 유지되는 조건하에서 상기 기판 결과물과 상부 밀폐용 웨이퍼(40)간의 조립을 진행한다.At this time, the attachment of the upper sealing wafer 40 proceeds to hermetic packaging at the wafer level so that the periphery of the inductor 38 maintains a vacuum even after assembly to minimize the parasitic capacitance. That is, after loading the substrate product on which the inductor 38 is formed and the upper sealing wafer 40 in the vacuum chamber, assembly between the substrate product and the upper sealing wafer 40 is performed under the condition that vacuum is maintained.
이와 같이 하면, 상기 인덕터 주변에 절연막이 없고, 그리고, 인덕터 주변이 진공 상태를 이루므로, 기판과 금속 패턴간 또는 금속 패턴들간의 기생 용량은 극소화되며, 따라서, 기생 용량에 의한 양호도 및 자기공진주파수 특성의 저하는 방지될 수 있고, 결국, 고성능 인덕터를 구현할 수 있게 된다.In this case, since there is no insulating film around the inductor, and the inductor surrounds a vacuum state, the parasitic capacitance between the substrate and the metal pattern or between the metal patterns is minimized, and thus the goodness and magnetic resonance due to the parasitic capacitance are minimized. Degradation of the frequency characteristic can be prevented, resulting in a high performance inductor.
도 4는 본 발명의 다른 실시예에 따라 형성된 인덕터를 도시한 단면도로서, 도시된 바와 같이, 이 실시예에 따른 인덕터(48)는 그 주변이 진공 상태를 유지하는 것은 동일하며, 단지, 단층 구조로 형성된 이전 실시예의 그것과는 달리 적층 구조로 형성된다.4 is a cross-sectional view showing an inductor formed according to another embodiment of the present invention. As shown, the inductor 48 according to this embodiment is the same in that its periphery maintains a vacuum state, but only a single layer structure. Unlike that of the previous embodiment, formed into a laminated structure.
따라서, 이 실시예에 따른 인덕터(48)는 그 주변이 진공 상태를 유지하는 것으로 인해 기생 용량의 극소화를 이루어 양호도 및 자기공진주파수 특성 저하를 방지할 수 있으며, 특히, 그 길이가 이전 실시예 보다 길어짐에 따라 상대적으로 큰 인덕턴스를 갖게 된다.Therefore, the inductor 48 according to this embodiment can minimize the parasitic capacitance due to maintaining the vacuum in the periphery thereof to prevent deterioration of the goodness and the magnetic resonance frequency characteristics, in particular, the length thereof is the previous embodiment. As it gets longer, it has a relatively large inductance.
도 4에서, 도 3으로부터 설명되지 않은 도면부호 36a는 제1콘택홀, 36b는 제2콘택홀, 37a는 제1금속기둥, 37b는 제2금속기둥, 38a는 하층 인덕터, 38b는 상층 인덕터, 41은 제3절연막, 42는 제4절연막, 그리고, 50은 적층 구조의 인덕터를 각각 나타낸다.In FIG. 4, reference numeral 36a, which is not described from FIG. 3, is a first contact hole, 36b is a second contact hole, 37a is a first metal pillar, 37b is a second metal pillar, 38a is a lower inductor, 38b is an upper inductor, 41 denotes a third insulating film, 42 denotes a fourth insulating film, and 50 denotes an inductor having a stacked structure.
이상에서와 같이, 본 발명은 인덕터 주변의 절연막을 제거함과 동시에 진공 상태를 유지시켜 줌으로써 기판과 금속 패턴간 및 금속 패턴들간의 기생 용량을 감소시켜 양호도가 높고 자기공진주파수 특성이 우수한 인덕터를 구현할 수 있으며, 아울러, 인덕터를 적층 구조로 형성함으로써 상기한 잇점 이외에 제한된 면적에서 큰 인덕턴스를 갖는 인덕터를 구현할 수 있다.As described above, the present invention reduces the parasitic capacitance between the substrate and the metal pattern and the metal patterns by removing the insulating film around the inductor and maintaining a vacuum state, thereby realizing an inductor having high goodness and excellent magnetic resonance frequency characteristics. In addition, by forming the inductor in a laminated structure, it is possible to implement an inductor having a large inductance in a limited area in addition to the above advantages.
결국, 본 발명은 RF 소자에서 요구하는 고성능의 인덕터를 용이하게 제공할 수 있다.As a result, the present invention can easily provide a high performance inductor required by an RF device.
기타, 본 발명은 그 요지가 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes in the range which does not deviate from the summary.
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| KR100948297B1 (en) * | 2007-12-10 | 2010-03-17 | 주식회사 동부하이텍 | Semiconductor device and method of manufacturing the semiconductor device |
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| KR100233237B1 (en) * | 1997-09-10 | 1999-12-01 | 정선종 | Fine inductor having 3-dimensional coil structure and method for forming the same |
| TW363278B (en) * | 1998-01-16 | 1999-07-01 | Winbond Electronics Corp | Preparation method for semiconductor to increase the inductive resonance frequency and Q value |
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| KR100948297B1 (en) * | 2007-12-10 | 2010-03-17 | 주식회사 동부하이텍 | Semiconductor device and method of manufacturing the semiconductor device |
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