JP4135564B2 - Semiconductor substrate and manufacturing method thereof - Google Patents

Semiconductor substrate and manufacturing method thereof Download PDF

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JP4135564B2
JP4135564B2 JP2003159888A JP2003159888A JP4135564B2 JP 4135564 B2 JP4135564 B2 JP 4135564B2 JP 2003159888 A JP2003159888 A JP 2003159888A JP 2003159888 A JP2003159888 A JP 2003159888A JP 4135564 B2 JP4135564 B2 JP 4135564B2
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groove
semiconductor substrate
thermal oxide
semiconductor
oxide film
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JP2004214596A (en
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和弘 鶴田
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Denso Corp
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
    • H01L21/76208—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region using auxiliary pillars in the recessed region, e.g. to form LOCOS over extended areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体基板およびその製造方法に関するものである。
【０００２】
【従来の技術】
携帯電話など小型無線情報機器の普及により、搭載される高周波回路の小型、低消費電力化、低コスト化のため、半導体基板に能動素子と受動素子を集積して、回路を１チップ化したモノリシックＩＣの開発が進んでいる。具体的には、半導体基板に、トランジスタ、ダイオード等の能動素子と、抵抗、キャパシタ、インダクタ等の受動素子を集積して、高周波の発振器、アンプ、フィルタ等の回路を１チップ化する。
【０００３】
しかしながら、半導体基板上にインダクタを形成する場合、非特許文献１に記載されているように、インダクタを構成する導電体と半導体基板との間に寄生容量及び寄生抵抗（渦電流損）が生じるという問題がある。従って、Ｑ値の高いインダクタを得るためには、寄生容量及び寄生抵抗を低減する必要がある。
【０００４】
この問題を解決する方法として非特許文献１では、半導体基板の表面のインダクタの下方に溝（空洞）を形成する方法を提案している。しかし、非特許文献１により開示された解決法には以下の２つの問題点がある。１つは、インダクタの下のシリコンをエッチングで取り除くプロセスは、従来のシリコンＬＳＩプロセスと相いれないものであることである。第２には、上述した構造では、インダクタを空中配線構造にしているため、十分な強度が得られないという問題である。
【０００５】
そこで、上述の問題を解決する手段として、特許文献１では、半導体基板の一部分に深さ２０μｍ以上の溝を形成し、その溝に絶縁物を充填し、その絶縁物上にインダクタ等の受動素子を形成することが提案されている。これにより、インダクタを構成する導電体と半導体基板との間の寄生容量及び寄生抵抗を低減しつつ、従来のシリコンＬＳＩプロセスとの融合を可能とし、しかも十分な強度が確保できる。
【０００６】
しかしながら、特許文献１で開示されている方法では、絶縁物は有機系の絶縁性流体を用いており、以下のような問題がある。通常、このような絶縁性流体は固体化する際、体積変化（体積収縮）が起こり、能動素子を形成するための半導体基板面と受動素子を形成するための絶縁物領域面を同程度の高さにしたり絶縁物領域表面を平坦にすることが困難であるとか、体積変化により基板に応力がかかり、基板が反るという問題がある。
【０００７】
また、非特許文献２，３においては次のような方法が開示されている。シリコン基板の一方の面側に深さ１０μｍ以上の複数の溝を形成する。そして、その溝と溝とで挟まれたシリコン基板の柱（壁）を熱酸化によって完全に酸化するとともに残った溝内に酸化物を堆積させ溝を埋めることで、シリコン基板に１０μｍ以上の厚い絶縁物領域を形成する。しかしながら、この方法においても、厚い絶縁物領域を形成した基板に能動素子を形成する場合の８００℃以上の熱処理を繰り返すと、同様な不具合が発生する。つまり、シリコン基板と酸化シリコンの熱膨張係数の違い（シリコン：２．５×１０-6／℃、酸化シリコン：０．５×１０-6／℃）によって、シリコン基板にストレスがかかり、シリコン基板が反る。また、シリコン基板内に結晶欠陥、転位が発生し、シリコン基板領域に形成した能動素子が動作不能になる。特に、厚い絶縁物領域近傍のシリコン基板領域には、結晶欠陥、転位が集中するため、能動素子が動作不能になるのを回避するには、能動素子を厚い絶縁物領域から一定の距離（例えば数十μｍ）離す必要があり、その部分がデッドスペースとなり、回路の集積度を悪化させることになる。
【０００８】
【特許文献１】
特開２００１−７７３１５号公報
【非特許文献１】
J.Y.C. Changらの論文“Large Suspended Inductors on Silicon and Their Use in a 2-μm CMOS RF Amplifier,”IEEE Electron Device Letters, Vol. 14, No.5, pp. 246-248 (1993)
【非特許文献２】
C.Zhangらの論文“FABRICATION OF THICK SILICON DIOXIDE LAYERS USING DRIE, OXIDATION AND TRENCH REFILL”, Technical Digest of The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, pp. 160-163 (2002)
【非特許文献３】
H. Jiangらの論文“REDUCING SILICON-SUBSTRATE PARASITICS OF ON-CHIP TRANSFORMERS”, Technical Digest of The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, pp. 649-652 (2002)
【０００９】
【発明が解決しようとする課題】
本発明はこのような背景の下になされたものであり、素子機能を十分に発揮させることができ、しかも十分な強度を得ることが可能な厚い絶縁物層を有し、かつ基板の反りや結晶欠陥、転位が発生しにくく、高い集積度の回路を実現可能な半導体基板およびその製造方法を提供することを目的としている。
【００１０】
【課題を解決するための手段】
請求項１に記載の半導体基板は、第１の素子が配置される部位において厚さ１０μｍ以上の熱酸化物層が形成されるとともに、当該熱酸化物層の外周面から内方において同外周面に沿って多結晶半導体を充填した溝が形成されており、多結晶半導体を充填した溝の深さが、熱酸化物層の厚さよりも大きいことを特徴としている。よって、この厚い熱酸化物層にて素子機能を十分に発揮させることができ（例えば、受動素子に対する寄生容量及び寄生抵抗を十分に低減することができ）、しかも第１の素子を空中配線構造としていないので十分な機械的強度を得ることが可能となる。また、熱酸化物層の外周面から内方において同外周面に沿って多結晶半導体を充填した溝を形成したので、多結晶半導体が第２の素子形成工程における熱ストレスの吸収層として働くため、基板の反りや結晶欠陥、転位の発生を抑制でき、第２の素子の動作不良を防止できる。これによりデッドスペースを少なくでき、高い集積度の回路を実現することができる。
【００１１】
また、多結晶半導体を充填した溝の深さが、熱酸化物層の厚さよりも大きいと、半導体基板に素子を形成する工程において、厚い熱酸化物層の領域下部まで効果的に前記熱ストレスを吸収できるので、基板の反りや結晶欠陥、転位の発生をさらに抑制することができる。
【００１２】
また、請求項２に記載のように、第１の素子は受動素子であり、第２の素子は能動素子であり、特に、請求項３に記載のように、受動素子は高周波を取り扱うものである場合に適用するとよい。
【００１３】
請求項４に記載の半導体基板の製造方法においては、半導体基板における第１の素子が配置される部位において、深さ１０μｍ以上の第１の溝と、この第１の溝を形成する領域の周囲に第１の溝の溝幅よりも大きな溝幅の第２の溝が同時に形成される。そして、熱酸化により第１および第２の溝の内面から酸化膜を成長させて第１の溝においては熱酸化膜によって埋設され、第２の溝においては側壁に熱酸化膜が第３の溝を残して形成される。さらに、第３の溝に多結晶半導体が充填される。これにより、請求項１に記載の半導体基板が得られる。
【００１４】
請求項５に記載の半導体基板の製造方法においては、半導体基板における第１の素子が配置される部位において、深さ１０μｍ以上の第１の溝が隣接して複数形成されるとともに第１の溝を形成する領域の周囲に第１の溝の溝幅よりも大きな溝幅の第２の溝が同時に形成される。そして、熱酸化により第１および第２の溝の内面から酸化膜を成長させて第１の溝においては熱酸化膜によって埋設されるとともに隣接する第１の溝の間が全て熱酸化膜とされ、第２の溝においては側壁に熱酸化膜が第３の溝を残して形成される。さらに、第３の溝に多結晶半導体が充填される。これにより、請求項１に記載の半導体基板が得られる。
【００１５】
この請求項４，５の発明によれば、第３の溝は、第１の溝の内部を酸化物で埋めていく時の酸化膜と半導体基板との熱膨張係数差に起因するストレスを吸収し、半導体基板部分に過大な応力が加わることが無いため、基板の反りを抑制することができる。
【００１６】
請求項６に記載のように、第１の溝と第２の溝を同時に形成する工程において、第２の溝の深さを第１の溝よりも深く形成することにより、請求項１に記載の半導体基板が得られる。この請求項６に記載の発明においては、基板製造プロセスにおいて、厚い酸化物層の領域下部まで効果的に酸化膜と半導体基板との熱膨張係数の差を吸収できるので、結晶欠陥、転位、基板（ウエハ）の反りの発生をさらに抑制することができる。
【００１７】
請求項７に記載のように、第３の溝に多結晶半導体を充填する工程は、半導体基板上に多結晶半導体を堆積させて第３の溝内に多結晶半導体を配した後、半導体基板の表面部に堆積した多結晶半導体を除去し、さらに、半導体基板の表面に残留した多結晶半導体を熱酸化する処理を含むようにする。このようにすると、熱酸化物層の表面部分の凹部を多結晶半導体で埋設して平坦化でき、さらにその後の熱酸化により凹部に残留した多結晶半導体が酸化され体積膨張するのでさらに表面が平坦化される。こうして形成された厚い熱酸化物層は表面が基板表面とほぼ同じ高さにすることができる。
【００１８】
請求項８に記載のように、第１の溝の溝幅を「Ｗ１」、第２の溝の溝幅を「Ｗ３」、半導体基板とその熱酸化物との熱膨張係数差を「Ａ」、熱酸化に伴なう第１の溝による熱酸化物層の最大幅を「Ｗ」、室温と最大熱酸化処理温度との温度差を「Ｔ」としたとき、
Ｗ３＞｛（Ａ・Ｗ・Ｔ）／２｝＋Ｗ１
を満足させると、第３の溝は、熱処理中の半導体とその酸化物の熱膨張率の違いによって基板の水平方向に発生する寸法差を吸収し、熱処理中に半導体基板に加わる応力を低減し、結晶欠陥、転位、基板（ウエハ）の反りの発生を抑制することができる。
【００１９】
請求項９に記載のように、第１の溝において、その溝幅に対する溝深さの寸法比であるアスペクト比が１０以上であると、一般的なＬＳＩ工程の範疇で形成できる膜厚１μｍ程度の熱酸化工程により、安価に深さ１０μｍ以上の厚い熱酸化物層を形成できる。
【００２０】
請求項１０に記載のように、第１の溝において、その溝幅に対する溝深さの寸法比であるアスペクト比が２０以上であると、安価に深さ２０μｍ以上の厚い熱酸化物層を形成でき、化合物半導体基板のように半絶縁性の基板上に形成した伝送線路並みの損失低減効果を得ることが可能となる。
【００２１】
請求項１１に記載のように、第１の溝において、その溝幅が１μｍ以下であると、第３の溝の側壁の酸化膜は１μｍ以下となり、より安価に厚い熱酸化物層を形成できるとともに、第２の素子形成領域の結晶欠陥の発生をより抑制できる。
【００２２】
請求項１２に記載のように、半導体基板としてＳＯＩ基板を用い、第１および第２の溝を形成する際に同溝がＳＯＩ基板の埋め込み酸化膜層に達していると、第２の素子形成過程の熱ストレスを溝および多結晶半導体に集中させることができ、第２の素子が形成される半導体基板領域の結晶欠陥、転位の発生をさらに抑制でき、第２の素子の動作不良を防止できる。
【００２３】
請求項１３に記載のように、第１の素子は受動素子であり、第２の素子は能動素子であり、特に、請求項１４に記載のように、受動素子は高周波を取り扱うものである場合に適用するとよい。
【００２４】
【発明の実施の形態】
以下、この発明を具体化した一実施の形態を図面に従って説明する。
本実施形態においては、図１，２に示す半導体基板１００を使用している。図１は半導体基板１００の縦断面図であり、図２は半導体基板１００の平面図である。図１に示すように、シリコン基板１の一方の表面側（素子形成面側）においてその一部領域に厚い熱酸化物層２が形成されている。熱酸化物層２は図２に示すように、四角形状をなしている。図１，２に示すように、熱酸化物層２の内部には溝３が形成され、この溝３は熱酸化物層２の外周面２ａから内方において同外周面２ａに沿って延びている。つまり、溝３は平面形状として四角環状をなしている。この溝３には多結晶シリコン（多結晶半導体）４が充填されている。即ち、熱酸化物層２の内部において熱酸化物層２の外周面２ａの近傍には多結晶シリコンによる壁（４）が埋設されている。
【００２５】
この半導体基板１００を用いて図３に示す高周波モノリシックＩＣを形成している。つまり、本実施の形態においては半導体装置として高周波モノリシックＩＣに具体化しており、図３には高周波モノリシックＩＣの一部分での縦断面図を示す。このモノリシックＩＣでの半導体基板１００において、厚い熱酸化物層２がその上に受動素子を配置するための絶縁物となる。
【００２６】
図３では、半導体基板１００に対し能動素子としてのトランジスタＱ１，Ｑ２と、受動素子としてのインダクタ５を集積化しており、高周波の発振器、アンプ、フィルタ等の回路を１チップ化している。
【００２７】
詳しくは、図３において、シリコン基板１上における受動素子形成領域Ａ１には１０μｍ以上の厚さの熱酸化物層２が形成されており、その上には、受動素子であるスパイラルインダクタ５が形成されている。高周波回路等においてはスパイラルインダクタ５の直下では強い電磁波が発生するため、熱酸化物層２の厚さｔ１は１０μｍ以上であることが好ましく、本例では３０μｍとしている。熱酸化物層２を構成するシリコン熱酸化膜は、比誘電率が「３．９」程度である。スパイラルインダクタ５は金属材料を用いて形成されており、本例では配線材料でもあるアルミ（Ａｌ）を用いている。ただし、材料はアルミ（Ａｌ）に限ったものではなく、Ｃｕ、Ａｕ等を用いてもよい。一方、シリコン基板１上における能動素子形成領域Ａ２には、ＮチャネルＭＯＳトランジスタＱ１とＰチャネルＭＯＳトランジスタＱ２が形成されている。
【００２８】
図４は、酸化膜上に配置される配線（信号線路）に印加される周波数ｆを２ＧＨｚとしたときの、信号の伝送損失と酸化膜厚との関係を示したシミュレーション結果である。シミュレーションでは、シリコン基板の比抵抗を４Ω・ｃｍ、線路の材料をアルミ（Ａｌ）、厚さを１μｍ、幅を５０μｍ、グランド配線との間隔を３０μｍ、全長を１ｍｍとした。
【００２９】
図４から次のことが分かる。酸化膜厚が厚いほど伝送損失は小さくなるが、酸化膜厚が１０μｍ以上であると、酸化膜厚１μｍのときの１０分の１程度にできる。また、酸化膜厚が２０μｍ以上でほぼ損失は飽和している。損失が飽和する酸化膜厚は、信号の周波数、線路の抵抗値、寸法で異なってくるが、１００ＭＨｚ以上の高周波領域において、厚い酸化膜による伝送損失低減効果を十分に得るためには酸化膜の膜厚を１０μｍ以上にすることが好ましい。さらに、酸化膜厚が２０μｍ以上であれば、化合物半導体基板のように半絶縁性の基板上に形成した伝送線路並みの損失低減効果が得られる。
【００３０】
次に、モノリシックＩＣの製造プロセスを、図５，６，７，８を用いて説明する。
まず、図５（ａ）に示すように、シリコン基板１を用意し、その上面に酸化膜（ＳｉＯ2）２０を形成する。さらに、図５（ｂ）に示すように、酸化膜２０上にフォトレジスト（符号２１で示す部材）を塗布する。そして、所定領域つまり受動素子形成領域Ａ１での厚い熱酸化物層の形成予定領域に、幅１μｍ以下、例えば０．８μｍの縞状の溝パターン２２とその周囲の幅１μｍ以上、例えば１．６μｍの溝パターン２３を露光して開口させる。この時、開口した溝パターン２２の間の幅Ｗ２は、溝パターン２２の幅（開口部の幅）Ｗ１の８１．８％程度に設定する。例えば、溝パターン２２の幅（溝幅）Ｗ１が０．８μｍであれば溝パターン２２間の幅（溝間隔）Ｗ２を０．６５μｍ程度に設定する。
【００３１】
そして、図５（ｃ）に示すように、前記溝パターン２２，２３で、酸化膜２０をエッチングした後、レジスト２１を除去することで、酸化膜２０によるマスクを形成する。これにより、シリコン基板１の溝が形成されるべき部分が露出した状態となる。
【００３２】
引き続き、図６（ａ）および図８の平面図に示すように、シリコン基板１における受動素子５が配置される部位（Ａ１）において、深さ１０μｍ以上の第１の溝２４を隣接して複数形成するとともに第１の溝２４を形成する領域の周囲に第１の溝２４の溝幅Ｗ１よりも大きな溝幅Ｗ３の第２の溝２５を同時に形成する。広義には、シリコン基板１における受動素子５が配置される部位（Ａ１）において、深さ１０μｍ以上の第１の溝２４と、この第１の溝２４を形成する領域の周囲に第１の溝２４の溝幅Ｗ１よりも大きな溝幅Ｗ３の第２の溝２５を同時に形成する。詳しくは次のようにする。
【００３３】
異方性エッチングを用いて、シリコン基板１をエッチングして、溝２４，２５を同時に形成する。第１の溝２４の幅Ｗ１は１μｍ以下であり、第２の溝２５の幅Ｗ３は１μｍ以上であり、前述したように溝２４，２５の深さＬ１は１０μｍ以上である。溝形成の際に、フッ素系ガスを用いた反応性イオンエッチング、特に高密度プラズマエッチングによる異方性エッチングを用いる。これにより、基板１に対してほぼ垂直な側面を有するアスペクト比（Ｌ１／Ｗ１）が「１０」以上の深い溝を形成することができる。また、特開２０００−２９９３１０号公報に開示されているエッチング方法を用いることにより、アスペクト比が「２０」以上の深い溝を形成することも可能であり、幅１μｍ以下の溝幅であっても、深さは２０μｍ以上のほぼ垂直な溝を形成することができる。また、この時、シリコン基板１における縞状の溝２４の間のシリコン材料２６は、その幅（厚さ）Ｗ２が溝幅Ｗ１の８１．８％程度であり、高さが１０μｍ以上の薄板状になる。
【００３４】
そして、図６（ｂ）に示すように、熱酸化により第１および第２の溝２４，２５の内面から酸化膜２７を成長させて第１の溝２４においては熱酸化膜２７によって埋設するとともに隣接する第１の溝２４の間を全て熱酸化膜２７とし、第２の溝２５においては側壁に熱酸化膜２７を第３の溝３を残して形成する。広義には、熱酸化により第１および第２の溝２４，２５の内面から酸化膜２７を成長させて第１の溝２４においては熱酸化膜２７によって埋設し、第２の溝２５においては側壁に熱酸化膜２７を第３の溝３を残して形成する。詳しくは次のようにする。
【００３５】
シリコン基板１をウェットＯ2、スチームＯ2、Ｈ2およびＯ2混合燃焼気体中等の水素を含む酸化性雰囲気で酸化処理をする。この際、溝２４，２５内のシリコン基板１は酸化が進行していく時、酸化膜厚の４５％に相当する厚さ分、基板内部のシリコン層が酸化シリコン化し、酸化膜厚の５５％に相当する厚さ分、酸化前のシリコン基板側面より外側に膨張する。従って、酸化が進行するにつれて、縞状パターンの溝２４は酸化シリコン（熱酸化膜２７）で埋められていき、溝２４の両側の側壁に成長した酸化膜２７が互いに接触すると、その酸化膜同士で結合ができて、溝２４内は酸化シリコン（熱酸化膜２７）で完全に埋設できる。例えば、溝２４の幅Ｗ１が０．８μｍの場合では、膜厚０．７３μｍ程度の酸化膜を成長させるのに相当する酸化処理を行うことで埋設できる。
【００３６】
このような膜厚１μｍ以下の酸化膜２７を成長させる酸化処理は通常のＬＳＩ製作工程で用いられており、１０００℃以上、数時間の酸化工程で特殊な工程を必要とせず、従来技術（特許文献１）よりも安価に厚い酸化物層を形成できる。逆に、酸化膜厚２μｍ以上を必要とする場合には、１０時間以上の酸化工程が必要となり、コスト高になるとともに、シリコン領域の結晶欠陥の発生が増加することになる。また、溝幅Ｗ１がさらに小さければ、この酸化処理はさらに短時間にでき、低コストになるとともに、最外周に形成される酸化膜厚を薄くでき、シリコン領域の結晶欠陥の発生をより抑制できる。
【００３７】
なお、溝２４での側面に成長した酸化膜２７が互いに接触し、酸化膜同士で結合が形成される過程においては、水素の関与が必要であるため、上記のような水素を含む酸化性雰囲気での処理を行っている。しかし、この水素を含む酸化性雰囲気は酸化膜が互いに接触する直前から溝２４が酸化物で完全に埋設されるまでの間のみで、それ以外の時間は水素を含まないドライＯ2等の酸化性雰囲気であってもよい。縞状の溝２４が形成された領域内の薄板状シリコン材料２６は幅（板厚）Ｗ２が溝幅Ｗ１の８１．８％程度の場合には、溝２４の内部が酸化物で完全に埋設されると同時に、すべて酸化され、酸化シリコン化するため、縞状の溝２４を形成した領域全域に渡り、厚さが１０μｍ以上の厚い熱酸化物層２が形成できる。
【００３８】
また、厚い熱酸化物層２における基板表面付近では、酸化が基板１の表面（水平方向）とは直交する方向に進行するため、はじめにシリコンがあった部分はもり上がった状態になるため、微小な凹凸がある状態になっている。
【００３９】
さらに、第２の溝２５は第１の溝２４よりも溝幅が大きいため第２の溝２５での熱酸化により第３の溝３が残った状態となり、その溝幅Ｓは、初期の溝幅（第２の溝２５の幅）Ｗ３が１．６μｍで、Ｗ１＝０．８μｍの場合においては０．８μｍ程度となる。
【００４０】
この第３の溝３は、熱処理中のシリコンと酸化シリコンの熱膨張率の違いによって基板の水平方向に発生する寸法差を吸収する。つまり、溝２４の内部を酸化物で埋めていく時の酸化膜とシリコン基板との熱膨張係数の差を吸収する。これにより、熱処理中にシリコン基板１に加わる応力を低減し、結晶欠陥、転位、基板（ウエハ）の反りの発生を抑制することができる。
【００４１】
この寸法差について具体的には、シリコンと酸化シリコンとの熱膨張係数差Ａ（２．５×１０-6−０．５×１０-6＝２．０×１０-6／℃）と、熱酸化に伴なう第１の溝２４による熱酸化物層２の最大幅Ｗと、図６（ｂ）の酸化処理での室温と最大酸化処理温度との温度差Ｔとの積（Ａ×Ｗ×Ｔ）で計算される。例えば、Ｗ＝３００μｍ、Ｔ＝１１００℃では、Ａ＝２．０×１０-6／℃であるので、０．６６μｍの寸法差が生じる。従って、第２の溝２５の酸化処理後の溝幅、即ち、第３の溝３の溝幅Ｓは少なくとも０．３３（＝０．６６／２）μｍ以上残るようにしておく必要がある。
【００４２】
このように、第１の溝２４の溝幅を「Ｗ１」、第２の溝２５の溝幅を「Ｗ３」、シリコン基板とその熱酸化物との熱膨張係数差を「Ａ」、熱酸化に伴なう第１の溝２４による熱酸化物層の最大幅を「Ｗ」、室温と最大熱酸化処理温度との温度差を「Ｔ」としたとき、
Ｗ３＞｛（Ａ・Ｗ・Ｔ）／２｝＋Ｗ１
を満足させる。これにより、第３の溝３は、熱処理中のシリコンとその酸化物の熱膨張率の違いによって基板の水平方向に発生する寸法差を吸収し、熱処理中にシリコン基板１に加わる応力を低減し、結晶欠陥、転位、基板（ウエハ）の反りの発生を抑制することができることとなる。即ち、第３の溝３は、第１の溝２４の内部を酸化物で埋めていく時の熱酸化物層とシリコン基板との熱膨張係数差に起因するストレスを吸収し、シリコン基板部分に過大な応力が加わることが無いため、基板１の反りを抑制することができる。
【００４３】
なお、本工程の酸化処理は、図５（ａ）で形成した酸化膜（マスク材）２０を残した状態で行った例を示したが、図６（ｂ）の酸化処理の前に、酸化膜（マスク材）２０をエッチングして除去した後に、酸化処理を行ってもよい。また、酸化膜（マスク材）２０が窒化膜を含む膜でもよく、その場合、マスク材（２０）を残して図６（ｂ）の酸化処理を行うと、溝２４，２５の内面のみに酸化膜を成長させることができ、厚い熱酸化物層２の表面の凹凸を小さくできる。
【００４４】
また、図６（ａ）の溝形成工程の後では、エッチング条件によっては、形成された溝２４，２５の表面がエッチング時のダメージにより微小な凹凸ができていたり、溝２４，２５の最上部の角部が鋭角になり、図６（ｂ）の工程において溝面での酸化膜の成長が不均一になり、溝２４内が酸化物で完全に埋設されず、空洞が残る場合がある。この空洞は、後工程のＬＳＩプロセスに支障が無ければそのままでもよいが、場合によっては空洞にプロセス途中の薬液が残留して汚染源になったり、熱処理中に膨張して破損したりする危険性があるため、犠牲酸化工程などの溝が酸化物で埋まり易い形状に溝を整形する工程を追加してもよい。また、熱処理温度は９６５℃以上が好ましく、この温度以上では、酸化工程中の酸化膜の粘性流動の効果により、シリコン基板１に対して低応力で酸化膜２７が形成されるとともに、溝２４への酸化物の埋め込み性がよくなる。
【００４５】
また、図６（ｂ）の酸化処理において、溝２４，２５のアスペクト比が大きい場合には、溝２４，２５内に充填されている酸化処理前の雰囲気（例えば空気や窒素、アルゴンといった不活性雰囲気）が充満しているため、溝底部まで酸化性雰囲気が行き渡らず、酸化が進行しない場合がある。その場合には、図６（ｂ）の酸化処理前に基板を真空中に挿入した後、酸素雰囲気中に挿入し、溝２４，２５内に酸素を充満させるとよい。
【００４６】
次に、図６（ｃ），図７（ａ），（ｂ）に示す工程を経て第３の溝３に多結晶シリコン４を充填する。まず、図６（ｃ）に示すように、シリコン基板１上に例えばＬＰ−ＣＶＤ法等により、多結晶半導体である多結晶シリコン２８を１μｍ程度堆積して、第３の溝３内に多結晶シリコンを配する（埋設する）。また、厚い熱酸化物層２の表面の凹凸も多結晶シリコンを堆積（凹部に多結晶シリコンを埋設）させることでほぼ平坦化することができる。さらに、溝２４内が酸化物で完全に埋設されず、表面に開口する空洞が残る場合においても、多結晶シリコンは空洞を埋めることができ、プロセス途中の汚染や基板の破損の危険性を排除する効果もある。
【００４７】
引き続き、シリコン基板１の表面部に堆積した多結晶シリコン２８を、図７（ａ）に示すように、例えば反応性イオンエッチング法等により厚い熱酸化物層形成予定領域以外の表面の酸化膜が露出するまでエッチング除去する。これによって、表面の余剰な多結晶シリコン２８が除去され、厚い熱酸化物層２の表面の凹部と、その外周側の溝３のみに多結晶シリコンが残る形になる。
【００４８】
次に、図７（ｂ）に示すように、シリコン基板１に対し厚い熱酸化物層２の表面近傍の凹部に残った多結晶シリコンを酸化処理する。つまり、シリコン基板１の表面に残留した多結晶シリコン（２８）を熱酸化する。このような工程を経て、所定領域に１０μｍ以上の厚い熱酸化物層（厚い絶縁物層）２が形成される。また、厚い熱酸化物層２の表面部分の凹部に残留した多結晶シリコンが酸化されるとき体積膨張するのでさらに表面が平坦化される。こうして形成された厚い熱酸化物層２は、表面がシリコン基板面とほぼ同じ高さであるとともに、凹部に埋設された多結晶シリコンはほとんど酸化することが可能であるため、熱酸化物層２での表面が平坦でかつ１０μｍ以上の厚さを有することとなる。
【００４９】
以上のように形成された１０μｍ以上の厚い熱酸化物層２の表面は、ほぼ平坦で、十分な機械的強度を有している。そのため、この半導体基板に対して、通常のＬＳＩプロセスを用いて図３に示すようにモノリシックＩＣ、即ち、シリコン基板１に能動素子Ｑ１，Ｑ２（ＭＯＳトランジスタ）を、熱酸化物層２上に受動素子（スパイラルインダクタ）５を形成することができる。つまり、シリコン基板１の表層部にＰウェル領域６とＮウェル領域７を形成するとともに、Ｐウェル領域６上においてゲート絶縁膜を介してゲート電極８を配置し、さらに、ソース領域９とドレイン領域１０を形成する。同様に、Ｎウェル領域７上においてゲート絶縁膜を介してゲート電極１１を配置するとともに、ソース領域１２とドレイン領域１３を形成する。その後、受動素子（スパイラルインダクタ）５を含む金属配線、さらに基板表面にパッシベーション膜１４を形成する。
【００５０】
ここで、通常のＬＳＩプロセス、特に能動素子形成過程では、８００℃以上の高温の熱処理工程が多数繰り返されるが、その時のシリコンと酸化シリコンの熱膨張率の違いによって基板の水平方向に発生する寸法差を多結晶シリコン４が歪むことで吸収することができる。これにより、熱処理過程にシリコン基板１に加わる応力を低減し、結晶欠陥、転位、基板（ウエハ）の反りの発生を抑制することができる。そして、シリコン基板１を低結晶欠陥、低転位にできることから能動素子の動作不良を回避でき、能動素子を熱酸化物層２に近い位置に形成できデッドスペースが少なく高い集積度の高周波モノリシックＩＣを実現できる。また、既存のＬＳＩの製造プロセスを変更することなく素子を形成でき、安く、大量生産に向く高性能の高周波モノリシックＩＣを実現できる。
【００５１】
このように本実施形態においては、図３での半導体基板１００は、第１の素子としての受動素子５（高周波を取り扱う素子）を絶縁物の上に配置するとともに第２の素子としての能動素子Ｑ１，Ｑ２を作り込んだ半導体装置に用いるための半導体基板であって、受動素子５が配置される部位（Ａ１）において厚さ１０μｍ以上の熱酸化物層２が形成されるとともに、当該熱酸化物層２の外周面２ａから内方において同外周面２ａに沿って多結晶シリコン４を充填した溝３が形成されている。よって、この厚い熱酸化物層２にて素子機能を十分に発揮させることができる。具体的には、受動素子（スパイラルインダクタ）５に対する寄生容量及び寄生抵抗を十分に低減することができる。しかも受動素子５を空中配線構造としていないので十分な機械的強度を得ることが可能となる。また、熱酸化物層２の外周面２ａから内方において同外周面２ａに沿って多結晶シリコン４を充填した溝３を形成したので、多結晶シリコン４が能動素子Ｑ１，Ｑ２の形成工程における熱ストレスの吸収層として働くため、基板の反りや結晶欠陥、転位の発生を抑制でき、能動素子Ｑ１，Ｑ２の動作不良を防止できる。これによりデッドスペースを少なくでき、高い集積度の回路を実現することができる。
【００５２】
また、図６（ａ）での第１の溝２４において、その溝幅Ｗ１に対する溝深さＬ１の寸法比であるアスペクト比（Ｌ１／Ｗ１）が１０以上であると、一般的なＬＳＩ工程の範疇で形成できる膜厚１μｍ程度の熱酸化工程により、安価に深さ１０μｍ以上の厚い熱酸化物層２を形成できる。また、第１の溝２４において、その溝幅Ｗ１に対する溝深さＬ１の寸法比であるアスペクト比（Ｌ１／Ｗ１）が２０以上であると、安価に深さ２０μｍ以上の厚い熱酸化物層２を形成でき、化合物半導体基板のように半絶縁性の基板上に形成した伝送線路並みの損失低減効果が得られる。
【００５３】
また、第１の溝２４において、その溝幅Ｗ１が１μｍ以下であると、第３の溝３の側壁の酸化膜は１μｍ以下となり、より安価に厚い熱酸化物層２を形成できるとともに、第２の素子形成領域の結晶欠陥の発生をより抑制できる。
【００５４】
また、図６（ａ）における溝２４，２５の形成工程において、エッチングの条件によっては溝深さは溝幅が広いところほど深くすることができる。これを利用して、図６（ａ）に代わる図９（ａ）に示すように第１の溝２４と第２の溝２５を同時に形成する工程において、第２の溝２５の深さＬ１１を第１の溝２４よりも深く形成する。そして、図９（ｂ），（ｃ）に示すように、熱酸化および多結晶シリコン２８のデポを行う。この工程を経ることにより、図１０に示すように、第３の溝３に充填した多結晶シリコン４の深さＬ１２が、第１の溝２４を熱酸化して埋めて形成した熱酸化物層２の厚さｔ１よりも大きくなるようにしてもよい。つまり、多結晶シリコン４を充填した溝３の深さＬ１２が、熱酸化物層２の厚さｔ１よりも大きくなるようにしてもよい。詳しくは、溝３の深さＬ１２を、熱酸化物層２における溝３を形成した部位以外での厚さｔ１よりも大きくする。これにより、半導体基板１００に素子を形成する工程（ＬＳＩプロセス）において、厚い熱酸化物層２の領域下部まで効果的に熱ストレス（酸化膜とシリコン基板との熱膨張係数の差）を吸収できるので、基板内部の結晶欠陥、転位の発生、基板（ウエハ）の反りの発生をさらに抑制することができる。また、図９（ａ）の第２の溝２５の深さＬ１１が第１の溝２４よりも深いと、半導体基板１００の製造工程において、厚い熱酸化物層２の領域下部まで効果的に酸化膜とシリコン基板との熱膨張係数の差を吸収できるので、結晶欠陥、転位、基板（ウエハ）の反りの発生をさらに抑制することができる。
【００５５】
これまでの説明においては一般的なシリコン基板を用いた場合を示したが、基板としては、図１１に示すように、ＳＯＩ（Silicon On Insulator）基板２００を用いてもよい。図１１において、シリコン基板２０１の上に厚さ１μｍ程度の酸化膜層２０２を介して厚さ１０μｍ以上の単結晶シリコン層２０３が形成されている。また、単結晶シリコン層２０３の一部領域において熱酸化物層２が形成され、この熱酸化物層２は埋め込み酸化膜層２０２に達している。そのためには、図６（ａ）の工程の際に溝２４，２５が埋め込み酸化膜層２０２に達するまでエッチングする。即ち、溝形成工程においてＳＯＩ基板の埋め込み酸化膜層２０２に達する溝２４，２５を形成する。これにより、熱酸化物層形成予定領域のシリコン層とそれ以外の領域のシリコン層とが完全に酸化物で分離できる。そのため、その後の厚い熱酸化物層形成工程や能動素子形成過程の熱ストレスを外周部の溝３および多結晶シリコン４に集中させることができ、能動素子が形成されるシリコン基板領域の結晶欠陥、転位の発生をさらに抑制でき、能動素子の動作不良を防止できる。より具体的には、図３においては熱酸化物層２の下面部において欠陥が発生した場合には左右方向に広がっていき、能動素子形成領域でのトランジスタＱ１，Ｑ２に悪影響を及ぼす可能性がある。これに比べ、図１１において埋め込み酸化膜層２０２の存在によりそのようなことが回避される。
【００５６】
また、これまでの説明においてはトランジスタを能動素子とし、インダクタを受動素子とした場合について述べてきたが、ダイオード等を能動素子としたり、金属配線、抵抗、キャパシタ等を受動素子とした場合に適用してもよい。
【００５７】
なお、図２，８においては、厚い熱酸化物層２のパターンを四角形状としているが、そのパターンは四角形状に限らず、どのようなパターンでもよい。具体的には、例えば、図１２に示すように円形であっても、図１３に示すように複雑な多角形等であってもよい。あるいは、図１４に示すように、シリコン基板１において平面構造として熱酸化物層２が四角環状に形成されていてもよい。つまり、四角環状の熱酸化物層２の周りに単結晶シリコン１ａが存在するとともに四角環状の熱酸化物層２の内側に単結晶シリコン島１ｂが存在するパターンでもよい。この場合には、熱酸化物層２と単結晶シリコン領域（１ａ，１ｂ）との境界部分において、その熱酸化物層２の外周面２ａから内方において同外周面２ａに沿って多結晶シリコン４を充填した溝３が形成されている。
【００５８】
さらに、これまでの説明においては、本発明による半導体基板を高周波モノリシックＩＣに適用した例で説明した。つまり、第１の素子としての受動素子（インダクタ）５を熱酸化物層２の上に配置するとともに、第２の素子としての能動素子（トランジスタ）Ｑ１，Ｑ２を作り込んだ半導体装置に用いるための半導体基板であった。これに限らず、以下のようにしてもよい。
【００５９】
例えば、１ＧＨｚ以上のクロック周波数のマイクロプロセッサ用のＩＣに適用する。具体的には、シリコン層に第２の素子としてのマイクロプロセッサ構成素子（トランジスタ等）を作り込むとともに熱酸化物層２の上に第１の素子として配線材を配する。
【００６０】
あるいは、１０００ボルト以上の高耐圧を必要とするパワー素子を具備するＩＣに適用する。具体的には、シリコン層に第２の素子としてパワー素子を作り込むとともに熱酸化物層２にて素子分離を図り、かつ、熱酸化物層２の上に第１の素子として配線材を配する。この場合には、厚い熱酸化物層２により耐電圧性を向上させることができる。
【００６１】
あるいは、基板に対して熱絶縁が必要なセンサ素子を具備するＩＣに適用する。具体的には、熱酸化物層２の上に第１の素子としてセンサ素子を配するとともに、その横のシリコン層に第２の素子としてのセンサ信号処理回路構成素子（アンプ構成素子、Ａ／Ｄ変換素子）を作り込む。この場合には、厚い熱酸化物層２により熱遮断性を向上させることができる。
【図面の簡単な説明】
【図１】実施の形態における半導体基板の縦断面図。
【図２】半導体基板の平面図。
【図３】実施の形態におけるモノリシックＩＣの一部分を示す縦断面図。
【図４】信号の伝送損失と酸化膜厚についてのシミュレーション結果を示す図。
【図５】（ａ），（ｂ），（ｃ）はモノリシックＩＣの製造プロセスを示す断面図。
【図６】（ａ），（ｂ），（ｃ）はモノリシックＩＣの製造プロセスを示す断面図。
【図７】（ａ），（ｂ）はモノリシックＩＣの製造プロセスを示す断面図。
【図８】モノリシックＩＣの製造プロセスを示す平面図。
【図９】（ａ），（ｂ），（ｃ）は製造プロセスを示す断面図。
【図１０】半導体基板の縦断面図。
【図１１】ＳＯＩ基板に適用した場合のモノリシックＩＣの一部分を示す縦断面図。
【図１２】半導体基板の平面図。
【図１３】半導体基板の平面図。
【図１４】半導体基板を示す図。
【符号の説明】
１…シリコン基板、２…熱酸化物層、３…溝（第３の溝）、４…多結晶シリコン、５…受動素子（第１の素子）、２４…第１の溝、２５…第２の溝、２６…シリコン材料、２８…多結晶シリコン、２００…ＳＯＩ基板、２０２…埋め込み酸化膜層、Ａ１…受動素子形成領域、Ｑ１，Ｑ２…能動素子。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor substrate and a manufacturing method thereof.
[0002]
[Prior art]
Due to the spread of small wireless information devices such as mobile phones, monolithic circuits that integrate active elements and passive elements on a semiconductor substrate to reduce the size, power consumption, and cost of high-frequency circuits mounted on a single chip. IC development is progressing. Specifically, active elements such as transistors and diodes and passive elements such as resistors, capacitors, and inductors are integrated on a semiconductor substrate to form circuits such as high-frequency oscillators, amplifiers, and filters on a single chip.
[0003]
However, when the inductor is formed on the semiconductor substrate, as described in Non-Patent Document 1, parasitic capacitance and parasitic resistance (eddy current loss) are generated between the conductor constituting the inductor and the semiconductor substrate. There's a problem. Therefore, in order to obtain an inductor having a high Q value, it is necessary to reduce parasitic capacitance and parasitic resistance.
[0004]
As a method for solving this problem, Non-Patent Document 1 proposes a method of forming a groove (cavity) below the inductor on the surface of the semiconductor substrate. However, the solution disclosed by Non-Patent Document 1 has the following two problems. One is that the process of removing the silicon under the inductor by etching is incompatible with the conventional silicon LSI process. Second, in the above-described structure, the inductor has an aerial wiring structure, so that sufficient strength cannot be obtained.
[0005]
Therefore, as means for solving the above-mentioned problem, in Patent Document 1, a groove having a depth of 20 μm or more is formed in a part of a semiconductor substrate, an insulator is filled in the groove, and a passive element such as an inductor is formed on the insulator. Has been proposed to form. As a result, the parasitic capacitance and parasitic resistance between the conductor constituting the inductor and the semiconductor substrate can be reduced, and fusion with the conventional silicon LSI process can be achieved, and sufficient strength can be secured.
[0006]
However, the method disclosed in Patent Document 1 uses an organic insulating fluid as the insulator, and has the following problems. Usually, when such an insulating fluid is solidified, a volume change (volume contraction) occurs, and the surface of the semiconductor substrate for forming the active element and the surface of the insulator region for forming the passive element are of the same level. In addition, there is a problem that it is difficult to flatten the surface of the insulating region or that the substrate is warped due to volume change and the substrate is warped.
[0007]
Non-Patent Documents 2 and 3 disclose the following methods. A plurality of grooves having a depth of 10 μm or more are formed on one surface side of the silicon substrate. Then, the silicon substrate pillar (wall) sandwiched between the grooves is completely oxidized by thermal oxidation, and oxide is deposited in the remaining grooves to fill the grooves, so that the silicon substrate has a thickness of 10 μm or more. An insulator region is formed. However, even in this method, if the heat treatment at 800 ° C. or higher in the case where an active element is formed on a substrate on which a thick insulating region is formed, the same problem occurs. That is, the difference in thermal expansion coefficient between the silicon substrate and silicon oxide (silicon: 2.5 × 10 -6 / ° C., silicon oxide: 0.5 × 10 -6 / ° C) stresses the silicon substrate and warps the silicon substrate. In addition, crystal defects and dislocations occur in the silicon substrate, and the active elements formed in the silicon substrate region become inoperable. In particular, crystal defects and dislocations are concentrated in the silicon substrate region in the vicinity of the thick insulator region. Therefore, to prevent the active device from becoming inoperable, the active device is separated from the thick insulator region by a certain distance (for example, Several tens of μm), which is a dead space, and deteriorates the degree of circuit integration.
[0008]
[Patent Document 1]
JP 2001-77315 A
[Non-Patent Document 1]
JYC Chang et al., “Large Suspended Inductors on Silicon and Their Use in a 2-μm CMOS RF Amplifier,” IEEE Electron Device Letters, Vol. 14, No. 5, pp. 246-248 (1993)
[Non-Patent Document 2]
C. Zhang et al. “FABRICATION OF THICK SILICON DIOXIDE LAYERS USING DRIE, OXIDATION AND TRENCH REFILL”, Technical Digest of The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, pp. 160-163 (2002)
[Non-Patent Document 3]
H. Jiang et al. "REDUCING SILICON-SUBSTRATE PARASITICS OF ON-CHIP TRANSFORMERS", Technical Digest of The Fifteenth IEEE International Conference on Micro Electro Mechanical Systems, pp. 649-652 (2002)
[0009]
[Problems to be solved by the invention]
The present invention has been made under such a background, and has a thick insulating layer that can sufficiently exhibit the element function and can obtain sufficient strength, and warps the substrate. It is an object of the present invention to provide a semiconductor substrate and a method for manufacturing the same, which are less likely to cause crystal defects and dislocations and can realize a highly integrated circuit.
[0010]
[Means for Solving the Problems]
The semiconductor substrate according to claim 1, wherein a thermal oxide layer having a thickness of 10 μm or more is formed at a portion where the first element is disposed, and the outer peripheral surface is inward from the outer peripheral surface of the thermal oxide layer. A groove filled with polycrystalline semiconductor is formed along The depth of the groove filled with the polycrystalline semiconductor is greater than the thickness of the thermal oxide layer. It is characterized by. Therefore, the element function can be sufficiently exhibited by the thick thermal oxide layer (for example, the parasitic capacitance and the parasitic resistance with respect to the passive element can be sufficiently reduced), and the first element is formed in the air wiring structure. Therefore, sufficient mechanical strength can be obtained. Further, since the groove filled with the polycrystalline semiconductor is formed along the outer peripheral surface inward from the outer peripheral surface of the thermal oxide layer, the polycrystalline semiconductor functions as a heat stress absorbing layer in the second element forming step. Further, the occurrence of substrate warpage, crystal defects, and dislocations can be suppressed, and malfunction of the second element can be prevented. As a result, the dead space can be reduced and a highly integrated circuit can be realized.
[0011]
Also If the depth of the groove filled with the polycrystalline semiconductor is larger than the thickness of the thermal oxide layer, the thermal stress is effectively applied to the lower portion of the thick thermal oxide layer in the step of forming an element on the semiconductor substrate. Since it can absorb, generation | occurrence | production of the curvature of a board | substrate, a crystal defect, and a dislocation can further be suppressed.
[0012]
Ma Claim 2 The first element is a passive element and the second element is an active element, in particular, 3 As described in the above, the passive element is preferably applied in the case of handling a high frequency.
[0013]
Claim 4 In the method for manufacturing a semiconductor substrate described in (1), a first groove having a depth of 10 μm or more and a first groove around a region where the first groove is formed in a portion where the first element is disposed in the semiconductor substrate. A second groove having a groove width larger than the groove width of the first groove is simultaneously formed. Then, an oxide film is grown from the inner surfaces of the first and second grooves by thermal oxidation, and the first groove is buried with the thermal oxide film, and in the second groove, the thermal oxide film is formed on the side wall of the third groove. Formed leaving. Further, the third groove is filled with a polycrystalline semiconductor. Thereby, the semiconductor substrate according to claim 1 is obtained.
[0014]
Claim 5 In the method for manufacturing a semiconductor substrate described in (1), a plurality of first grooves having a depth of 10 μm or more are formed adjacent to each other at a portion where the first element is disposed on the semiconductor substrate, and the first grooves are formed. A second groove having a groove width larger than that of the first groove is simultaneously formed around the region. Then, an oxide film is grown from the inner surfaces of the first and second grooves by thermal oxidation, and the first groove is buried with the thermal oxide film, and the space between the adjacent first grooves is all the thermal oxide film. In the second groove, a thermal oxide film is formed on the side wall leaving the third groove. Further, the third groove is filled with a polycrystalline semiconductor. Thereby, the semiconductor substrate according to claim 1 is obtained.
[0015]
This claim 4 , 5 According to the invention, the third groove absorbs stress caused by a difference in thermal expansion coefficient between the oxide film and the semiconductor substrate when the inside of the first groove is filled with the oxide, and the semiconductor substrate portion Since excessive stress is not applied, warping of the substrate can be suppressed.
[0016]
Claim 6 In the step of simultaneously forming the first groove and the second groove, the depth of the second groove is formed deeper than that of the first groove. 1 The semiconductor substrate described in 1 is obtained. This claim 6 In the invention described in (4), since the difference in thermal expansion coefficient between the oxide film and the semiconductor substrate can be effectively absorbed up to the lower part of the region of the thick oxide layer in the substrate manufacturing process, crystal defects, dislocations, substrate (wafer) The occurrence of warpage can be further suppressed.
[0017]
Claim 7 As described in the above, the step of filling the third groove with the polycrystalline semiconductor includes depositing the polycrystalline semiconductor on the semiconductor substrate and arranging the polycrystalline semiconductor in the third groove, and then the surface portion of the semiconductor substrate. The polycrystalline semiconductor deposited on the semiconductor substrate is removed, and a process of thermally oxidizing the polycrystalline semiconductor remaining on the surface of the semiconductor substrate is included. In this way, the concave portion of the surface portion of the thermal oxide layer can be buried and flattened with a polycrystalline semiconductor, and the polycrystalline semiconductor remaining in the concave portion is oxidized by the subsequent thermal oxidation, resulting in volume expansion and further flattening the surface. It becomes. The thick thermal oxide layer thus formed can have a surface that is approximately level with the substrate surface.
[0018]
Claim 8 The groove width of the first groove is “W1”, the groove width of the second groove is “W3”, the difference in thermal expansion coefficient between the semiconductor substrate and its thermal oxide is “A”, and thermal oxidation When the maximum width of the thermal oxide layer due to the first groove is “W” and the temperature difference between the room temperature and the maximum thermal oxidation temperature is “T”,
W3> {(A · W · T) / 2} + W1
The third groove absorbs the dimensional difference generated in the horizontal direction of the substrate due to the difference in thermal expansion coefficient between the semiconductor being heat treated and its oxide, and reduces the stress applied to the semiconductor substrate during the heat treatment. Further, the occurrence of crystal defects, dislocations, and substrate (wafer) warpage can be suppressed.
[0019]
Claim 9 In the first groove, when the aspect ratio, which is the dimension ratio of the groove depth to the groove width, is 10 or more, thermal oxidation with a film thickness of about 1 μm that can be formed in the category of a general LSI process. By the process, a thick thermal oxide layer having a depth of 10 μm or more can be formed at low cost.
[0020]
Claim 1 0 In the first groove, when the aspect ratio, which is the dimension ratio of the groove depth to the groove width, is 20 or more, a thick thermal oxide layer having a depth of 20 μm or more can be formed inexpensively, and the compound It is possible to obtain the same loss reduction effect as a transmission line formed on a semi-insulating substrate such as a semiconductor substrate.
[0021]
Claim 1 1 In the first groove, if the groove width is 1 μm or less, the oxide film on the side wall of the third groove is 1 μm or less, and a thick thermal oxide layer can be formed at a lower cost. The occurrence of crystal defects in the element formation region 2 can be further suppressed.
[0022]
Claim 1 2 If an SOI substrate is used as the semiconductor substrate and the first and second grooves are formed and the groove reaches the buried oxide film layer of the SOI substrate, the heat of the second element formation process The stress can be concentrated on the trench and the polycrystalline semiconductor, the generation of crystal defects and dislocations in the semiconductor substrate region where the second element is formed can be further suppressed, and malfunction of the second element can be prevented.
[0023]
Claim 1 3 The first element is a passive element and the second element is an active element, in particular as claimed in claim 1. 4 As described in the above, the passive element is preferably applied in the case of handling a high frequency.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
In this embodiment, the semiconductor substrate 100 shown in FIGS. FIG. 1 is a longitudinal sectional view of the semiconductor substrate 100, and FIG. 2 is a plan view of the semiconductor substrate 100. As shown in FIG. 1, a thick thermal oxide layer 2 is formed in a partial region on one surface side (element forming surface side) of a silicon substrate 1. As shown in FIG. 2, the thermal oxide layer 2 has a quadrangular shape. As shown in FIGS. 1 and 2, a groove 3 is formed inside the thermal oxide layer 2, and the groove 3 extends inward from the outer peripheral surface 2 a of the thermal oxide layer 2 along the outer peripheral surface 2 a. Yes. That is, the groove 3 has a quadrangular annular shape as a planar shape. This groove 3 is filled with polycrystalline silicon (polycrystalline semiconductor) 4. That is, a wall (4) made of polycrystalline silicon is buried in the vicinity of the outer peripheral surface 2a of the thermal oxide layer 2 inside the thermal oxide layer 2.
[0025]
The semiconductor substrate 100 is used to form the high frequency monolithic IC shown in FIG. That is, in this embodiment, the semiconductor device is embodied as a high-frequency monolithic IC, and FIG. 3 shows a longitudinal sectional view of a part of the high-frequency monolithic IC. In the semiconductor substrate 100 in this monolithic IC, the thick thermal oxide layer 2 becomes an insulator for disposing a passive element thereon.
[0026]
In FIG. 3, transistors Q1 and Q2 as active elements and an inductor 5 as a passive element are integrated on a semiconductor substrate 100, and high-frequency oscillators, amplifiers, filters, and other circuits are integrated into one chip.
[0027]
Specifically, in FIG. 3, a thermal oxide layer 2 having a thickness of 10 μm or more is formed in the passive element formation region A1 on the silicon substrate 1, and a spiral inductor 5 as a passive element is formed thereon. Has been. In a high-frequency circuit or the like, a strong electromagnetic wave is generated immediately below the spiral inductor 5, so that the thickness t1 of the thermal oxide layer 2 is preferably 10 μm or more, and in this example, 30 μm. The silicon thermal oxide film constituting the thermal oxide layer 2 has a relative dielectric constant of about “3.9”. The spiral inductor 5 is formed using a metal material, and in this example, aluminum (Al) which is also a wiring material is used. However, the material is not limited to aluminum (Al), and Cu, Au, or the like may be used. On the other hand, an N-channel MOS transistor Q1 and a P-channel MOS transistor Q2 are formed in the active element formation region A2 on the silicon substrate 1.
[0028]
FIG. 4 is a simulation result showing the relationship between the signal transmission loss and the oxide film thickness when the frequency f applied to the wiring (signal line) arranged on the oxide film is 2 GHz. In the simulation, the specific resistance of the silicon substrate was 4 Ω · cm, the line material was aluminum (Al), the thickness was 1 μm, the width was 50 μm, the distance from the ground wiring was 30 μm, and the total length was 1 mm.
[0029]
The following can be seen from FIG. The transmission loss decreases as the oxide film thickness increases. However, when the oxide film thickness is 10 μm or more, the transmission loss can be reduced to about 1/10 of the oxide film thickness of 1 μm. Further, the loss is almost saturated when the oxide film thickness is 20 μm or more. The oxide film thickness at which the loss is saturated differs depending on the signal frequency, the line resistance value, and the dimensions. However, in order to obtain a sufficient transmission loss reduction effect due to a thick oxide film in a high-frequency region of 100 MHz or higher, The film thickness is preferably 10 μm or more. Furthermore, when the oxide film thickness is 20 μm or more, the loss reduction effect similar to a transmission line formed on a semi-insulating substrate such as a compound semiconductor substrate can be obtained.
[0030]
Next, the manufacturing process of the monolithic IC will be described with reference to FIGS.
First, as shown in FIG. 5A, a silicon substrate 1 is prepared, and an oxide film (SiO 2) is formed on the upper surface thereof. 2 ) 20 is formed. Further, as shown in FIG. 5B, a photoresist (a member indicated by reference numeral 21) is applied on the oxide film 20. Then, in a predetermined region, that is, a region where the thick thermal oxide layer is to be formed in the passive element formation region A1, a striped groove pattern 22 having a width of 1 μm or less, for example, 0.8 μm, and a surrounding width of 1 μm or more, for example, 1.6 μm. The groove pattern 23 is exposed and opened. At this time, the width W2 between the opened groove patterns 22 is set to about 81.8% of the width (opening width) W1 of the groove pattern 22. For example, if the width (groove width) W1 of the groove pattern 22 is 0.8 μm, the width (groove interval) W2 between the groove patterns 22 is set to about 0.65 μm.
[0031]
Then, as shown in FIG. 5C, the oxide film 20 is etched by the groove patterns 22 and 23, and then the resist 21 is removed to form a mask made of the oxide film 20. As a result, a portion of the silicon substrate 1 where the groove is to be formed is exposed.
[0032]
Subsequently, as shown in the plan views of FIG. 6A and FIG. 8, a plurality of first grooves 24 having a depth of 10 μm or more are provided adjacent to each other in the portion (A1) where the passive element 5 is disposed in the silicon substrate 1. The second groove 25 having a groove width W3 larger than the groove width W1 of the first groove 24 is simultaneously formed around the region where the first groove 24 is formed. In a broad sense, in the portion (A1) where the passive element 5 is disposed in the silicon substrate 1, the first groove 24 having a depth of 10 μm or more and the first groove around the region where the first groove 24 is formed. A second groove 25 having a groove width W3 larger than 24 groove widths W1 is simultaneously formed. Details are as follows.
[0033]
Using anisotropic etching, the silicon substrate 1 is etched to form the grooves 24 and 25 at the same time. The width W1 of the first groove 24 is 1 μm or less, the width W3 of the second groove 25 is 1 μm or more, and the depth L1 of the grooves 24 and 25 is 10 μm or more as described above. In forming the groove, reactive ion etching using a fluorine-based gas, particularly anisotropic etching by high-density plasma etching is used. Accordingly, a deep groove having an aspect ratio (L1 / W1) of “10” or more having a side surface substantially perpendicular to the substrate 1 can be formed. Further, by using the etching method disclosed in Japanese Patent Laid-Open No. 2000-299310, it is possible to form a deep groove having an aspect ratio of “20” or more, even if the groove width is 1 μm or less. A substantially vertical groove having a depth of 20 μm or more can be formed. At this time, the silicon material 26 between the striped grooves 24 in the silicon substrate 1 has a width (thickness) W2 of about 81.8% of the groove width W1 and a height of 10 μm or more. become.
[0034]
Then, as shown in FIG. 6B, an oxide film 27 is grown from the inner surfaces of the first and second grooves 24 and 25 by thermal oxidation, and the first groove 24 is buried with the thermal oxide film 27. Between the adjacent first grooves 24 is a thermal oxide film 27, and in the second groove 25, the thermal oxide film 27 is formed on the side wall leaving the third groove 3. In a broad sense, an oxide film 27 is grown from the inner surfaces of the first and second grooves 24 and 25 by thermal oxidation, and the first groove 24 is buried with the thermal oxide film 27, and the second groove 25 has a sidewall. Then, a thermal oxide film 27 is formed leaving the third groove 3. Details are as follows.
[0035]
Wet O silicon substrate 1 2 , Steam O 2 , H 2 And O 2 Oxidation is performed in an oxidizing atmosphere containing hydrogen, such as in a mixed combustion gas. At this time, when the oxidation of the silicon substrate 1 in the grooves 24 and 25 proceeds, the silicon layer inside the substrate becomes silicon oxide by a thickness corresponding to 45% of the oxide film thickness, and 55% of the oxide film thickness. It expands to the outside from the side surface of the silicon substrate before oxidation by a thickness corresponding to. Therefore, as the oxidation proceeds, the stripe-shaped groove 24 is filled with silicon oxide (thermal oxide film 27), and when the oxide films 27 grown on the side walls on both sides of the groove 24 come into contact with each other, the oxide films are in contact with each other. The groove 24 can be completely filled with silicon oxide (thermal oxide film 27). For example, when the width W1 of the groove 24 is 0.8 μm, it can be buried by performing an oxidation process corresponding to growing an oxide film having a thickness of about 0.73 μm.
[0036]
Such an oxidation process for growing the oxide film 27 having a thickness of 1 μm or less is used in a normal LSI manufacturing process, and does not require a special process at an oxidation process of 1000 ° C. or more for several hours. A thick oxide layer can be formed at a lower cost than in literature 1). Conversely, when an oxide film thickness of 2 μm or more is required, an oxidation process of 10 hours or more is required, resulting in an increase in cost and the occurrence of crystal defects in the silicon region. Further, if the groove width W1 is further reduced, this oxidation process can be further shortened and the cost can be reduced, and the thickness of the oxide film formed on the outermost periphery can be reduced, and the generation of crystal defects in the silicon region can be further suppressed. .
[0037]
Note that, in the process in which the oxide films 27 grown on the side surfaces of the trenches 24 are in contact with each other and a bond is formed between the oxide films, it is necessary to participate in hydrogen. Therefore, an oxidizing atmosphere containing hydrogen as described above. We are processing with. However, this oxidizing atmosphere containing hydrogen is only from immediately before the oxide films contact each other until the groove 24 is completely filled with oxide, and the other time is dry O containing no hydrogen. 2 An oxidizing atmosphere such as When the width (plate thickness) W2 of the thin plate silicon material 26 in the region where the striped grooves 24 are formed is about 81.8% of the groove width W1, the inside of the grooves 24 is completely buried with oxide. At the same time, since all of them are oxidized and converted to silicon oxide, a thick thermal oxide layer 2 having a thickness of 10 μm or more can be formed over the entire region where the striped grooves 24 are formed.
[0038]
Further, in the vicinity of the substrate surface in the thick thermal oxide layer 2, the oxidation proceeds in a direction perpendicular to the surface (horizontal direction) of the substrate 1. There is a rough surface.
[0039]
Furthermore, since the second groove 25 has a larger groove width than the first groove 24, the third groove 3 remains due to thermal oxidation in the second groove 25, and the groove width S is equal to the initial groove. When the width (width of the second groove 25) W3 is 1.6 μm and W1 = 0.8 μm, the width is about 0.8 μm.
[0040]
The third groove 3 absorbs a dimensional difference generated in the horizontal direction of the substrate due to a difference in thermal expansion coefficient between silicon and silicon oxide during heat treatment. That is, the difference in thermal expansion coefficient between the oxide film and the silicon substrate when the inside of the trench 24 is filled with oxide is absorbed. Thereby, the stress applied to the silicon substrate 1 during the heat treatment can be reduced, and the occurrence of crystal defects, dislocations, and warpage of the substrate (wafer) can be suppressed.
[0041]
Specifically, the difference in thermal expansion coefficient A (2.5 × 10 5) between silicon and silicon oxide. -6 -0.5 × 10 -6 = 2.0 × 10 -6 / ° C.), the maximum width W of the thermal oxide layer 2 by the first groove 24 accompanying thermal oxidation, and the temperature difference T between the room temperature and the maximum oxidation temperature in the oxidation process of FIG. (A × W × T). For example, at W = 300 μm and T = 1100 ° C., A = 2.0 × 10 -6 Therefore, a dimensional difference of 0.66 μm is generated. Therefore, the groove width after the oxidation treatment of the second groove 25, that is, the groove width S of the third groove 3 needs to remain at least 0.33 (= 0.66 / 2) μm or more.
[0042]
Thus, the groove width of the first groove 24 is “W1”, the groove width of the second groove 25 is “W3”, the difference in thermal expansion coefficient between the silicon substrate and its thermal oxide is “A”, and the thermal oxidation is performed. When the maximum width of the thermal oxide layer due to the first groove 24 due to is “W” and the temperature difference between the room temperature and the maximum thermal oxidation treatment temperature is “T”,
W3> {(A · W · T) / 2} + W1
To satisfy. Thereby, the third groove 3 absorbs the dimensional difference generated in the horizontal direction of the substrate due to the difference in thermal expansion coefficient between silicon during heat treatment and its oxide, and reduces the stress applied to the silicon substrate 1 during heat treatment. Thus, generation of crystal defects, dislocations, and warpage of the substrate (wafer) can be suppressed. That is, the third groove 3 absorbs stress caused by the difference in thermal expansion coefficient between the thermal oxide layer and the silicon substrate when the inside of the first groove 24 is filled with oxide, Since excessive stress is not applied, warping of the substrate 1 can be suppressed.
[0043]
In addition, although the oxidation process of this process showed the example performed in the state which left the oxide film (mask material) 20 formed in FIG. 5A, the oxidation process was performed before the oxidation process of FIG. After the film (mask material) 20 is removed by etching, an oxidation treatment may be performed. Further, the oxide film (mask material) 20 may be a film including a nitride film. In that case, if the oxidation treatment of FIG. 6B is performed with the mask material (20) left, only the inner surfaces of the grooves 24 and 25 are oxidized. A film can be grown, and unevenness on the surface of the thick thermal oxide layer 2 can be reduced.
[0044]
In addition, after the groove forming step of FIG. 6A, depending on the etching conditions, the surface of the formed grooves 24 and 25 may have minute irregularities due to damage during etching, or the uppermost portions of the grooves 24 and 25. The corner portion of the groove becomes an acute angle, and in the step of FIG. 6B, the growth of the oxide film on the groove surface becomes non-uniform, and the inside of the groove 24 is not completely filled with oxide, and a cavity may remain. This cavity can be left as long as there is no hindrance to the LSI process in the subsequent process, but in some cases there is a risk that chemicals in the middle of the process may remain in the cavity and become a contamination source, or expand and break during heat treatment. Therefore, a step of shaping the groove into a shape in which the groove is easily filled with oxide, such as a sacrificial oxidation process, may be added. Further, the heat treatment temperature is preferably 965 ° C. or higher, and above this temperature, the oxide film 27 is formed with low stress on the silicon substrate 1 due to the effect of the viscous flow of the oxide film during the oxidation process, and into the groove 24. This improves the embedding property of the oxide.
[0045]
6B, when the aspect ratio of the grooves 24 and 25 is large, the atmosphere before the oxidation process filled in the grooves 24 and 25 (for example, inert such as air, nitrogen, and argon). Atmosphere) is filled, the oxidizing atmosphere does not reach the bottom of the groove, and oxidation may not proceed. In that case, the substrate may be inserted into a vacuum before the oxidation treatment of FIG. 6B and then inserted into an oxygen atmosphere to fill the grooves 24 and 25 with oxygen.
[0046]
Next, the polycrystalline silicon 4 is filled in the third groove 3 through the steps shown in FIGS. 6C, 7A, and 7B. First, as shown in FIG. 6C, a polycrystalline silicon 28, which is a polycrystalline semiconductor, is deposited on the silicon substrate 1 by, for example, LP-CVD or the like, and polycrystalline in the third groove 3. Dispose (embed) silicon. Further, the unevenness on the surface of the thick thermal oxide layer 2 can be substantially flattened by depositing polycrystalline silicon (burying polycrystalline silicon in the concave portions). In addition, even if the trench 24 is not completely filled with oxide and a cavity opened on the surface remains, the polycrystalline silicon can fill the cavity, eliminating the risk of contamination during the process and damage to the substrate. There is also an effect.
[0047]
Subsequently, as shown in FIG. 7A, the polycrystalline silicon 28 deposited on the surface portion of the silicon substrate 1 is formed with an oxide film on the surface other than the region where the thick thermal oxide layer is to be formed by, for example, reactive ion etching. Etch away until exposed. As a result, the excess polycrystalline silicon 28 on the surface is removed, and the polycrystalline silicon remains only in the concave portion on the surface of the thick thermal oxide layer 2 and the groove 3 on the outer peripheral side thereof.
[0048]
Next, as shown in FIG. 7B, the polycrystalline silicon remaining in the recesses near the surface of the thick thermal oxide layer 2 is oxidized with respect to the silicon substrate 1. That is, the polycrystalline silicon (28) remaining on the surface of the silicon substrate 1 is thermally oxidized. Through such a process, a thick thermal oxide layer (thick insulator layer) 2 having a thickness of 10 μm or more is formed in a predetermined region. Further, since the volume of the polycrystalline silicon remaining in the concave portion of the surface portion of the thick thermal oxide layer 2 is oxidized, the surface is further flattened. The thick thermal oxide layer 2 formed in this way has a surface that is almost the same height as the silicon substrate surface, and the polycrystalline silicon embedded in the recesses can almost be oxidized. The surface of the substrate is flat and has a thickness of 10 μm or more.
[0049]
The surface of the thick thermal oxide layer 2 of 10 μm or more formed as described above is substantially flat and has sufficient mechanical strength. Therefore, a monolithic IC, that is, active elements Q1 and Q2 (MOS transistors) on the silicon substrate 1 and passive elements on the thermal oxide layer 2 as shown in FIG. An element (spiral inductor) 5 can be formed. That is, the P well region 6 and the N well region 7 are formed in the surface layer portion of the silicon substrate 1, the gate electrode 8 is disposed on the P well region 6 through the gate insulating film, and the source region 9 and the drain region are further formed. 10 is formed. Similarly, the gate electrode 11 is disposed on the N well region 7 through the gate insulating film, and the source region 12 and the drain region 13 are formed. Thereafter, a passivation film 14 is formed on the metal wiring including the passive element (spiral inductor) 5 and further on the substrate surface.
[0050]
Here, in a normal LSI process, particularly in the active element formation process, a number of heat treatment steps at a high temperature of 800 ° C. or more are repeated. The dimension generated in the horizontal direction of the substrate due to the difference in thermal expansion coefficient between silicon and silicon oxide at that time The difference can be absorbed by the distortion of the polycrystalline silicon 4. Thereby, the stress applied to the silicon substrate 1 during the heat treatment process can be reduced, and the occurrence of crystal defects, dislocations, and warpage of the substrate (wafer) can be suppressed. Further, since the silicon substrate 1 can be made to have low crystal defects and low dislocations, it is possible to avoid malfunction of the active element, and to form the active element in a position close to the thermal oxide layer 2. realizable. Further, an element can be formed without changing an existing LSI manufacturing process, and a high-performance, high-frequency monolithic IC suitable for mass production can be realized.
[0051]
As described above, in the present embodiment, the semiconductor substrate 100 in FIG. 3 has the passive element 5 (element that handles high frequency) as the first element disposed on the insulator and the active element as the second element. A semiconductor substrate for use in a semiconductor device in which Q1 and Q2 are formed, and a thermal oxide layer 2 having a thickness of 10 μm or more is formed in a portion (A1) where the passive element 5 is disposed, and the thermal oxidation A groove 3 filled with polycrystalline silicon 4 is formed along the outer peripheral surface 2 a inward from the outer peripheral surface 2 a of the physical layer 2. Therefore, the element function can be sufficiently exhibited by the thick thermal oxide layer 2. Specifically, the parasitic capacitance and the parasitic resistance with respect to the passive element (spiral inductor) 5 can be sufficiently reduced. In addition, since the passive element 5 does not have an aerial wiring structure, sufficient mechanical strength can be obtained. Further, since the groove 3 filled with the polycrystalline silicon 4 is formed along the outer peripheral surface 2a inward from the outer peripheral surface 2a of the thermal oxide layer 2, the polycrystalline silicon 4 is used in the process of forming the active elements Q1 and Q2. Since it functions as a heat stress absorption layer, it is possible to suppress the occurrence of warpage, crystal defects, and dislocations in the substrate, and to prevent malfunction of the active elements Q1, Q2. As a result, the dead space can be reduced and a highly integrated circuit can be realized.
[0052]
Further, in the first groove 24 in FIG. 6A, if the aspect ratio (L1 / W1), which is the dimensional ratio of the groove depth L1 to the groove width W1, is 10 or more, A thick thermal oxide layer 2 having a depth of 10 μm or more can be formed inexpensively by a thermal oxidation process having a thickness of about 1 μm that can be formed in a category. Further, in the first groove 24, when the aspect ratio (L1 / W1) which is the dimension ratio of the groove depth L1 to the groove width W1 is 20 or more, the thick thermal oxide layer 2 having a depth of 20 μm or more is inexpensively formed. The loss reduction effect similar to that of a transmission line formed on a semi-insulating substrate such as a compound semiconductor substrate can be obtained.
[0053]
Further, in the first groove 24, when the groove width W1 is 1 μm or less, the oxide film on the side wall of the third groove 3 becomes 1 μm or less, and the thick thermal oxide layer 2 can be formed at a lower cost, and The occurrence of crystal defects in the element formation region 2 can be further suppressed.
[0054]
In the step of forming the grooves 24 and 25 in FIG. 6A, depending on the etching conditions, the groove depth can be increased as the groove width becomes wider. Using this, in the step of simultaneously forming the first groove 24 and the second groove 25 as shown in FIG. 9A instead of FIG. 6A, the depth L11 of the second groove 25 is set. It is formed deeper than the first groove 24. Then, as shown in FIGS. 9B and 9C, thermal oxidation and deposition of the polycrystalline silicon 28 are performed. Through this process, as shown in FIG. 10, the thermal oxide layer formed by filling the first groove 24 with the depth L12 of the polycrystalline silicon 4 filling the third groove 3 by thermal oxidation. The thickness may be larger than the thickness t1 of 2. That is, the depth L12 of the groove 3 filled with the polycrystalline silicon 4 may be larger than the thickness t1 of the thermal oxide layer 2. Specifically, the depth L12 of the groove 3 is made larger than the thickness t1 of the thermal oxide layer 2 other than the portion where the groove 3 is formed. Thereby, in the step of forming elements on the semiconductor substrate 100 (LSI process), thermal stress (difference in thermal expansion coefficient between the oxide film and the silicon substrate) can be effectively absorbed up to the lower portion of the thick thermal oxide layer 2 region. Therefore, it is possible to further suppress the occurrence of crystal defects, dislocations, and warpage of the substrate (wafer) inside the substrate. Further, when the depth L11 of the second groove 25 in FIG. 9A is deeper than the first groove 24, it is effectively oxidized to the lower part of the region of the thick thermal oxide layer 2 in the manufacturing process of the semiconductor substrate 100. Since the difference in thermal expansion coefficient between the film and the silicon substrate can be absorbed, the occurrence of crystal defects, dislocations, and warpage of the substrate (wafer) can be further suppressed.
[0055]
Although the case where a general silicon substrate is used has been described so far, an SOI (Silicon On Insulator) substrate 200 may be used as the substrate as shown in FIG. In FIG. 11, a single crystal silicon layer 203 having a thickness of 10 μm or more is formed on a silicon substrate 201 via an oxide film layer 202 having a thickness of about 1 μm. Further, the thermal oxide layer 2 is formed in a partial region of the single crystal silicon layer 203, and the thermal oxide layer 2 reaches the buried oxide film layer 202. For this purpose, etching is performed until the grooves 24 and 25 reach the buried oxide film layer 202 in the process of FIG. That is, the grooves 24 and 25 reaching the buried oxide film layer 202 of the SOI substrate are formed in the groove forming step. Thereby, the silicon layer in the region where the thermal oxide layer is to be formed and the silicon layer in other regions can be completely separated by the oxide. Therefore, the thermal stress in the subsequent thick thermal oxide layer forming process and active element forming process can be concentrated on the groove 3 and the polycrystalline silicon 4 in the outer peripheral portion, and crystal defects in the silicon substrate region where the active element is formed, The occurrence of dislocation can be further suppressed, and malfunction of the active element can be prevented. More specifically, in FIG. 3, when a defect occurs in the lower surface portion of the thermal oxide layer 2, it spreads in the left-right direction, and may adversely affect the transistors Q 1 and Q 2 in the active element formation region. is there. Compared to this, such a situation is avoided by the presence of the buried oxide film layer 202 in FIG.
[0056]
In the description so far, the case where the transistor is an active element and the inductor is a passive element has been described. However, the present invention is applied to a case where a diode or the like is an active element or a metal wiring, resistor, capacitor, or the like is a passive element. May be.
[0057]
In FIGS. 2 and 8, the thick thermal oxide layer 2 has a quadrangular pattern, but the pattern is not limited to a quadrangular shape and may be any pattern. Specifically, for example, it may be a circle as shown in FIG. 12, or a complex polygon as shown in FIG. Alternatively, as illustrated in FIG. 14, the thermal oxide layer 2 may be formed in a square ring shape as a planar structure in the silicon substrate 1. That is, a pattern in which the single crystal silicon 1a exists around the square annular thermal oxide layer 2 and the single crystal silicon island 1b exists inside the square annular thermal oxide layer 2 may be used. In this case, at the boundary portion between the thermal oxide layer 2 and the single crystal silicon region (1a, 1b), polycrystalline silicon is formed along the outer peripheral surface 2a inward from the outer peripheral surface 2a of the thermal oxide layer 2. A groove 3 filled with 4 is formed.
[0058]
Further, in the above description, the semiconductor substrate according to the present invention is described as an example applied to a high frequency monolithic IC. That is, the passive element (inductor) 5 as the first element is disposed on the thermal oxide layer 2 and used for the semiconductor device in which the active elements (transistors) Q1 and Q2 as the second elements are formed. It was a semiconductor substrate. However, the present invention is not limited to this, and may be as follows.
[0059]
For example, the present invention is applied to an IC for a microprocessor having a clock frequency of 1 GHz or more. Specifically, a microprocessor constituent element (transistor or the like) as a second element is formed in the silicon layer, and a wiring material is disposed as the first element on the thermal oxide layer 2.
[0060]
Alternatively, it is applied to an IC having a power element that requires a high breakdown voltage of 1000 volts or more. Specifically, a power element is formed as a second element in the silicon layer, element isolation is achieved by the thermal oxide layer 2, and a wiring material is disposed on the thermal oxide layer 2 as the first element. To do. In this case, the withstand voltage can be improved by the thick thermal oxide layer 2.
[0061]
Alternatively, the present invention is applied to an IC having a sensor element that requires thermal insulation with respect to the substrate. Specifically, a sensor element is arranged as a first element on the thermal oxide layer 2, and a sensor signal processing circuit constituent element (amplifier constituent element, A / A) as a second element is disposed on the lateral silicon layer. D conversion element). In this case, the thermal barrier property can be improved by the thick thermal oxide layer 2.
[Brief description of the drawings]
FIG. 1 is a longitudinal sectional view of a semiconductor substrate in an embodiment.
FIG. 2 is a plan view of a semiconductor substrate.
FIG. 3 is a longitudinal sectional view showing a part of a monolithic IC in the embodiment.
FIG. 4 is a diagram showing simulation results for signal transmission loss and oxide film thickness.
5A, 5B, and 5C are cross-sectional views showing a manufacturing process of a monolithic IC.
6A, 6B, and 6C are cross-sectional views showing a manufacturing process of a monolithic IC.
7A and 7B are cross-sectional views showing a manufacturing process of a monolithic IC.
FIG. 8 is a plan view showing a manufacturing process of the monolithic IC.
9A, 9B, and 9C are cross-sectional views showing a manufacturing process.
FIG. 10 is a longitudinal sectional view of a semiconductor substrate.
FIG. 11 is a longitudinal sectional view showing a part of a monolithic IC when applied to an SOI substrate.
FIG. 12 is a plan view of a semiconductor substrate.
FIG. 13 is a plan view of a semiconductor substrate.
FIG. 14 shows a semiconductor substrate.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Thermal oxide layer, 3 ... Groove (3rd groove | channel), 4 ... Polycrystalline silicon, 5 ... Passive element (1st element), 24 ... 1st groove | channel, 25 ... 2nd , 26 ... silicon material, 28 ... polycrystalline silicon, 200 ... SOI substrate, 202 ... buried oxide film layer, A1 ... passive element formation region, Q1, Q2 ... active elements.

Claims (14)

第１の素子（５）を絶縁物の上に配置するとともに第２の素子（Ｑ１，Ｑ２）を作り込んだ半導体装置に用いるための半導体基板であって、
第１の素子が配置される部位（Ａ１）において厚さ１０μｍ以上の熱酸化物層（２）が形成されるとともに、当該熱酸化物層（２）の外周面（２ａ）から内方において同外周面（２ａ）に沿って多結晶半導体（４）を充填した溝（３）が形成されており、
前記多結晶半導体（４）を充填した溝（３）の深さ（Ｌ１２）が、熱酸化物層（２）の厚さ（ｔ１）よりも大きいことを特徴とする半導体基板。A semiconductor substrate for use in a semiconductor device in which the first element (5) is disposed on an insulator and the second element (Q1, Q2) is formed,
A thermal oxide layer (2) having a thickness of 10 μm or more is formed at a site (A1) where the first element is disposed, and the same is applied inward from the outer peripheral surface (2a) of the thermal oxide layer (2). A groove (3) filled with the polycrystalline semiconductor (4) is formed along the outer peripheral surface (2a) ,
A semiconductor substrate, wherein a depth (L12) of the groove (3) filled with the polycrystalline semiconductor (4) is larger than a thickness (t1) of the thermal oxide layer (2) . 前記第１の素子（５）は受動素子であり、前記第２の素子（Ｑ１，Ｑ２）は能動素子であることを特徴とする請求項１に記載の半導体基板。 2. The semiconductor substrate according to claim 1, wherein the first element (5) is a passive element and the second element (Q1, Q2) is an active element . 前記受動素子（５）は高周波を取り扱うものであることを特徴とする請求項２に記載の半導体基板。 3. The semiconductor substrate according to claim 2 , wherein the passive element (5) handles high frequencies . 第１の素子（５）を絶縁物の上に配置するとともに第２の素子（Ｑ１，Ｑ２）を作り込んだ半導体装置に用いるための半導体基板の製造方法であって、
半導体基板（１）における第１の素子（５）が配置される部位（Ａ１）において、深さ１０μｍ以上の第１の溝（２４）と、この第１の溝（２４）を形成する領域の周囲に第１の溝（２４）の溝幅よりも大きな溝幅の第２の溝（２５）を同時に形成する工程と、
熱酸化により前記第１および第２の溝（２４，２５）の内面から酸化膜（２７）を成長させて第１の溝（２４）においては熱酸化膜（２７）によって埋設し、第２の溝（２５）においては側壁に熱酸化膜（２７）を第３の溝（３）を残して形成する工程と、
前記第３の溝（３）に多結晶半導体（４）を充填する工程と、
を備えたことを特徴とする半導体基板の製造方法。 A method of manufacturing a semiconductor substrate for use in a semiconductor device in which a first element (5) is disposed on an insulator and a second element (Q1, Q2) is formed,
In a portion (A1) where the first element (5) is disposed in the semiconductor substrate (1), a first groove (24) having a depth of 10 μm or more and a region for forming the first groove (24) Simultaneously forming a second groove (25) having a groove width larger than the groove width of the first groove (24) around the periphery;
An oxide film (27) is grown from the inner surfaces of the first and second grooves (24, 25) by thermal oxidation, and the first groove (24) is buried by the thermal oxide film (27), and the second Forming a thermal oxide film (27) on the side wall in the groove (25), leaving the third groove (3);
Filling the third groove (3) with a polycrystalline semiconductor (4);
A method for manufacturing a semiconductor substrate, comprising: 第１の素子（５）を絶縁物の上に配置するとともに第２の素子（Ｑ１，Ｑ２）を作り込んだ半導体装置に用いるための半導体基板の製造方法であって、A method of manufacturing a semiconductor substrate for use in a semiconductor device in which a first element (5) is disposed on an insulator and a second element (Q1, Q2) is formed,
半導体基板（１）における第１の素子（５）が配置される部位（Ａ１）において、深さ１０μｍ以上の第１の溝（２４）を隣接して複数形成するとともに第１の溝（２４）を形成する領域の周囲に第１の溝（２４）の溝幅よりも大きな溝幅の第２の溝（２５）を同時に形成する工程と、  In the part (A1) where the first element (5) is disposed in the semiconductor substrate (1), a plurality of first grooves (24) having a depth of 10 μm or more are formed adjacent to each other and the first grooves (24). Simultaneously forming a second groove (25) having a groove width larger than the groove width of the first groove (24) around a region for forming
熱酸化により前記第１および第２の溝（２４，２５）の内面から酸化膜（２７）を成長させて第１の溝（２４）においては熱酸化膜（２７）によって埋設するとともに隣接する第１の溝（２４）の間を全て熱酸化膜（２７）とし、第２の溝（２５）においては側壁に熱酸化膜（２７）を第３の溝（３）を残して形成する工程と、  An oxide film (27) is grown from the inner surfaces of the first and second grooves (24, 25) by thermal oxidation, and the first groove (24) is buried with the thermal oxide film (27) and adjacent to the first groove (24, 25). A step of forming a thermal oxide film (27) between the first groove (24) and forming a thermal oxide film (27) on the side wall of the second groove (25) leaving the third groove (3); ,
前記第３の溝（３）に多結晶半導体（４）を充填する工程と、  Filling the third groove (3) with a polycrystalline semiconductor (4);
を備えたことを特徴とする半導体基板の製造方法。A method for manufacturing a semiconductor substrate, comprising: 前記第１の溝（２４）と第２の溝（２５）を同時に形成する工程において、前記第２の溝（２５）の深さ（Ｌ１１）を第１の溝（２４）よりも深く形成したことを特徴とする請求項４または５に記載の半導体基板の製造方法。 In the step of simultaneously forming the first groove (24) and the second groove (25), the depth (L11) of the second groove (25) was formed deeper than the first groove (24). the method of manufacturing a semiconductor substrate according to claim 4 or 5, characterized in that. 前記第３の溝（３）に多結晶半導体（４）を充填する工程は、
前記半導体基板（１）上に多結晶半導体（２８）を堆積させて前記第３の溝（３）内に多結晶半導体（２８）を配した後、前記半導体基板（１）の表面部に堆積した前記多結晶半導体（２８）を除去し、さらに、前記半導体基板（１）の表面に残留した多結晶半導体（２８）を熱酸化する処理を含むことを特徴とする請求項４〜６のいずれか１項に記載の半導体基板の製造方法。 Filling the third groove (3) with the polycrystalline semiconductor (4),
After depositing the polycrystalline semiconductor (28) on the semiconductor substrate (1) and arranging the polycrystalline semiconductor (28) in the third groove (3), the polycrystalline semiconductor (28) is deposited on the surface portion of the semiconductor substrate (1). 7. The method according to claim 4 , further comprising: removing the polycrystalline semiconductor (28) and further thermally oxidizing the polycrystalline semiconductor (28) remaining on the surface of the semiconductor substrate (1). A method for manufacturing a semiconductor substrate according to claim 1 . 前記第１の溝（２４）の溝幅を「Ｗ１」、前記第２の溝（２５）の溝幅を「Ｗ３」、半導体基板（１）とその熱酸化物との熱膨張係数差を「Ａ」、熱酸化に伴なう第１の溝（２４）による熱酸化物層の最大幅を「Ｗ」、室温と最大熱酸化処理温度との温度差を「Ｔ」としたとき、
Ｗ３＞｛（Ａ・Ｗ・Ｔ）／２｝＋Ｗ１
を満足するようにしたことを特徴とする請求項４〜７のいずれか１項に記載の半導体基板の製造方法。 The groove width of the first groove (24) is “W1”, the groove width of the second groove (25) is “W3”, and the difference in thermal expansion coefficient between the semiconductor substrate (1) and its thermal oxide is “ A ”, when the maximum width of the thermal oxide layer by the first groove (24) accompanying thermal oxidation is“ W ”, and the temperature difference between the room temperature and the maximum thermal oxidation treatment temperature is“ T ”,
W3> {(A · W · T) / 2} + W1
The method of manufacturing a semiconductor substrate according to claim 4 , wherein the semiconductor substrate is satisfied . 前記第１の溝（２４）において、その溝幅（Ｗ１）に対する溝深さ（Ｌ１）の寸法比であるアスペクト比（Ｌ１／Ｗ１）が１０以上であることを特徴とする請求項４〜８のいずれか１項に記載の半導体基板の製造方法。 In the first groove (24), according to claim 4-8 in which the aspect ratio is the size ratio of the groove depth (L1) for the groove width (W1) (L1 / W1) is equal to or is 10 or more The manufacturing method of the semiconductor substrate of any one of these. 前記第１の溝（２４）において、その溝幅（Ｗ１）に対する溝深さ（Ｌ１）の寸法比であるアスペクト比（Ｌ１／Ｗ１）が２０以上であることを特徴とする請求項４〜８のいずれか１項に記載の半導体基板の製造方法。 In the first groove (24), according to claim 4-8 aspect ratio is the size ratio of the groove depth (L1) for the groove width (W1) (L1 / W1) is equal to or is more than 20 The manufacturing method of the semiconductor substrate of any one of these. 前記第１の溝（２４）において、その溝幅（Ｗ１）が１μｍ以下であることを特徴とする請求項４〜１０のいずれか１項に記載の半導体基板の製造方法。 11. The method of manufacturing a semiconductor substrate according to claim 4, wherein the first groove (24) has a groove width (W 1) of 1 μm or less . 半導体基板としてＳＯＩ基板を用い、前記第１および第２の溝（２４，２５）を形成する際に同溝（２４，２５）がＳＯＩ基板の埋め込み酸化膜層（２０２）に達していることを特徴とする請求項４または５に記載の半導体基板の製造方法。 An SOI substrate is used as the semiconductor substrate, and when the first and second grooves (24, 25) are formed, the grooves (24, 25) reach the buried oxide film layer (202) of the SOI substrate. 6. The method for manufacturing a semiconductor substrate according to claim 4 , wherein the method is a semiconductor substrate. 前記第１の素子（５）は受動素子であり、前記第２の素子（Ｑ１，Ｑ２）は能動素子であることを特徴とする請求項４〜１２のいずれか１項に記載の半導体基板の製造方法。 13. The semiconductor substrate according to claim 4, wherein the first element (5) is a passive element and the second element (Q1, Q2) is an active element . Production method. 前記受動素子（５）は高周波を取り扱うものであることを特徴とする請求項１３に記載の半導体基板の製造方法。 14. The method of manufacturing a semiconductor substrate according to claim 13 , wherein the passive element (5) handles high frequency .
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