JP2001223331A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a high mechanical strength at a low part of wirings without bringing about a problem in reliability and a method for manufacturing the same. SOLUTION: An oxide film 12 is formed on a silicon substrate 11. A resist film 13 is formed on the film 12, and a pattern 14 for opening a window is formed. The film 12 is etched by anisotropically etching to form an opening 1 at the film 12. The substrate 12 is etched in a depthwise direction of the substrate 11 by anisotropically etching to form grooves 16. The substrate 11 is isotropically etched. Thus, a cavity 18 is formed. A CVD oxide film 17 is formed on an opening 15 by using a vapor phase growing method, a reduced pressure TEOSCVD method or an ordinary pressure CVD method. An integrated circuit is completed by conducting a step of contact opening, a step of forming first wiring 19, a step of forming an interlayer insulating film 20, and a step of forming a second wiring 21 (inductor).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a reduction in a loss of a spiral inductor required for an inductive element formed on a semiconductor substrate.

[0002]

2. Description of the Related Art In silicon semiconductor devices such as LSIs (Large Scale Integrated Circuits), as the frequency becomes higher, the necessity of mounting an inductive element, which has not been conventionally mounted, inside the LSI is rapidly increasing. . Mounting an inductive element on a silicon LSI, which is a conductive substrate, requires GaAs.
Unlike the case of mounting on a semi-insulating substrate, there is a problem that a mutual induction phenomenon easily occurs between the inductive element and the Si substrate, and energy is lost due to an eddy current, and it is difficult to obtain desired characteristics.

In order to solve this problem, it is known to use a substrate cavity for an inductor element formed on a silicon substrate. About this, IEEE Electron Device L
etters, vol. 14, no. 5, pp. 246-248, MAY, 1993. In a silicon substrate, since a large number of carriers are present, charges are induced in the substrate by a mutual induction effect.
In contrast, by forming a cavity in the silicon substrate, the occurrence of this phenomenon can be suppressed.

In addition, since a cavity exists in the silicon substrate, the parasitic capacitance value (the dielectric constant of the silicon substrate is 11.1).
7, the capacitance value is much larger than that of vacuum). Thereby, the energy loss in the silicon substrate can be effectively reduced (Q value can be improved).

FIGS. 5 and 6 show the structure and layout of the above-described semiconductor device. That is, the silicon substrate 10
MOS transistor 101 and interlayer insulating film 10
4 and the second wiring 102 and the first wiring 103 provided via
Are laminated, and the MOS transistor and the wiring structure are separated by an opening 106. Further, the cavity 1 is formed in the silicon substrate 100 so as to communicate with the opening 106 and under the MOS transistor and the wiring structure.
05 is provided.

In this structure, Japanese Patent Laid-Open No. 9-1
As described in Japanese Patent No. 62285, improvements in layout and structure have been made to maintain the mechanical strength under the inductor.

FIGS. 7 and 8 show the structure and layout of another semiconductor device. In this structure, a cavity 105 is provided in the silicon substrate 100 so as to communicate with the opening 106, and a second wiring 102 and a first wiring 103 provided via an interlayer insulating film 104 are stacked above the cavity 105. It has a structure.

In this structure, by arranging the cavities 105 in a staggered manner on the wiring side, the bridges can be regularly arranged, and the mechanical strength can be greatly improved.

[0009]

However, the above-mentioned 2)
Each of the two structures is formed after the cavity 105 is processed into a wiring functioning as an inductor. When such a structure is employed, the cavity portion is released to the atmosphere during the post-process and packaging, which may affect the surroundings, cause contamination, etc., and is likely to cause reliability problems. . In addition, there is a problem in that the cavity is released from the viewpoint of the mechanical strength below the wiring.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device which does not cause a problem in reliability and has a high mechanical strength under a wiring and a method of manufacturing the same. And

[0011]

Means for Solving the Problems In order to solve the above problems, the present invention has taken the following means. The present invention includes a step of forming a groove in the depth direction of the semiconductor substrate from the main surface of the semiconductor substrate, and closing the opening by depositing a film by vapor deposition on the opening of the groove. A method for manufacturing a semiconductor device, comprising: forming a cavity in a semiconductor substrate; and forming a wiring layer on the cavity.

According to this method, anisotropic etching, isotropic etching, and CVD of silicon are performed when forming a cavity in a silicon substrate necessary for introducing a high-performance inductive element in a silicon semiconductor. By combining them, the parasitic capacitance between the wiring and the substrate can be reduced without lowering the mechanical strength of the lower part of the wiring layer, without causing reliability problems due to the influence of surroundings and contamination, etc. Semiconductor device excellent in the above can be obtained.

In the method of manufacturing a semiconductor device according to the present invention, the trench is formed in a depth direction of the semiconductor substrate by performing anisotropic etching after performing anisotropic etching on the semiconductor substrate. Is preferred.

Thus, while maintaining the mechanical strength of the semiconductor device, the volume of the cavity is increased, and the width of the bridge between the cavities is made constant by isotropic etching in order to keep the bridge at a constant interval. Can be.

According to the present invention, a groove is formed in a depth direction of the semiconductor substrate from a main surface of the semiconductor substrate, and a film is deposited on the opening of the groove by a vapor deposition method to close the opening. A semiconductor device obtained by forming a cavity in the semiconductor substrate and forming a wiring layer on the cavity is provided.

According to this configuration, when forming a cavity in the silicon substrate necessary for introducing a high-performance inductive element in a silicon semiconductor, anisotropic etching, isotropic etching, and CVD of silicon are performed. By the combination, the parasitic capacitance between the wiring and the substrate can be reduced without lowering the mechanical strength of the lower part of the wiring layer and without causing a reliability problem due to the influence of surroundings and contamination.

In the semiconductor device according to the present invention, it is preferable that the wiring layer forms a spiral inductor.

[0018]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. The present invention employs a device structure in which a cavity is machined in a semiconductor substrate such as a silicon substrate after element formation and before an inductor is formed, and then the cavity is intentionally closed to manufacture.

First, an oxide film 12 is formed on a silicon substrate 11 as shown in FIG. An element (not shown) is formed on the oxide film 12. Then
As shown in FIG. 1B, the resist film 1 is formed on the oxide film 12.
3 is formed, and a pattern 14 for opening a window in a cavity region is formed in the inductor region of the resist film 13.

Next, as shown in FIG. 1C, the oxide film 12 is etched by anisotropic etching.
An opening 15 is formed in 2. Next, as shown in FIG. 1D, after forming an opening 15 in the oxide film 12, the silicon substrate 11 is etched in the depth direction of the silicon substrate 11 by anisotropic etching to form a groove 16. The etching of the silicon substrate 11 has a depth of, for example, about 5 μm.

Next, as shown in FIG. 2A, the silicon substrate 11 is isotropically etched. As a result, the silicon substrate 11 is also shaved in the width direction, and the lower portion of the oxide film 12 becomes eaves-like.

As described above, the combination of anisotropic etching and isotropic etching is intended to increase the volume of the cavities and maintain a constant spacing between the cavities while maintaining the mechanical strength of the semiconductor device. This is to make the lateral spread constant by isotropic etching. Note that the above object can be achieved by only the isotropic etching according to the layout. In addition, the length of the eaves 16a is formed to be at least 1 μm or more. Thereby, the cavity 18 is formed.

The eave 16a is formed by a cavity 18 of the CVD oxide film 17
Suppress film formation on the inside. This prevents the CVD oxide film 17 from continuously depositing on the side wall of the cavity 18 and covering the cavity 18 with the CVD oxide film 17 so as to be buried, thereby sufficiently exhibiting the effect of reducing the dielectric constant. it can.

Next, as shown in FIG.
8 is performed. For example, a CVD oxide film 17 is formed on the opening 15 by using a low pressure TEOSCVD method or a normal pressure CVD method which is a vapor growth method. CVD oxide film 1
7 is formed in the interior of the cavity 18 in the initial stage, but the film is formed, and the opening 15 of the oxide film 12 corresponding to the entrance of the cavity 18 becomes narrower as the CVD oxide film 17 is deposited, and is finally completely closed. State. In this state, further CVD
By continuing the deposition of the oxide film 17, the opening 15 is completely removed.
Becomes blocked.

It should be noted here that the width of the opening 15 needs to be suppressed to, for example, about 0.5 μm on one side. By setting one side of the opening 15 to this size, the CVD oxide film 1
7 is deposited to a thickness of about 1 μm to completely remove the cavity 18.
Can be closed.

Next, as shown in FIG. 2C, a contact opening step, a step of forming a first wiring 19, an interlayer insulating film 2
In this way, the integrated circuit is completed through the step of forming the first wirings 0 and the step of forming the second wiring 21 (inductor).

FIG. 3 shows an example of a semiconductor device according to one embodiment of the present invention. In this case, the layout (spiral shape) of the cavities 18 is, for example, about 0.5 × 3 μm, and is arranged at intervals of 3 μm. With such a layout, the capacity under the inductor can be effectively reduced while maintaining the mechanical strength of the bridge between the cavities 18.

FIG. 4 shows another example of a semiconductor device according to one embodiment of the present invention. In this case, the layout of the cavity 18 is the same as that of FIG. 3, but a cavity 23 is further added. The layout of the cavity 23 is, for example, 0.5 × 10
It is about 0 μm and is arranged radially from the center of the inductor.

As described above, by arranging the cavities 23 radially, it becomes possible to cut off the path of the induced current generated on the vortex due to the mutual induction of the inductors. By employing this structure, it is possible to more effectively prevent the generation of eddy current and improve the high-frequency characteristics of the inductor.

As described above, according to the present embodiment, when forming a cavity in a silicon substrate necessary for introducing a high-performance inductive element in a silicon semiconductor, anisotropic etching of silicon, etc. Isotropic etching,
By combining CVD, wiring and wiring can be performed without lowering the mechanical strength of the lower part of the wiring layer and without causing reliability problems due to surrounding influences and contamination.
The parasitic capacitance between the substrates can be reduced, and a semiconductor device having excellent high-frequency characteristics can be obtained.

The present invention is not limited to the above embodiment, but can be implemented with various modifications. For example, the present invention is not limited to the material of each film or wiring, and can be implemented by appropriately changing materials having the same kind of properties.

[0032]

As described above, according to the present invention, wiring can be performed without lowering the mechanical strength of the lower part of the wiring layer and without causing reliability problems due to the influence of surroundings and contamination. -The parasitic capacitance between the substrates can be reduced, and a semiconductor device having excellent high frequency characteristics can be obtained. Therefore, the present invention is suitable for manufacturing a high-frequency ultra-highly integrated semiconductor that requires a high-performance inductive element, and has extremely high industrial utility value.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing the first half of a process in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a latter half of a process in a method for manufacturing a semiconductor device according to one embodiment of the present invention;

FIG. 3 is a plan view showing an example of a semiconductor device according to one embodiment of the present invention.

FIG. 4 is a plan view showing another example of the semiconductor device according to one embodiment of the present invention;

FIG. 5 is a sectional view showing a conventional semiconductor device.

FIG. 6 is a plan view showing a conventional semiconductor device.

FIG. 7 is a sectional view showing a conventional semiconductor device.

FIG. 8 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

11 silicon substrate, 12 oxide film, 13 resist film, 14 pattern, 15 opening, 16 groove, 16a
Eaves, 17: CVD oxide film, 18, 23: cavity, 19: first wiring, 20: interlayer insulating film, 21: second wiring, 22: contact.

Claims (4)

[Claims] A step of forming a groove in a depth direction of the semiconductor substrate from a main surface of the semiconductor substrate, and closing the opening by depositing a film in an opening of the groove by a vapor deposition method. A method for manufacturing a semiconductor device, comprising: forming a cavity in the semiconductor substrate; and forming a wiring layer on the cavity. 2. The semiconductor device according to claim 1, wherein the trench is formed in a depth direction of the semiconductor substrate by performing isotropic etching after performing anisotropic etching on the semiconductor substrate. A method for manufacturing a semiconductor device. 3. A groove is formed from a main surface of the semiconductor substrate in a depth direction of the semiconductor substrate, and a film is deposited on an opening of the groove by a vapor phase epitaxy to close the opening to form the semiconductor. A semiconductor device obtained by forming a cavity in a substrate and forming a wiring layer on the cavity. 4. The semiconductor device according to claim 3, wherein said wiring layer forms a spiral inductor.