GB2345578A - A method of manufacturing a semiconductor device including a trench - Google Patents

A method of manufacturing a semiconductor device including a trench Download PDF

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Publication number
GB2345578A
GB2345578A GB0000562A GB0000562A GB2345578A GB 2345578 A GB2345578 A GB 2345578A GB 0000562 A GB0000562 A GB 0000562A GB 0000562 A GB0000562 A GB 0000562A GB 2345578 A GB2345578 A GB 2345578A
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Prior art keywords
trench
film
semiconductor device
semiconductor substrate
etching
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GB0000562A
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GB0000562D0 (en
Inventor
Hidekazu Hasegawa
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NEC Corp
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NEC Corp
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Publication of GB0000562D0 publication Critical patent/GB0000562D0/en
Publication of GB2345578A publication Critical patent/GB2345578A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76237—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials introducing impurities in trench side or bottom walls, e.g. for forming channel stoppers or alter isolation behavior
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface

Abstract

A method of manufacturing a semiconductor device, wherein impurity ions are selectively introduced to a semiconductor substrate, at a corner portion of a trench 12 near an opening of the trench 12. The semiconductor substrate is then thermally oxidized to form an oxide film on an inner surface of the trench. An anti-etching film 24 is formed on the semiconductor substrate 11, the anti-etch film 24 is used as a mask to form the trench 12. Preferably, the impurity ions are phosphorous ions. The anti-etching layer may include silicon oxide, silicon nitride and a resist. The impurity-ion introducing step may include changing the angle of injection of the impurity ions whilst maintaining the acceleration energy substantially constant. Prior to introducing the ions, the corners of the trench 12 may be rounded by etching. The semiconductor device may be a gate electrode, or a gate line (15b Figure 2A). The trenches may be isolation trenches for MOSFETs, isolation trenches for bipolar transistors, or capacitor trenches.

Description

METHOD FOR FORMING A TRENCH ON A SEMICONDUCTOR DEVICE BACKGROUND OF THE INVENTION (a) Field of the Invention The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device having a trench used for element isolation or a capacitor structure.
(b) Description of a Related Art With the recent development of etching techniques, a trench having a higher aspect ratio, i. e., ratio of the width of the trench to the depth thereof, can be formed in a semiconductor device. Thus, for a higher element density, semiconductor devices having trenches are increasingly used, wherein element regions are separated by an isolation trench, or a capacitor has a trench-based structure.
Such kind of trenches known as element isolation trenches include ones described in Patent Publications JP-A10-4137 and JP-A-10-242259, wherein the trench techniques are applied to element isolation trenches for isolating element regions in which insulated-gate field-effect transistors (MOSFETs) are formed. It is also known that the trench technique is applied to the structure of a capacitor in a MOSFET device (refer to JP-A-3-84924, for example).
Figs. 1A to 1C show consecutive steps of the process for forming element isolation trenches. In Fig. 1A, a silicon oxide film 32 and a silicon nitride film 33 are consecutively formed on a semiconductor substrate 31. Subsequently, as shown in Fig. 1B, the silicon nitride film 33 and the silicon oxide film 32 are patterned to have an opening 35 by using a photoresist film 34 as a mask. Thereafter, the semiconductor substrate 31 is etched through the opening 35 to form a trench 36, followed by removal of the photoresist film 34, the silicon nitride film 33 and the silicon oxide film 32. At this stage, the corner 36a of the trench 36 at the top opening is substantially right-angled.
Next, as shown in Fig. 1C, another silicon oxide film 37 is formed by thermal oxidation of the surface of the semiconductor substrate 31 including the inner surface of the trench 36, followed by forming another silicon nitride film 38 on the another silicon oxide film 37 for prevention of further oxidation thereof. Subsequently, another thermal oxidation is conducted at a temperature above 1000'C, usually above 1100 C, to form another silicon oxide film 39 on the inner surface of the trench 36.
Thereafter, the trench 36 is filled with a suitable filling material such as a polycrystalline silicon (polysilicon), followed by oxidation of the surface of the polysilicon exposed through the top opening of the trench 36 to obtain an element isolation region.
In the above process for forming the isolation trench, since the corner 36b of the trench opening is made round by the thermal oxidation, the stress acting on the isolation trench 36 is alleviated, whereby generation of the crystal defects can be suppressed at the corner 36b of the trench opening.
In the conventional process, however, with the increase in the size of the wafer and thus the increase in the heat capacity thereof, the alleviation effect of the stress as described above is limited at a high temperature range above 1000 C, especially above 1100 C. Thus, crystal defects may be generated at the corner 36b of the trench opening and propagate toward the interior of the semiconductor substrate 31.
SUMMARY OF THE INVENTION It is therefore an object of the preferred embodiment of the present invention to provide a method for manufacturing a semiconductor device, which method is capable of effectively alleviating the stress when and after the thermal oxide film is formed on a trench, to thereby prevent the crystal defects from generating on the corner of the trench at the opening. The present invention also provides a semiconductor device manufactured by the method as described above.
The present invention provides a method for manufacturing a semiconductor device comprising the steps of forming an anti-etching film on a semiconductor substrate, selectively etching the semiconductor substrate by using the anti-etching film as a mask to form a trench having a top opening, selectively introducing impurity ions to the semiconductor substrate at a corner portion of the trench near the top opening, and thermally oxidizing the semiconductor substrate to form an oxide film on an inner surface of the trench.
In accordance with the method of the present invention and a semiconductor device manufactured by the method, impurity ions, such as phosphorous ions, are introduced in the semiconductor substrate by ion-implantation at the corner portion of the trench opening, followed by a thermal oxidation of the semiconductor substrate to form an oxide film on the inner surface of the trench. Since thermal oxidation is accelerated in the corner portion of the trench wherein the impurity ions are introduced, the subsequent thermal oxidation provides a larger thickness of the oxide film on the corner portion of the trench, even when the thermal oxidation is conducted at a lower temperature. The larger thickness of the thermal oxide film at the corner portion prevents reduction of the breakdown voltage of the gate electrode at a location where the gate electrode passes over the trench.
A lower temperature for the thermal oxidation, if employed, reduces the thermal stress generated during the thermal oxidation due to the difference between the thermal expansion coefficients of the oxide film and the semiconductor substrate. Thus, crystal defects are not likely to occur at the corner portion of the trench. In this case, even the ion-implantation in a direction slanted with respect to the injected surface can provide a deep injection in the semiconductor substrate. It is preferable in this respect to remove at least one of the anti-etching layer structure at the corner portion of the trench near the opening.
It is preferable that the injection angle of the impurity ions be changed, with the acceleration energy thereof being maintained at a constant. This results from the depth of the ion-implantation being larger at the top portion of the injected region and smaller at the bottom portion of the injected region. Thus, the roundness of the trench corner at the opening can be improved.
It is also preferable that the corner portion of the trench at the opening be etched to have a round surface.
This provides further alleviation of the mechanical stress after the thermal oxidation, in addition to the reduced thermal stress during the thermal oxidation due to the lower temperature of the thermal oxidation. Thus, the crystal defects at the corner of the trench at the opening can be further reduced.
BRIEF DESCRIPTION OF THE DRAWINGS Preferred features of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figs. 1A to 1C are sectional views of a semiconductor device in consecutive steps of fabrication thereof Fig. 2A is a top plan view of a semiconductor device according to a first embodiment of the present invention, and Figs. 2B and 2C are sectional views taken along A-A and B-B, respectively, in Fig. 2A.
Figs. 3A to 3D are sectional views of the semiconductor device of Fig. 2A in consecutive steps of fabrication thereof.
Fig. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
Fig. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
Fig. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention.
Figs. 7A to 7C are sectional views of a semiconductor device according to a fifth embodiment of the present invention, in consecutive steps thereof.
PREFERRED EMBODIMENTS OF THE INVENTION Now, the present invention is more specifically described with reference to accompanying drawings, wherein similar constituent elements are designated by similar reference numerals.
Ftrst Fmbodiment Referring to Figs. 2A, 2B and 2C showing a semiconductor device according to a first embodiment of the present invention, the semiconductor device includes a square element region 101 disposed on a main surface of a p-type silicon substrate 11. An element isolation region 102 receives therein an nMOSFET, including heavily doped n± source/drain regions 16a and 16b formed on the surface area of the silicon substrate 11 and a gate electrode 15b overlying the silicon substrate 11 with an intervention of a gate oxide film 14.
The element region 101 is surrounded or isolated by the element isolation region 102 implemented by an isolation trench 12. The isolation trench 12 is covered by an insulator film 13 on the inner surface thereof and further filled with a dielectric film 17 made of polysilicon. The insulator film 13 has a larger thickness at the corner of the isolation trench 12 at the opening, where the isolation trench 12 has a round surface.
The gate electrode 15b extends over the element region 101, crossing the isolation trench 12, to be connected to a gate pad 15a outside the element region 101. An interlevel dielectric film 18 covering the nMOSFET has through-holes 19a and 19b on the source/drain regions 16a and 16b.
Referring to Figs. 3A to 3D, there are shown consecutive steps of a process according to a first embodiment of the present invention for fabricating the semiconductor device of Fig. 2. In Fig. 3A, a semiconductor substrate (silicon substrate) 11 made of a single crystalline silicon is thermally treated at a temperature of 850 C to form a 20-nm-thick silicon oxide film 21 on the surface of the silicon substrate 11 by a thermal oxidation technique.
Subsequently, a silicon nitride film 22 is deposited to a thickness of 100 to 200 nm by a low pressure chemical vapor deposition (LPCVD) technique.
Thereafter, as shown in Fig. 3B, a resist film (photoresist film) 23 is formed on the silicon nitride film 22, followed by patterning thereof by a photolithographic technique to form an opening for a trench. The silicon oxide film 21, the silicon nitride film 22 and the photoresist film 23 constitute an anti-etching layer structure 24 for prevention of etching of the silicon substrate 11 in the later step.
Then, the silicon nitride film 22 and the silicon oxide film 21 are subjected to etching by using the photoresist film 23 as a mask to form an opening 24a in the silicon nitride film 22 and the silicon oxide film 21. Further, the silicon substrate 11 is etched by using SF6 gas through the opening 24a of the anti-etching layer structure 24 to form a trench 12.
Thereafter, as shown in Fig. 3C, with the photoresist film 23, the silicon nitride film 22 and the silicon oxide film remaining on the silicon substrate 11, ion-implantation is conducted wherein phosphorous ions are injected through the opening of the trench 12 to the silicon substrate 11. The acceleration energy for the phosphorous ions are 70 keV, for example, and the injection angle is maintained at 45"with respect to the side walls of the trench. The ion-implantation forms an impurity-injected region 25a in the silicon substrate 11 at the corner 12a of the trench 12.
Next, after the photoresist film 23 is removed, as shown in Fig. 3D, a thermal oxidation process is conducted in an oxidation ambient at a substrate temperature as low as about 900 C to form a 400-angstrom-thick silicon oxide film 13 on the inner surface (bottom and side surfaces) of the trench 12.
In an alternative, the silicon nitride film 22 and the silicon oxide film 21 in addition to the photoresist film 23 may be removed before the thermal oxidation. In this case, another silicon oxide film is formed on the entire surface of the semiconductor substrate including the inner surface of the trench, followed by formation of another silicon nitride film as an anti-oxidation film on the silicon oxide film in the element region, and a thermal oxidation to form the silicon oxide film 23 on the inner surface of the trench by using the another silicon nitride film as a mask.
Thereafter, the trench is filled with, for example, a polysilicon film acting as a filling material, followed by oxidation of the surface of the polysilicon film exposed from the trench 12, thereby achieving an element isolation region 102.
As described above, the method of the present embodiment includes the step of ion-implantation of phosphorous into the semiconductor substrate at the corner of the trench 12 near the opening and in the vicinities thereof, and the subsequent step of thermal oxidation of the inner surface of the trench to form the silicon oxide film.
The corner portion of the semiconductor substrate injected with phosphorous ions has a higher oxidation rate, whereby the subsequent thermal oxidation of the inner surface of the trench conducted even at a lower temperature of 900 C allows a thick silicon oxide film to be formed on the inner surface of the trench, especially at the corner of an opening of the trench 12. This allows the corner of the opening of the trench 12 to have a round surface and. together with the function of the thick silicon oxide film, prevents the reduction of the breakdown voltage of the gate passing over the trench.
The thermal oxidation at a lower temperature reduces the thermal stress due to the difference between the thermal expansion coefficients of the silicon oxide film 13 and the silicon substrate 11 during the thermal oxidation. This suppresses generation of the crystal defects at the corner 12b of the trench 12 without using the step of etching the corner of the trench 12 at the opening to have a round surface before the thermal oxidation. In addition, the thermal stress of the silicon substrate 11 applied from the silicon oxide film 21 after the thermal oxidation can be reduced, which allows further suppression of the crystal defects generated especially at the corner of the opening of the trench 12.
Second Embodiment Referring to Fig. 4, there is shown a semiconductor device at a step of a process according to a second embodiment of the present invention. The second embodiment is similar to the first embodiment except that the photoresist film 23 of the anti-etching layer structure 24 used for forming the trench 12 is removed at the corner of the trench 12 near the opening in the present embodiment before ion-implantation of phosphorous at the corner of the trench 12. In the first embodiment, as described before, the ion-implantation for the corner of the opening of the trench 12 is conducted at an angle slanted from the injected surface. At this step, a portion of the photoresist film 23 used for forming the trench may be an obstacle for the ionimplantation at the corner of the trench 12 near the opening.
The second embodiment removes the possibility of the obstacle.
In the second embodiment, an impurity-injected region 25b is formed at the corner 12b of the trench opening in the semiconductor substrate 11, similarly to the case of the first embodiment. In the present embodiment, the removal of the photoresist film 23 at the corner of the trench 12 allows a deep injection for the ion-implantation into the semiconductor substrate 11 even when the injection angle is larger compare to the first embodiment.
Third Embodiment Referring to Fig. 5, there is shown a semiconductor device at a step, similar to the step of Fig. 4, of a process according to a third embodiment of the present invention.
The third embodiment is similar to the second embodiment except that the photoresist film 23 is entirely removed in the present embodiment before the ion-implantation step for the corner of the trench 12 near the opening. The third embodiment provides a similar advantage.
Fourth Embodiment Referring to Fig. 6, there is shown a semiconductor device at a step, similar to the step of Fig. 4, of a process according to a fourth embodiment of the present invention.
The fourth embodiment is similar to the first embodiment except that the injection angle is changed during the ionimplantation. In the present embodiment, with the acceleration energy for the impurity ions being maintained at a constant, the ion-implantation provides a deep injection at the top portion of the impurity-injected region 25d and a shallow injection at the bottom portion of the impurityinjected region 25d, as shown in the drawing. This configuration allows the corner of the trench 12 near the opening to have a natural and larger radius at the round surface.
Fifth Embodiment Referring to Figs. 7A to 7C, there is shown a process according to a fifth embodiment of the present invention.
The fifth embodiment is similar to the first embodiment except that the corner of the trench 12 is etched after the trench 12 is formed and before the corner of the trench 12 near the opening is subjected to the ion-implantation.
More specifically, in the present embodiment, an antietching layer structure including a silicon oxide film, a silicon nitride film and a photoresist film is used to form a trench similarly to the steps of Figs. 3A and 3B of the first embodiment. Then, as shown in Fig. 7A, the silicon oxide film 21 is selectively etched at the edge thereof through the opening of the anti-etching layer structure by a side etching technique using a fluorinated acid solution, for example.
Thus, the corner of the trench 12 near the opening in the silicon substrate 11 is exposed from the anti-etching layer structure. Then, the silicon substrate 11 is etched at the exposed corner of the trench 12 near the opening by a chemical dry etching (CDE) technique to have a round surface 27 at the corner.
Subsequently, as shown in Fig. 7B, phosphorous ions are injected through the opening of the anti-etching layer structure and the trench opening to the round corner 27 of the trench 12 to form an impurity-injected region 25e.
Then, as shown in Fig. 7C, after the photoresist film 23 is removed, the wafer is subjected to a thermal oxidation in an oxidation ambient at a substrate temperature as low as about 900 C to form a silicon oxide film 13 on the inner surface of the trench 12. The impurity-injected region 25e has a higher oxidation rate during the thermal oxidation and thus is covered with a thick silicon oxide film by the lower temperature of the thermal oxidation. As a result, the corner portion of the trench 12 near the trench opening has a large radius and is covered with a silicon oxide film having a sufficient thickness. Thereafter, ordinary steps are conducted to the semiconductor device to have a structure similar to that shown in Figs. 2B and 2C.
In the present embodi. ment, the etching step for forming a round surface of the corner of the trench 12 near the trench opening functions to alleviate the thermal stress due to the lower temperature and the mechanical stress due to the configuration of the corner. Thus, in the semiconductor device fabricated by the present embodiment, reduction in the breakdown voltage of the gate passing over the trench can be suppressed, and the suppression of crystal defects is ensured.
In the above embodiments, element isolation trenches for isolating the element regions for MOSFETs are exemplified. However, the present invention can be applied to element isolation regions for bipolar transistors or other elements.
The present invention can be also applied to capacitor trenches.
The anti-etching layer structure in the above embodiments is formed by a silicon oxide film, a silicon nitride film and a photoresist film. However, the anti-etching layer structure may be implemented by a single resist film, a two-layer structure including a silicon oxide film and a resist film or other layer structure including a single film or a plurality of film having an anti-etching property.
The acceleration energy for the impurity ions and/or the injection angle may be designed to have any desired value.
Since the above embodiments are described only for examples, the present invention is not limited to the above embodiments, and various modifications or alterations can be easily made therefrom by those skilled in the art without departing from the scope of the present invention.
Each feature disclosed in this specification (which term includes the claims) and/or shown in the drawings may be incorporated in the invention independently of other disclosed and/or illustrated features.
Reference numbers appearing in the claims are by way of illustration only and should be disregarded when interpreting the scope of the claims.
The text of the abstract filed herewith is repeated here as part of the specification.
A method for forming an element isolation region includes the steps of etching a semiconductor substrate by using a silicon oxide film, a silicon nitride film and a resist film as a mask to form a trench, injecting impurity ions to the semiconductor substrate at the corner of an opening of the trench, thermally oxidizing the inner surface of the trench, and filling the trench with a polysilicon film. A thick oxide film is formed at the corner of the trench due to a higher oxidation rate. A higher breakdown voltage can be obtained for the gate passing over the trench.

Claims (12)

CLAIMS:
1. A method for manufacturing a semiconductor device, comprising the steps of forming an anti-etching film (24) on a semiconductor substrate, selectively etching the semiconductor substrate (11) by using the anti-etching film (24) as a mask to form a trench (12) having an opening, selectively introducing impurity ions to the semiconductor substrate (11) at a corner portion of the trench (12) near the opening, and thermallyoxidizing the semiconductor substrate (11) to form an oxide film (13) on an inner surface of the trench (12).
2. The method as defined in claim 1, wherein the impurity ions are phosphorous ions.
3. The method as defined in claim 1 or 2, wherein the anti-etching layer (24) includes a silicon oxide film (21), a silicon nitride film (22) and a resist film (23) consecutively formed on the semiconductor substrate (11).
4. The method as defined in claim 3, wherein at least an edge portion of the resist film (23) is removed near the trench.
5. The method as defined in one of claims 1 to 4, further comprising, before the impurity-ion introducing step, the step of selectively etching the semiconductor substrate (11) at the corner portion of the trench to form a substantially-round corner (27).
6. The method as defined in one of claims 1 to 5, wherein said impurity-ion introducing step is such that an injection angle of the impurity ions is changed, with an acceleration energy of the impurity ions being maintained substantially at a constant.
7. The method as defined in one of claims 1 to 6, wherein the trench (12) isolates an element region (102).
8. The method as defined in claim 7, further comprising, after the thermally-oxidizing step, the step of filling the trench (12) with a polysilicon film (17).
9. A semiconductor device manufactured by the method defined in one of claims 1 to 8.
10. The semiconductor device as defined in claim 9, wherein said semiconductor device comprises a gate electrode or gate line (15b) passing over the trench.
11. A method for manufacturing a semiconductor device, the method being substantially as herein described with reference to and as shown in Figures 2A to 7C of the accompanying drawings.
12. A semiconductor device substantially as herein described with reference to and as shown in Figures 2A to 7C of the accompanying drawings.
GB0000562A 1999-01-11 2000-01-11 A method of manufacturing a semiconductor device including a trench Withdrawn GB2345578A (en)

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JP11004531A JP2000208606A (en) 1999-01-11 1999-01-11 Semiconductor device and production thereof

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GB2345578A true GB2345578A (en) 2000-07-12

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EP2159835A1 (en) * 2008-08-27 2010-03-03 Magnachip Semiconductor Ltd. Semiconductor device and method for fabricating the same

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KR100608386B1 (en) * 2005-06-30 2006-08-08 주식회사 하이닉스반도체 Method of manufacturing semiconductor device
CN100416793C (en) * 2005-11-24 2008-09-03 上海华虹Nec电子有限公司 Method for improving isolation effect of apparatus in shallow groove isolation techniques
JP2008135458A (en) * 2006-11-27 2008-06-12 Elpida Memory Inc Semiconductor device and its fabrication process
CN102110708A (en) * 2011-01-14 2011-06-29 北方工业大学 High-voltage isolation trench and manufacturing method thereof and metal oxide semiconductor (MOS) device
CN108109992B (en) * 2017-12-15 2020-08-11 温州曼昔维服饰有限公司 Manufacturing method of MIM capacitor

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US5057444A (en) * 1985-03-05 1991-10-15 Matsushita Electric Industrial Co., Ltd. Method of fabricating semiconductor device
US5112762A (en) * 1990-12-05 1992-05-12 Anderson Dirk N High angle implant around top of trench to reduce gated diode leakage
US5798553A (en) * 1995-01-10 1998-08-25 International Business Machines Corporation Trench isolated FET devices, and method for their manufacture

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JPS63133664A (en) * 1986-11-26 1988-06-06 Matsushita Electronics Corp Manufacture of semiconductor device
US5112762A (en) * 1990-12-05 1992-05-12 Anderson Dirk N High angle implant around top of trench to reduce gated diode leakage
US5798553A (en) * 1995-01-10 1998-08-25 International Business Machines Corporation Trench isolated FET devices, and method for their manufacture

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2159835A1 (en) * 2008-08-27 2010-03-03 Magnachip Semiconductor Ltd. Semiconductor device and method for fabricating the same
US8431465B2 (en) 2008-08-27 2013-04-30 Magnachip Semiconductor, Ltd. Semiconductor device and method for fabricating the same

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KR20000053417A (en) 2000-08-25
GB0000562D0 (en) 2000-03-01
JP2000208606A (en) 2000-07-28
CN1260586A (en) 2000-07-19

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