KR20040008635A - Method for fabricating bitline conatct hole using anti-reflection coating - Google Patents

Abstract

PURPOSE: A method for forming a bitline contact hole is provided to simplify manufacturing processes and to reduce manufacturing costs by using a single anti-reflective layer. CONSTITUTION: An interlayer dielectric(39) is formed on a substrate(31) defined by a cell region and a peripheral region. An anti-reflective layer(40) is formed on the interlayer dielectric. The first bitline contact hole is formed by selectively etching the interlayer dielectric using the first mask for defining the first bitline contact of the cell region. After removing the first mask using thinner, the second mask(43) is formed on the remaining anti-reflective layer(40) to define the second bitline contact of the peripheral region. The second bitline contact hole(44) is then formed by using the second mask. The second mask and the anti-reflective layer are simultaneously removed by using oxygen plasma.

Description

Method for fabricating bitline conatct hole using anti-reflection coating}

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device using an anti-reflection film technology.

In recent years, as the degree of integration of a circuit formed on a semiconductor substrate increases, individual elements on the semiconductor substrate are miniaturized and feature sizes of the circuit are reduced, so that fine pattern formation is required.

In a conventional photolithography process, a photoresist film is coated on a multilayer made of various materials formed on a semiconductor substrate, a predetermined portion of the photoresist film is exposed to light rays, and then subjected to a development process to form a photoresist pattern. In this case, in order to realize a photolithography process having a higher resolution, it is essential to form an anti reflection coating (ARC) under the photosensitive film in advance to suppress diffuse reflection from the underlying film generated during the exposure process.

1A to 1C are cross-sectional views illustrating a method of forming a bit line contact hole using an anti-reflection film according to the prior art.

As shown in FIG. 1A, after the field oxide film 12 is formed on the semiconductor substrate 11 in which the cell region and the peripheral circuit region are defined by using a shallow trench isolation (STI) method, the semiconductor substrate 11 is formed. ), The gate lines stacked in the order of the gate oxide film 13, the gate electrode 14, and the hard mask 15 are formed.

Here, the gate line is formed by first depositing the gate oxide film 13, the conductive film for the gate electrode 14, and the hard mask 15 in order, and then applying a photoresist film on the hard mask 15, and exposing and Through development, a mask defining a gate line is formed. Next, the hard mask is first etched using the mask as an etch mask, and then the mask is removed, and the conductive film for the gate electrode 14 and the gate oxide film 13 are etched using the etched hard mask 15 as an etch mask. Form a gate line.

On the other hand, the hard mask 15 uses an oxide film or a nitride film. In order to facilitate the subsequent contact etching process, a nitride film having an excellent etching selectivity with respect to the oxide film, which is an interlayer insulating film, is used.

Next, after the insulating film is deposited on the entire surface including the gate line, a spacer 16 is formed to contact both sidewalls of the gate line through the entire surface etching process.

Next, after forming the first interlayer insulating layer (ILD, 17) on the entire surface including the spacer 16, the first interlayer insulating layer 17 is etched to expose the contact hole for exposing the semiconductor substrate 11 between the gate lines. Form. In this case, the contact hole is formed only in the cell region. After the polysilicon film is deposited on the entire surface including the contact hole, chemical mechanical polishing (CMP) is performed until the surface of the hard mask 15 is exposed to form the polysilicon plug 18. Here, the polysilicon plug 18 is a contact plug to which a subsequent bit line is contacted and a contact plug to which a storage node contact is to be contacted, and is formed only in the cell region, and the hard mask 15 may be partially lost during chemical mechanical polishing.

Next, the second interlayer insulating film 19 and the first antireflection film 20 are sequentially formed on the entire surface of the semiconductor substrate 11 on which the polysilicon plug 18 is formed, and then on the first antireflection film 20. Is applied and patterned by exposure and development to form a first mask 21 defining a first bit line contact BLC1 of the cell region.

Next, the first bit line contact hole 22 exposing the polysilicon plug 18 by sequentially etching the first anti-reflection film 20 and the second interlayer insulating film 19 using the first mask 21 as an etching mask. ). The first bit line contact hole 22 is formed because the bit line contact holes of the cell region and the peripheral circuit region are formed, respectively, and the bit line contact hole to be formed in the subsequent peripheral circuit region is formed in the second bit line contact hole. This is called.

As shown in FIG. 1B, after removing the first mask 21 and the first anti-reflection film 20 using oxygen plasma, a second anti-reflection film 23 is formed on the entire surface, and the second anti-reflection film 23 is formed. The photoresist film is coated on the photoresist layer and patterned by exposure and development to form a second mask 24 defining the second bit line contact BLC2.

Next, the second bit line contact hole exposing the upper portion of the gate line of the peripheral circuit region by sequentially etching the second anti-reflection film 23 and the second interlayer insulating film 19 using the second mask 24 as an etching mask ( 25). That is, the second bit line contact hole 25 is formed by performing an etching process under the condition that the hard mask 15 on the gate line is etched. In the drawing, the second bit line contact hole 25 is formed on the gate line. Although formed, the active region of the semiconductor substrate 11 may be exposed.

As shown in FIG. 1C, after the second mask 24 and the second anti-reflection film 23 are removed using oxygen plasma, the first bit line contact hole 22 and the second bit line contact hole 25 are removed. Bit lines 26a and 26b connected to each other are formed.

However, in the above-described conventional technology, since the anti-reflection film is introduced twice to form the bit line contact holes in the cell region and the peripheral circuit region, the process is complicated and the cost is increased.

The present invention has been made to solve the above problems of the prior art, and reduces the complexity and cost of the process by introducing the anti-reflection film twice in forming the bit line contact holes in the cell region and the peripheral circuit region, respectively. It is an object of the present invention to provide a method for forming a bit line contact hole suitable for use.

1A to 1C are cross-sectional views illustrating a method for forming a bit line contact hole using an anti-reflection film according to the prior art;

2A to 2D are cross-sectional views illustrating a method of forming a bit line contact hole using an anti-reflection film according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

31 semiconductor substrate 32 field oxide film

33: gate oxide film 34: gate electrode

35: hard mask 36: spacer

37: first interlayer insulating film 38: polysilicon plug

39: second interlayer insulating film 40: antireflection film

41: first mask 42: first bit line contact hole

43: second mask 44: second bit line contact hole

45a, 45b: bit line

A method of forming a bit line contact hole according to the present invention for achieving the above object is to form an interlayer insulating film on the semiconductor substrate defined in the cell region and the peripheral circuit region, forming an anti-reflection film on the interlayer insulating film, the reflection Forming a first mask defining a first bit line contact to be formed in the cell region on the protection layer, etching the interlayer insulating layer using the first mask as an etch mask to form a first bit line contact hole; Selectively removing the first mask; forming a second mask defining a second bit line contact to be formed in the peripheral circuit region on the anti-reflection film remaining after removing the first mask; Etching the interlayer insulating layer using an mask as an etch mask to form a second bit line contact hole, and simultaneously forming the second mask and the anti-reflection film And removing the first mask by using a thinner, and simultaneously removing the second mask and the anti-reflective coating by using an oxygen plasma.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

2A to 2D are cross-sectional views illustrating a method of forming a bit line contact hole according to an exemplary embodiment of the present invention.

As shown in FIG. 2A, after the field oxide film 32 is formed on the semiconductor substrate 31 in which the cell region and the peripheral circuit region are defined by the device isolation method, the field oxide film 32 is formed, the gate oxide film is formed on the semiconductor substrate 31. (33), the gate electrodes 34 and the hard mask 35 are stacked in this order.

Here, in the method of forming the gate line, first, the gate oxide film 33, the conductive film for the gate electrode 34, and the hard mask 35 are sequentially deposited, and then a photoresist film is applied on the hard mask 35, and the exposure and Through development, a mask defining a gate line is formed. Next, the hard mask 35 is etched first using the mask as an etch mask and then the mask is removed, and the conductive film and gate oxide film 34 for the gate electrode 34 are etched using the etched hard mask 35 as an etch mask. Is etched to form a gate line.

On the other hand, the hard mask 35 uses an oxide film or a nitride film. In order to facilitate the subsequent contact etching process, a nitride film having an excellent etching selectivity with respect to the oxide film, which is an interlayer insulating film, is used.

Next, after the insulating film is deposited on the entire surface including the gate line, a spacer 36 is formed in contact with both sidewalls of the gate line through the entire surface etching process.

Next, after forming the first interlayer insulating layer (ILD) 37 on the entire surface including the spacer 36, the contact hole for etching the first interlayer insulating layer 37 to expose the semiconductor substrate 31 between the gate lines. Form. In this case, the contact hole is formed only in the cell region. After the polysilicon film is deposited on the entire surface including the contact hole, chemical mechanical polishing (CMP) is performed until the surface of the hard mask 35 is exposed to form the polysilicon plug 38. Here, the polysilicon plug 38 is a contact plug to which a subsequent bit line is contacted and a contact plug to which a storage node contact is to be contacted, and is formed only in the cell region, and the hard mask 35 may be partially lost during chemical mechanical polishing.

Next, a second interlayer insulating film 39 and an antireflection film 40 are sequentially formed on the entire surface of the semiconductor substrate 31 on which the polysilicon plug 38 is formed, and then a photosensitive film is coated on the antireflection film 40 and exposed. And a first mask 41 defining the first bit line contact BLC1 by patterning with development. Here, the anti-reflection film uses a known technique, for example, a silicon oxynitride film (SiON), which is formed by chemical vapor deposition (CVD) or physical vapor deposition (PVD). Can be.

Next, the first bit line contact hole 42 exposing the polysilicon plug 38 by sequentially etching the anti-reflection film 40 and the second interlayer insulating film 39 using the first mask 41 as an etch mask. Form.

As shown in FIG. 2B, only the first mask 41 is selectively removed using a thinner.

The above-described thinner is a thinner composition used in an edge rinse process formed after the photosensitive film is applied. Here, the edge rinse process refers to a process of cleaning and removing unnecessary photoresist film generated at the edge portion of the wafer when spin-coating the photoresist film on the wafer to form the photoresist film.

Meanwhile, as the thinner composition, single solvents such as ethylene glycol monoethyl ether acetate (EGMEA), propylene glycol monomethyl ether acetate (PGMEA; propyleneglycol monomethylether acetate) and ethyl lactate (EL; ethyl lactate), and pyrufinic acid A mixture of an alkyl solvent and methyl ethyl ketone, a mixture of propylene glycol alkyl ether and alkyl 3-alkoxypropionate, a mixture of propylene glycol alkyl ether, butyl acetate and ethyl lactate, butyl acetate and ethyl lactate, and propylene glycol alkyl ether A mixture of acetate, a mixture of propylene glycol alkylether propionate and methylethyl ketone, a mixture of propylene glycol alkylether propionate and butyl acetate, propylene glycol alkylether acetate and propylene glycol alkylether A mixture consisting of a mixture, ethyl lactate and methyl ethyl ketone is selected and used.

After forming the first bit line contact hole 42, the thinner composition may be added dropwise to the surface of the first mask 41 or sprayed through a nozzle to remove the first mask 41. The amount of the thinner composition can be adjusted according to the type and thickness of the photosensitive film to be used.

As shown in FIG. 2C, the second mask 43 defining the second bit line contact BLC2 of the peripheral circuit area by applying the photoresist film again on the remaining antireflection film 40 and patterning by exposure and development is performed. Form.

Next, the second bit line contact hole 44 exposing the upper portion of the gate line of the peripheral circuit area by sequentially etching the anti-reflection film 40 and the second interlayer insulating film 39 using the second mask 43 as an etch mask. To form. That is, the second bit line contact hole 44 is formed by performing an etching process under the condition that the hard mask 35 on the gate line is etched. In the drawing, the second bit line contact hole 44 is formed on the gate line. Although formed, the active region of the semiconductor substrate 31 may be exposed.

As shown in FIG. 2D, after the second mask 43 and the anti-reflection film 40 are removed using oxygen plasma, the first bit line contact hole 42 and the second bit line contact hole 44 are respectively removed. Bit lines 45a and 45b connected to each other are formed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention as described above has the effect of simplifying the process by introducing the anti-reflection film only once.

In addition, there is an effect that the cost can be reduced by using a relatively inexpensive thinner compared to the track normally used in place of the plasma equipment using oxygen plasma, that is, the coating and developing equipment and the oxygen gas.

Claims (4)

Forming an interlayer insulating film over the defined semiconductor substrate in the cell region and the peripheral circuit region; Forming an anti-reflection film on the interlayer insulating film; Forming a first mask on the anti-reflection film to define a first bit line contact to be formed in the cell region; Etching the interlayer dielectric layer using the first mask as an etch mask to form a first bit line contact hole; Selectively removing the first mask; Forming a second mask on the anti-reflection film remaining after removing the first mask to define a second bit line contact to be formed in the peripheral circuit region; Etching the interlayer dielectric layer using the second mask as an etch mask to form a second bit line contact hole; And Simultaneously removing the second mask and the anti-reflection film Bit line contact hole forming method comprising a. The method of claim 1, Selectively removing the first mask, A method for forming a bit line contact hole, comprising using thinner. The method of claim 1, Simultaneously removing the second mask and the anti-reflection film, A method of forming a bit line contact hole, characterized by using an oxygen plasma. The method of claim 1, The first mask and the second mask is formed by applying a photosensitive film and patterning by exposure and development, respectively.