KR20040007950A - Method of manufacture semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to be capable of reducing the resistance of a PMOS(P channel Metal Oxide Semiconductor) silicide layer, improving thermal stability of the silicide layer, and preventing the increase of junction leakage current. CONSTITUTION: After a gate and a gate spacer(5) are sequentially formed at the upper portion of a semiconductor substrate(1), a source/drain region(6) are formed at both sides of the gate in the semiconductor substrate. After an SOG(Spin On Glass) layer is formed on the resultant structure, the upper surface of the gate is exposed to the outside by carrying out an etch-back process at the SOG layer using etching gas having a predetermined etching rate for the gate and gate spacer. After the first Co/TiN layer is formed on the resultant structure, the first silicide layer(9) is formed at the upper portion of the gate by carrying out an annealing process. After the second Co/TiN layer is formed on the resultant structure, the second silicide layer(11) is formed at the upper portion of the source/drain region by carrying out an annealing process.

Description

Method of manufacturing a semiconductor device {METHOD OF MANUFACTURE SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and in particular, by increasing the thickness of the silicide film formed in the polysilicon region to be thicker than the thickness of the silicide film formed in the active region, thereby increasing the polysilicon resistance without increasing leakage current. A method for manufacturing a semiconductor device that can be reduced.

In the semiconductor manufacturing process, especially in the logic device manufacturing process, silicide is applied to reduce the resistance because the operation speed of the device is a very important factor. This silicide forming process deposits metal and forms metal silicide by thermal process, in which silicide is formed only on the active region made of silicon and polysilicon, which is a gate forming material, but not on the remaining insulating material. It adopts the Salicide (Self Aligned Silicide) process. In particular, as the gate line width decreases to 0.18 μm or less, cobalt silicide having excellent resistance and stability is being applied.

However, since the silicide-formed region is very low in resistance, it cannot be applied in the region where a high resistance is required, and thus the non-salicide which covers the region where the silicide should not be formed with an insulating film and forms silicide in other regions. (Non-Salicide) process is required.

The non-salicide process deposits an insulating film on the entire surface of the wafer before forming the salicide, and protects the insulating film in the non-salicide region by using a photo mask, and the insulating film in the salicide forming region. Will be removed.

However, such an insulating film removal process mainly uses dry etching using plasma, and the etching damage generated at this time greatly degrades the polysilicon resistance of the PMOS transistor region. This deterioration of resistance is stabilized as the thickness of the silicide is increased, but the increase in the thickness of the silicide formation is the same in the active region as well as polysilicon, so the increase in the silicide thickness in the active region is accompanied by an increase in the junction leakage current. It will degrade.

Accordingly, the present invention has been made to solve the above problems, and an object of the present invention is to increase the leakage current by selectively increasing the thickness of the silicide film formed in the polysilicon region to be thicker than the thickness of the silicide film formed in the active region. It is to provide a method of manufacturing a semiconductor device that can reduce the polysilicon resistance without.

1 to 5 are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention.

(Explanation of symbols for the main parts of the drawing)

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2: Shallow trench separator

3: gate oxide film 4: gate polysilicon film

5: LDD spacer or gate spacer

6: source / drain area or active area

7: SOG film 9: first silicide film

8: first cobalt (Co) / titanium nitride (TiN) film

10: second cobalt (Co) / titanium nitride (TiN) film

11: second silicide film

A semiconductor device manufacturing method according to the present invention for achieving the above object,

Forming a gate and a gate spacer on a semiconductor substrate on which a shallow trench isolation (STI) film is formed;

Performing a N + / P + ion implantation process on the structure to form a source / drain region;

Forming a SOG film to a predetermined thickness by spin coating using spin on glass (SOG) on the structure;

Etching the gate top portion after the SOG film is formed by an etch back process using an etching gas having a high etching selectivity with respect to the gate and gate spacer materials without a photo mask;

Forming a first cobalt (Co) / titanium nitride (TiN) film on the structure;

Performing an annealing process on the structure to form a first silicide film on the gate and then removing the first cobalt (Co) / titanium nitride (TiN) film;

Removing the SOG film formed on the source / drain regions;

Forming a second cobalt (Co) / titanium nitride (TiN) film on the structure; And

And forming a second silicide layer on the source / drain region by performing an annealing process on the structure, and then removing the second cobalt (Co) / titanium nitride (TiN) layer.

The etching gas is characterized in that the etching gas of CF / Ar or CF / Ar.

It is characterized by performing an etch back process using dry etching using the etching gas and wet etching using a BOE or HF solution.

The thickness of the SOG film formed on the source / drain region during the etch back process may be about 1500 mW.

The SOG layer may be removed by wet etching using BOE (Buffered Oxide Etchant) or HF.

The thickness of the first silicide layer is formed to be thicker than the thickness of the second silicide layer.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the present invention.

First, as shown in FIG. 1, a shallow trench isolation (STI) film 2 for device isolation is formed on a silicon (Si) substrate 1. At this time, the STI film 2 is filled with an insulating film (or an oxide film) and processes a region other than active by a chemical mechanical polishing (CMP) process (planarization).

Then, P wells and N wells are formed in the silicon substrate 1.

Next, after the gate oxide film 3 and the polysilicon film 4 are deposited, a gate electrode is formed through a patterning process. At this time, the polysilicon film 4 is isotropically etched.

Next, NM / PM ions are implanted onto the structure.

Next, ion implantation is performed to form an LDD diffusion layer in the silicon substrate 1.

Next, a buffer oxide film 4a is formed on the silicon substrate 1 on which the gate sidewall and the LDD spacer will be formed.

Next, the LDD spacers 5 are formed on the sidewalls of the gate, and the source / drain regions 6 are formed by performing an N + / P + ion implantation process.

Next, an SOG film (500Å) 7 is formed by spin coating using spin on glass (SOG). In the case of such SOG, unlike other deposition methods, since the flow characteristic is very large, it is possible to form the SOG film 7 flat regardless of surface irregularities.

Next, as shown in FIG. 2, after forming the SOG film 7, CF / Ar or CF / Ar having a high selectivity with respect to the nitride film of the polysilicon 4 and the gate spacer 5 material without the photomask is used. Etchback processes are performed using dry etching using an etching gas and wet etching using a BOE or HF solution. At this time, the SOG film 7 is etched until the upper portion of the gate 4 is completely exposed, and the SOG film 7 is etched until the SOG film 7 has a thickness of about 1500 占 위에 over the active region of the source / drain region 6. . Therefore, after the etching is completed, all of the SOG film 7 on the gate polysilicon 4 is removed, and the SOG film 7 having a thickness of 1500 Å remains on the active region 6.

Next, as shown in FIGS. 2 and 3, a TiN film 8 made of cobalt (Co) and a capping material is formed on the structure, and then annealing is performed. As a result, the cobalt silicide film 9 is formed in the gate 4 where the polysilicon is exposed, while no reaction occurs in the active region covered with the SOG film 7.

Then, after the capping material and the unreacted cobalt (Co) film 8 are removed, a cobalt silicide film 9 is selectively formed only in the gate polysilicon region.

Next, as shown in FIG. 4, the SOG film 7 formed in the active region 6 is removed by a wet etching method using BOE (Buffered Oxide Etchant) or HF.

Next, as shown in FIGS. 4 and 5, the TiN film 10, which is cobalt (Co) and a capping material, is formed on the structure, and then annealing is performed. As a result, silicide 11 is formed in the active region 6 by the thickness thereof, whereas in the gate polysilicon region 4, not only the existing silicide is formed but also the silicide is formed by diffusion of additionally deposited cobalt (Co). Since 9 is formed, the thickness is increased.

As described above, according to the method of manufacturing a semiconductor device according to the present invention, the silicide thickness of the gate polysilicon region is increased to improve the resistance and thermal stability of the PMOS silicide, and also to maintain a constant silicide thickness in the active region. This prevents an increase in junction leakage current, allowing stable operation of the device.

In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (6)

Forming a gate and a gate spacer on a semiconductor substrate on which a shallow trench isolation (STI) film is formed; Performing a N + / P + ion implantation process on the structure to form a source / drain region; Forming a SOG film to a predetermined thickness by spin coating using spin on glass (SOG) on the structure; After forming the SOG layer, etching the gate top to be completely exposed by an etch back process using an etching gas having a high etching selectivity with respect to the gate and gate spacer materials without a photo mask; Forming a first cobalt (Co) / titanium nitride (TiN) film on the structure; Performing an annealing process on the structure to form a first silicide film on the gate and then removing the first cobalt (Co) / titanium nitride (TiN) film; Removing the SOG film formed on the source / drain regions; Forming a second cobalt (Co) / titanium nitride (TiN) film on the structure; And Performing a annealing process on the structure to form a second silicide layer on the source / drain region, and then removing the second cobalt (Co) / titanium nitride (TiN) layer. . The method of claim 1, The etching gas is a manufacturing method of a semiconductor device, characterized in that the etching gas of CF / Ar or CF / Ar. The method of claim 1, A method of manufacturing a semiconductor device, comprising performing an etch back process using dry etching using the etching gas and wet etching using a BOE or HF solution. The method of claim 1, The thickness of the SOG film formed on the source / drain region during the etch back process has a thickness of about 1500Åm. The method of claim 1, And removing the SOG layer by wet etching using BOE (Buffered Oxide Etchant) or HF. The method of claim 1, The thickness of the first silicide layer is formed to be thicker than the thickness of the second silicide layer.