KR20040007147A - Method for fabrication of dram device - Google Patents

Method for fabrication of dram device Download PDF

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Publication number
KR20040007147A
KR20040007147A KR1020020041805A KR20020041805A KR20040007147A KR 20040007147 A KR20040007147 A KR 20040007147A KR 1020020041805 A KR1020020041805 A KR 1020020041805A KR 20020041805 A KR20020041805 A KR 20020041805A KR 20040007147 A KR20040007147 A KR 20040007147A
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South Korea
Prior art keywords
gate
nitride film
forming
photoresist pattern
layer
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KR1020020041805A
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Korean (ko)
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KR100861357B1 (en
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김호웅
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82345—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

PURPOSE: A method for fabricating a DRAM device is provided to prevent the oxidation of metal gate and enhance the yield by using a nitride layer as a metal barrier. CONSTITUTION: A gate oxide layer(101) is formed by performing an oxidation process on a substrate including a well(100). An HDP oxide layer(102) is formed thereon. The first nitride layer(103) is deposited on the gate oxide layer(101). The first nitride layer is patterned on the first nitride layer(103). An oxide layer(105) is deposited on the first nitride layer. The second nitride layer(106) is deposited on the oxide layer(105). A spacer is formed thereon and the second photoresist pattern is formed. A contact is formed by performing an etch process. A doped silicon layer(108), a tungsten layer(109), and a hard mask nitride layer(110) are deposited within the contact. The third photoresist pattern is formed thereon. A gate spacer and a gate are formed by performing an etch process. A source/drain is formed by performing an ion implantation process.

Description

디램 소자의 제조 방법{METHOD FOR FABRICATION OF DRAM DEVICE}Method for manufacturing DRAM device {METHOD FOR FABRICATION OF DRAM DEVICE}

본 발명은 디램 소자의 게이트 형성시 메탈 게이트를 형성시 산화에 의한 공정의 어려움을 극복하기 위해 리버스 게이트를 적용하여 질화막을 장벽층으로 적용하여 메탈 게이트의 산화를 방지하고자 하는 디램 소자의 제조 방법에 관한 것이다.The present invention relates to a method of manufacturing a DRAM device to prevent oxidation of the metal gate by applying a nitride film as a barrier layer by applying a reverse gate in order to overcome the difficulty of the process of oxidation when forming a metal gate when forming a gate of the DRAM device. It is about.

일반적으로, 디램(dynamic random access memory)은 필드산화막 등의 분리구조를 기판에 형성하여 소자형성영역을 정의하고, 그 소자형성영역에 모스 트랜지스터를 제조한 후, 상기 모스 트랜지스터의 드레인에 접속되는 커패시터를 형성함과아울러 상기 모스 트랜지스터의 소스에 비트라인을 접속하여 제조되는 다수의 셀 트랜지스터를 포함하여 구성된다. 그 특성으로는 커패시터를 사용하여 전기적인 신호를 저장함으로써 자연방전에 의한 데이터의 손실을 방지하기 위해 일정한 시간마다 저장된 데이터를 다시 리프레시(refresh)해야한다.In general, a dynamic random access memory (DRAM) defines a device formation region by forming a separation structure such as a field oxide film on a substrate, manufactures a MOS transistor in the device formation region, and then connects the capacitor to the drain of the MOS transistor. And a plurality of cell transistors manufactured by connecting a bit line to a source of the MOS transistor. As a characteristic, it is necessary to refresh the stored data at regular time intervals in order to prevent the loss of data due to natural discharge by storing an electrical signal using a capacitor.

이러한 종래의 디램 트랜지스터 제조시 메탈 게이트를 적용하는데 이는 저항 감소 및 트랜지스터의 동작이 빠른 이점이 있으나, 이는 메탈의 산화로 인해 공정상의 문제가 발생한다.Metal gates are used in the fabrication of such conventional DRAM transistors, which have advantages such as resistance reduction and fast operation of transistors. However, this causes process problems due to oxidation of metals.

상기와 같은 문제를 해결하기 위한 본 발명은 리버스 게이트를 적용하여 질화막을 금속 장벽층으로 사용하여 메탈 게이트의 산화를 방지하기 위한 디램 소자의 제조 방법을 제공하는 것이다.The present invention for solving the above problems is to provide a method for manufacturing a DRAM device for preventing the oxidation of the metal gate using a nitride film as a metal barrier layer by applying a reverse gate.

도1a 내지 도1k는 본 발명에 의한 디램 소자의 제조 방법을 나타낸 단면도들이다.1A to 1K are cross-sectional views illustrating a method of manufacturing a DRAM device according to the present invention.

- 도면의 주요부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawings-

100 : 웰 101 : 게이트 산화막100 well 101 gate oxide film

102 : HLD 산화막 103 : 제 1 질화막102: HLD oxide film 103: first nitride film

104 : 제 1 포토레지스트 105 : 산화막104: first photoresist 105: oxide film

106 : 제 2 질화막 107 : 제 2 포토레지스트106: second nitride film 107: second photoresist

108 : 도프트 폴리실리콘 109 : 텅스텐108: doped polysilicon 109: tungsten

110 : 하드마스크용 질화막 111 : 제 3 포토레지스트 패턴Reference numeral 110: nitride film for hard mask 111: third photoresist pattern

112 :소오스/드레인112: source / drain

상기와 같은 목적을 실현하기 위한 본 발명은 웰이 형성된 기판 상에 산화 공정을 실시하여 게이트 산화막을 형성하는 단계와, 상기 게이트 산화막이 형성된 결과물 상에 HDP 산화막을 형성한 다음, 게이트 산화막 상부에 제 1 질화막을 증착하는 단계와, 상기 제 1 질화막 상부에 1 포토레지스트 패턴을 형성한 제 1 질화막을 패터닝하는 단계와, 상기 제 1 포토레지스트 패턴을 제거한 후 제 1 질화막 상부에 산화막을 증착하는 단계와, 상기 산화막 상부에 제 2 질화막을 증착하는 단계와, 상기 제 2 질화막이 증착된 결과물에 전면 식각을 통해 스페이서를 형성한 다음 제 2 포토레지스트 패턴을 형성하는 단계와, 상기 제 2 포토레지스트를 마스크로 식각 공정을 진행하여 콘택을 형성하는 단계와, 상기 콘택 내부에 도프트 폴리실리콘과 텅스텐 및 하드 마스크용 질화막을 증착하는 단계와, 상기 결과물 상에 제 3 포토레지스트 패턴을 형성한 후 식각 공정을 통해 게이트 스페이서를 형성하여 게이트를 형성한 후 이온 주입 공정을 통해 소오스/드레인을 형성하는 단계를 포함하는 것을 특징으로 하는 디램 소자의 제조 방법에 관한 것이다.The present invention for achieving the above object is performed by the step of forming a gate oxide film by performing an oxidation process on the substrate on which the well is formed, and forming an HDP oxide film on the resultant product formed with the gate oxide film, Depositing a first nitride film, patterning a first nitride film having a first photoresist pattern on the first nitride film, removing the first photoresist pattern, and depositing an oxide film on the first nitride film; And depositing a second nitride film on the oxide layer, forming a spacer through the entire surface etching on the resultant product of depositing the second nitride film, and then forming a second photoresist pattern, and masking the second photoresist. Etching to form a contact, and forming doped polysilicon, tungsten, and hard mask in the contact. Forming a gate spacer by forming a gate spacer through an etching process after forming a third photoresist pattern on the resultant, and forming a source / drain through an ion implantation process; The present invention relates to a method for manufacturing a DRAM device.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명한다. 또한 본 실시예는 본 발명의 권리범위를 한정하는 것은 아니고, 단지 예시로 제시된 것이며 종래 구성과 동일한 부분은 동일한 부호 및 명칭을 사용한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

도1a 내지 도1k는 본 발명에 의한 디램 소자의 제조 방법을 나타낸 단면도들이다.1A to 1K are cross-sectional views illustrating a method of manufacturing a DRAM device according to the present invention.

도1a를 참조하면, 웰(100)이 형성된 기판 상에 산화 공정을 실시하여 게이트 산화막(101)을 형성한 후 HDP 산화막(102)을 형성한 다음, 게이트 산화막(101) 상부에 제 1 질화막(103)을 증착한다.Referring to FIG. 1A, an oxidation process is performed on a substrate on which a well 100 is formed to form a gate oxide film 101, and then an HDP oxide film 102 is formed, and then a first nitride film (or upper portion) is formed on the gate oxide film 101. 103).

도1b를 참조하면, 제 1 포토레지스트 패턴(104)을 형성한 후 도1c에 도시된 바와 같이 제 1 포토레지스트 패턴(104)을 마스크로 제 1 질화막(103)을 패터닝한다.Referring to FIG. 1B, after forming the first photoresist pattern 104, the first nitride film 103 is patterned using the first photoresist pattern 104 as a mask, as shown in FIG. 1C.

도1d를 참조하면, 제 1 포토레지스트 패턴(104)을 제거한 후 제 1 질화막(103) 상부에 산화막(105)을 증착한 후 도1e에 도시된 바와 같이 산화막(105) 상부에 제 2 질화막(106)을 증착한다.Referring to FIG. 1D, after the first photoresist pattern 104 is removed, an oxide film 105 is deposited on the first nitride film 103, and then, as illustrated in FIG. 1E, a second nitride film ( 106).

도1f를 참조하면, 전면 식각을 통해 스페이서(103')를 형성한 다음, 도1g에 도시된 바와 같이 제 2 포토레지스트 패턴(107)을 형성한다.Referring to FIG. 1F, a spacer 103 ′ is formed through front surface etching, and then a second photoresist pattern 107 is formed as shown in FIG. 1G.

도1h를 참조하면, 제 2 포토레지스트(107)를 마스크로 식각 공정을 진행하여 콘택(A)을 형성한 후 도1i에 도시된 바와 같이 콘택(A) 내부에 도프트 폴리실리콘(108)과 텅스텐(109) 및 하드 마스크용 질화막(110)을 증착한다.Referring to FIG. 1H, the second photoresist 107 may be etched using a mask to form a contact A, and then the doped polysilicon 108 may be formed inside the contact A as shown in FIG. 1I. Tungsten 109 and nitride film 110 for hard mask are deposited.

도1j를 참조하면, 제 3 포토레지스트 패턴(111)을 형성한 후 식각 공정을 통해 게이트 스페이서(106')를 형성하여 게이트(B)를 형성한 후 도1k에 도시된 바와 같이 이온 주입 공정을 통해 소오스/드레인(112)을 형성한다.Referring to FIG. 1J, after the third photoresist pattern 111 is formed, a gate spacer 106 ′ is formed through an etching process to form a gate B, and an ion implantation process is performed as shown in FIG. 1K. Source / drain 112 is formed through.

상기한 바와 같이 본 발명은 리버스 게이트를 적용하여 질화막을 금속 장벽층으로 사용하여 메탈 게이트의 산화를 방지함으로써 반도체 소자의 수율을 향상시킬 수 있는 이점이 있다.As described above, the present invention has an advantage of improving the yield of a semiconductor device by applying a reverse gate to prevent oxidation of the metal gate by using a nitride film as the metal barrier layer.

Claims (1)

웰이 형성된 기판 상에 산화 공정을 실시하여 게이트 산화막을 형성하는 단계와,Performing a oxidation process on the well-formed substrate to form a gate oxide film; 상기 게이트 산화막이 형성된 결과물 상에 HDP 산화막을 형성한 다음, 게이트 산화막 상부에 제 1 질화막을 증착하는 단계와,Forming an HDP oxide film on the resultant product on which the gate oxide film is formed, and then depositing a first nitride film on the gate oxide film; 상기 제 1 질화막 상부에 1 포토레지스트 패턴을 형성한 제 1 질화막을 패터닝하는 단계와,Patterning a first nitride film having a first photoresist pattern formed on the first nitride film; 상기 제 1 포토레지스트 패턴을 제거한 후 제 1 질화막 상부에 산화막을 증착하는 단계와,Removing an oxide layer on the first nitride layer after removing the first photoresist pattern; 상기 산화막 상부에 제 2 질화막을 증착하는 단계와,Depositing a second nitride film on the oxide film; 상기 제 2 질화막이 증착된 결과물에 전면 식각을 통해 스페이서를 형성한 다음 제 2 포토레지스트 패턴을 형성하는 단계와,Forming a spacer on the resultant in which the second nitride film is deposited by etching the entire surface, and then forming a second photoresist pattern; 상기 제 2 포토레지스트를 마스크로 식각 공정을 진행하여 콘택을 형성하는 단계와,Forming a contact by performing an etching process using the second photoresist as a mask; 상기 콘택 내부에 도프트 폴리실리콘과 텅스텐 및 하드 마스크용 질화막을 증착하는 단계와,Depositing a doped polysilicon, a nitride film for tungsten and a hard mask inside the contact; 상기 결과물 상에 제 3 포토레지스트 패턴을 형성한 후 식각 공정을 통해 게이트 스페이서를 형성하여 게이트를 형성한 후 이온 주입 공정을 통해 소오스/드레인을 형성하는 단계를After forming a third photoresist pattern on the resultant to form a gate spacer through an etching process to form a gate and then to form a source / drain through an ion implantation process 포함하는 것을 특징으로 하는 디램 소자의 제조 방법.Method of manufacturing a DRAM device comprising a.
KR1020020041805A 2002-07-16 2002-07-16 Method for fabrication of dram device KR100861357B1 (en)

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KR100338104B1 (en) * 1999-06-30 2002-05-24 박종섭 Method of manufacturing a semiconductor device
KR100378183B1 (en) * 2000-09-18 2003-03-29 삼성전자주식회사 Semiconductor memory device and method for manufacturing the same
KR100384774B1 (en) * 2000-11-16 2003-05-22 주식회사 하이닉스반도체 Method for manufacturing gate in semiconductor device
KR20020058512A (en) * 2000-12-30 2002-07-12 박종섭 Method for fabricating semiconductor device

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