KR20040003980A - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

PURPOSE: A method for manufacturing a cylindrical capacitor of a semiconductor device is provided to be capable of improving reliability and reducing manufacturing costs. CONSTITUTION: A sacrificial layer(24) for capacitors is formed on a substrate(20) by gradually reducing a source power and a source gas. Capacitor holes are formed by selectively etching the sacrificial layer(24). The capacitor holes are wet-cleaned so as to have vertical profile. A lower electrode(28) is then formed by filling a conductive layer in the capacitor holes. After the sacrificial layer is removed, a dielectric film and an upper electrode are sequentially formed on the lower electrode.

Description

Method for fabricating capacitor in semiconductor device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor manufacturing technology, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of the electrode in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.

In addition, the method of reducing the thickness of the dielectric thin film in order to minimize the distance between electrodes (d) also faces the limitation due to the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.

Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O ₃ (hereinafter referred to as PLZT), SrBi2Ta2O ₉ (hereinafter referred to as SBT), Bi Ferroelectric materials such as _4-x La _x Ti ₃ O ₁₂ (hereinafter referred to as BLT) are applied as the dielectric thin film material.

In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.

In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO ₂ , IrO _2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.

1A to 1C are cross-sectional views illustrating a method of manufacturing a cylindrical capacitor according to the prior art.

First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. A contact plug 13 is formed by filling the contact hole with a conductive material. Subsequently, the sacrificial layer 14 for forming the capacitor is formed as large as the capacitor is to be formed.

Subsequently, as shown in FIG. 1B, the capacitor formation sacrificial film 14 in the region where the capacitor is to be formed is selectively removed to form the capacitor hole 15. Here, the capacitor forming sacrificial film 14 serves as a die in a process of forming a subsequent lower electrode.

Profile management is very important for the process of forming subsequent lower electrodes. However, since the capacitor hole for forming such a storage electrode has a very long and narrow shape, it is fundamentally impossible to manage the profile vertically, which is illustrated in FIG. 1B.

Considering the dielectric constant of Ta ₂ O ₅ film, which is the most commonly used dielectric thin film in the next-generation semiconductor manufacturing process that requires ultra-fine processing technology with 0.1 micrometer line width, it is currently used to secure the required storage capacity. It should be at least 20000Å in height.

Therefore, as the capacitor hole is etched, the linearity of ions in the hole decreases, so that an inclined surface is inevitably shown at the lower end of the capacitor hole. When the lower end of the capacitor hole is inclined, the lower electrode is formed as shown in FIG. 1C. When the lower electrode is formed, the capacity of the storage electrode is reduced and there is a risk of falling because the bottom area of the lower electrode is small, thereby reducing process reliability of the semiconductor memory device.

It is an object of the present invention to provide a method for producing a cylindrical capacitor which is more stable and more advantageous for integration.

1A to 1C are cross-sectional views showing a method of manufacturing a cylindrical capacitor according to the prior art.

2A to 2E are cross-sectional views illustrating a method of manufacturing a semiconductor capacitor according to a preferred embodiment of the present invention.

3A to 3C are diagrams showing experimental data on an etching selectivity of an insulating film according to process conditions according to the present invention.

<Description of the symbols for the main parts of the drawings>

20: substrate

21: active area

22: interlayer insulating film

23: Contact Plug

24: sacrificial film for capacitor formation

25: polysilicon film for hard mask

26: photosensitive film pattern

27: capacitor hole

28: lower electrode

The present invention for achieving the above object comprises the steps of forming a sacrificial film for forming a capacitor to a height to form a capacitor while gradually reducing the source power and source gas on the substrate; Selectively removing the capacitor forming sacrificial film in the region where the capacitor is to be formed by using a dry etching process to form a capacitor hole; Wet cleaning the inside of the capacitor hole such that the lower end of the capacitor hole has a vertical profile; Forming a lower electrode in the capacitor hole; Removing the sacrificial layer for forming the capacitor; And forming a dielectric thin film and an upper electrode on the lower electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

2a to 2e is a view showing a cylindrical capacitor manufacturing method according to a preferred embodiment of the present invention.

First, as shown in FIG. 2A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. A contact plug 23 is formed by filling a contact hole with a conductive snow material. The interlayer insulating layer 22 is formed by depositing a SiO ₂ film at 2000 kPa to 10000 kPa, forming a contact hole using a photolithography process and an anisotropic etching method, and filling the contact hole with a conductive material to form a contact plug 23.

Subsequently, the capacitor formation sacrificial film 24 is formed using the SiH 4 as the source gas as high as the capacitor is formed. In the subsequent process, the capacitor forming sacrificial film 24 is used as a formwork for the capacitor lower electrode.

At this time, the capacitor forming sacrificial film 24 to be used as the electrode of the lower electrode is a PSG (Phospho-Silicate Glass) film, BPSG (Boro-Phospho-Silicate Glass) film, BSG (Boro-Silicate Glass) film, PETEOS film ( Plasma enhanced Tetraethylorthosilicate) is used to adjust the flow rate or ratio of the Si source and the O ₂ source, or to adjust the power or temperature during deposition to form different etching ratios depending on the height. That is, the lower portion of the capacitor-forming sacrificial layer 24 is formed by depositing an oxide film having a high etching rate, and the upper portion is formed with a slow etching rate.

In the case of forming the capacitor formation sacrificial film using plasma equipment, the etching rate may be changed according to the height of the capacitor formation sacrificial film deposited by various methods such as controlling source power and bias power.

3A to 3B show experimental data on the wet etching selectivity of the sacrificial layer for forming a capacitor according to the change of the source power, the deposition gas, and the temperature according to the present invention.

FIG. 3A is a diagram showing a change in etching selectivity of a silicon oxide film with respect to a change in source power when the silicon oxide film is used as a capacitor forming sacrificial film. When the etching selectivity of the thermal silicon oxide (thrmal oxide) is 1, it can be seen that the etching selectivity when the power is 300W, 500W, 700W respectively increases to 2.8, 3, and 5.

FIG. 3B is a graph showing the change in etching selectivity of the silicon oxide film according to the flow amount of the source gas during deposition of the silicon oxide film. When the etch selectivity of the thermal silicon oxide is 1, the etch selectivity of the source gas flow at 50 sccm, 75 sccm, 100 sccm, and 150 sccm is about 3, about 3.5, about 4.8, and about 6, respectively. It can be seen that the increase.

FIG. 3C is a graph showing a change in etching selectivity of a silicon oxide film according to deposition temperature during deposition of the silicon oxide film. Etch selectivity is shown when the source gas is 60sccm, 75sccm, 100sccm when the deposition temperature is 400 and 550 ° C, respectively.

Therefore, when the bottom and top of the sacrificial film for capacitor formation are deposited, an insulating film having a different etching selectivity for each height may be deposited by adjusting temperature, source flow amount, or power.

In addition, in the case of using the PETEOS film, it is not easy to control the temperature in the deposition process, thereby controlling the etch rate according to the height of the capacitor-forming sacrificial film by adjusting the ratio of source gas or flow amount of gas or power.

Subsequently, a polysilicon film 25 for hard mask is formed and a photosensitive film pattern 26 for selectively removing the capacitor forming sacrificial film 24 is formed.

Subsequently, as shown in FIG. 2B, the polysilicon film 25 for hard mask is patterned using the photosensitive film pattern 26, and the photosensitive film pattern 26 is removed. Subsequently, the patterned hard silicon polysilicon layer 25 is used as an etch barrier to remove the capacitor forming sacrificial layer 24, which is an underlying layer, by a dry etching process so that the contact plug 23 is exposed to form a capacitor hole 25. . At this time, as described above, since the capacitor hole is narrow and has a high height, the lower part of the capacitor maintains a narrower shape than the upper part due to the characteristics of the dry etching process.

Then, as shown in FIG. 2C, the inside of the capacitor hole is subjected to wet cleaning using dilute hydrofluoric acid based solution (HF, BOE), such as 100: 1 or less. At this time, the upper portion of the capacitor hole is hardly etched due to the doping concentration difference of the capacitor forming sacrificial layer 24, and the lower portion is etched according to the doping concentration, so that the profile of the lower portion of the capacitor hole is vertically formed.

Subsequently, as shown in FIG. 3D, the polysilicon film 25 for hard mask is removed and a lower electrode is formed in the capacitor hole. The lower electrode 27 is formed in the capacitor hole 26 with a metal such as ruthenium (Ru) to a thickness of 100 kV to 500 kV. The lower electrode 27 deposits a metal film such as ruthenium by MOCVD (Metal-Organic Chemical Vapor Deposition) and separates it from the lower electrode of the adjacent capacitor by chemical mechanical polishing. In addition, a metal film such as Pt, Ir, and W may be used as the lower electrode.

Subsequently, as shown in FIG. 2E, the sacrificial layer 24 for forming the capacitor is removed by a wet etching process using a hydrofluoric acid-based solution.

Subsequently, a dielectric thin film and an upper electrode are formed on the surface of the cylindrical lower electrode 27. Here, the dielectric thin film may use Ta ₂ O ₅ , TiO ₂ , Al ₂ O ₃ , BST, or STO, and a metal film such as Ru, Pt, Ir, TiN, or W may be used as the upper electrode.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

When the capacitor is formed according to the present invention, the micropattern of the ultra-high integrated device can be applied to the current process by increasing the reliability of forming the lower electrode, thereby improving the reliability and cost of the semiconductor device manufacturing process.

Claims (6)

Forming a capacitor forming sacrificial layer on the substrate to a level at which the capacitor is formed while gradually reducing the source power and the source gas; Selectively removing the capacitor forming sacrificial film in the region where the capacitor is to be formed by using a dry etching process to form a capacitor hole; Wet cleaning the inside of the capacitor hole such that the lower end of the capacitor hole has a vertical profile; Forming a lower electrode in the capacitor hole; Removing the sacrificial layer for forming the capacitor; And Forming a dielectric thin film and an upper electrode on the lower electrode Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, The capacitor forming sacrificial film is initially deposited at a low temperature gradually changing the process conditions, the capacitor manufacturing method of a semiconductor device. The method of claim 1, The capacitor forming sacrificial film is a semiconductor capacitor manufacturing method, characterized in that one selected from BPSG film, BSP film, PSG film, PETEOS film. The method of claim 1, The source power is a semiconductor capacitor manufacturing method, characterized in that to gradually reduce to 300W in the 700W range. The method of claim 1, The source gas is a semiconductor capacitor manufacturing method, characterized in that to deposit the sacrificial film for forming the capacitor while gradually reducing SiH ₄ from 150sccm to 50sccm. The method of claim 2, The temperature is gradually reduced from 550 ℃ to 400 ℃ semiconductor capacitor manufacturing method characterized in that for depositing the sacrificial film for forming the capacitor.