KR100801306B1 - Method for fabricating capacitor in semiconductor device - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a method of manufacturing a capacitor having improved process reliability in a highly integrated semiconductor device. To this end, the present invention provides a method of forming a capacitor insulating layer on a substrate. Doing; Forming a hard mask pattern inclined in a trapezoid shape on the capacitor insulating film; Forming a capacitor hole by using the hard mask pattern as an etch barrier to remove the capacitor insulating layer in the region where the capacitor is to be formed; Forming a lower electrode in the capacitor hole; And forming a dielectric thin film and an upper electrode on the lower electrode.

 Semiconductor, Capacitor, Ferroelectric, High Dielectric, Hard Mask.

Description

Method for fabricating capacitor in semiconductor device             

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

2A and 2B are electron micrographs showing a cross section of a capacitor of a semiconductor device manufactured by the prior art.

3A to 3D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device in accordance with a preferred embodiment of the present invention.

4A and 4B are electron micrographs showing a cross section of a capacitor manufactured according to the present invention.

* Description of the symbols for the main parts of the drawings *

20: substrate

21: active area

22: interlayer insulating film

23: Contact Plug                 

24: capacitor insulating film

25: polysilicon film for hard mask

26: photosensitive film pattern

27: capacitor hole

28: antireflection film

The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a capacitor of a semiconductor device.

As the degree of integration of semiconductor devices, in particular DRAM (Dynamic Random Access Memory) semiconductor memories, increases, the area of memory cells, which are basic units for information storage, is rapidly being reduced.

Such a reduction in the memory cell area is accompanied by a reduction in the area of the cell capacitor, thereby lowering the sensing margin and the sensing speed, and causes a problem that the durability against soft errors caused by α-particles is degraded. Accordingly, there is a need for a method capable of securing sufficient capacitance in a limited cell area.

The capacitance C of the capacitor is defined as in Equation 1 below.

C = ε · As / d

Is the dielectric constant, As is the effective surface area of the electrode, and d is the distance between the electrodes.

Therefore, in order to increase the capacitance of the capacitor, it is necessary to increase the surface area of the electrode, reduce the thickness of the dielectric thin film, or increase the dielectric constant.

Among these, the first method of increasing the surface area of the electrode has been considered. Capacitors of three-dimensional structures, such as concave structures, cylinder structures, multilayer fin structures, and the like, are all proposed to increase the effective surface area of electrodes in a limited layout area. However, this method has a limitation in increasing the effective surface area of the electrode as the semiconductor device is very high integration.

In addition, the method of reducing the thickness of the dielectric thin film to minimize the distance between the electrodes (d) also faces the limitation because of the problem that the leakage current increases as the thickness of the dielectric thin film is reduced.

Therefore, in recent years, research and development have been focused on securing capacitance of a capacitor mainly by increasing the dielectric constant of a dielectric thin film. Traditionally, so-called NO (Nitride-Oxide) capacitors using silicon oxide or silicon nitride as the dielectric thin film have become mainstream, but recently, Ta ₂ O ₅ , (Ba, Sr) TiO ₃ (hereinafter referred to as BST) High dielectric materials such as (Pb, Zr) TiO ₃ (hereinafter referred to as PZT), (Pb, La) (Zr, Ti) O ₃ (hereinafter referred to as PLZT), SrBi2Ta2O ₉ (hereinafter referred to as SBT), Bi Ferroelectric materials such as _4-x La _x Ti ₃ O ₁₂ (hereinafter referred to as BLT) are applied as the dielectric thin film material.

In the manufacture of high dielectric capacitors or ferroelectric capacitors using such high dielectric materials or ferroelectric materials as dielectric thin film materials, proper control of dielectric surrounding materials and processes must be accompanied to realize dielectric properties specific to the high dielectric materials or ferroelectric materials. do.

In general, a noble metal or a compound thereof, such as Pt, Ir, Ru, RuO ₂ , IrO _2, or the like is used as the upper and lower electrode materials of the high dielectric capacitor and the ferroelectric capacitor.

In order to maintain a constant capacitance in a limited area, a capacitor having a concave structure is most widely used.In order to realize a highly integrated device, the height of the concave hole is increased and the width becomes narrower. There is a lot of difficulty in forming the hole stably.

1A to 1D are cross-sectional views illustrating a method of manufacturing a capacitor of a semiconductor device according to the prior art.

First, as shown in FIG. 1A, the interlayer insulating film 12 is formed on the semiconductor substrate 10 on which the active region 11 is formed, and then penetrates the interlayer insulating film 12 to form an active region ( A contact hole connected to 11) is formed. Subsequently, the contact hole is filled with a conductive material to form the contact plug 13, and the capacitor insulating layer 14 is formed to have a size on which the capacitor is formed.                         

Subsequently, a polysilicon film 15 for hard mask is formed, and a photosensitive film pattern 16 for a capacitor hole in which a concave type capacitor is to be formed is formed thereon.

Subsequently, as shown in FIG. 1B, the polysilicon film 15 for hard mask is selectively removed and patterned using the photosensitive film pattern 16.

Subsequently, as shown in FIG. 1C, the capacitor insulating layer 14 is removed using the patterned polymask polysilicon layer 15 as an etch barrier to form the capacitor hole 16.

In the ultra-fine processing technology with the line width of 0.12㎛ or less, the height of the capacitor hole should be more than 20000 위해서는 in order to secure the necessary storage capacity considering the dielectric constant of Ta2O5, which is mainly used as the dielectric thin film. Since the photoresist pattern used previously is not used as an etching barrier, it is impossible to form such a capacitor hole. Thus, a polysilicon film is formed as a hard mask pattern and used as an etching barrier to form a capacitor hole.

As the capacitor hole in which the capacitor is formed becomes narrower and longer in shape, the profile is not vertically formed and the deformation is caused. One of the capacitor holes is formed in a state where the capacitor hole is thinner than the upper portion. This is illustrated in 'A' of FIG. 1C.

When the capacitor hole is deformed in detail, the plasma gas accelerated by the electric field is changed from the vertical direction to the oblique direction by the collision with neutral atoms or molecules to etch the capacitor hole in an oblique direction.

In addition, when the inclined portion of the photoresist pattern or the hard mask pattern is inclined, the accelerated ions are scattered at the edges of the inclined photoresist pattern or the hard mask pattern and penetrate at an angle into the capacitor hole. When the electrons are charged to the surface of the capacitor hole adjacent to the photoresist pattern or the hard mask pattern, the sidewalls of the capacitor hole are etched by the positive attraction of the cation, thereby deforming the inside of the capacitor hole.

For this reason, voids are generated when the upper and lower electrodes and the dielectric thin film are formed inside the deformed capacitor hole 16, and the figure is shown in FIG. 1D.

Figure 2a is an electron micrograph showing a cross-section patterned polysilicon film for hard mask using a photoresist pattern to form a capacitor hole in the actual process, Figure 2b is a cross-sectional view showing a capacitor insulating film removed using a polysilicon film for hard mask Electron micrograph.

As described above, due to the deformation of the capacitor hole, it is impossible to stably manufacture the capacitor with voids generated during the formation of the subsequent upper and lower electrodes, thereby reducing the reliability of the operation of the semiconductor device.

An object of the present invention is to provide a method of manufacturing a capacitor having improved process reliability in a highly integrated semiconductor device.

In order to achieve the above object, the present invention provides a method for forming an interlayer insulating film on a substrate, the method comprising: forming a capacitor insulating film on the interlayer insulating film to a height at which a capacitor is formed; Forming a hard mask pattern inclined in a trapezoid shape on the capacitor insulating film; Forming a capacitor hole by using the hard mask pattern as an etch barrier to remove the capacitor insulating layer in the region where the capacitor is to be formed; Forming a lower electrode in the capacitor hole; And forming a dielectric thin film and an upper electrode on the lower electrode.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

3A to 3D are views showing a capacitor manufacturing method of a semiconductor device according to a preferred embodiment of the present invention.

First, as shown in FIG. 3A, the interlayer insulating film 22 is formed on the semiconductor substrate 20 on which the active region 21 is formed, and then penetrates the interlayer insulating film 22 to form the active region of the semiconductor substrate 20 ( A contact hole connected to 21 is formed. Subsequently, the contact hole 23 is filled with a conductive material to form the contact plug 23, and the capacitor insulating layer 24 is formed to have a height at which the capacitor is formed. The capacitor insulating film 24 may be an oxide film such as USG (Undoped-Silicate Glass), PSG (Phospho-Silicate Glass), BPSG (Boro-Phospho-Silicate Glass), or the like.                     

Subsequently, a polysilicon film 25 for hard mask is formed to a thickness of 500 to 5000 kPa, and an antireflective film 28 for antireflection during the photolithography process is formed thereon.

The hard mask film may be an oxide film series, a silicon nitride (SixNy) film, or a metal series such as tungsten film, tungsten nitride film, titanium film, titanium nitride film, or tungsten silicide film.

Subsequently, a photoresist pattern 26 for forming a capacitor hole for a concave capacitor is formed on the anti-reflection film 28.

Subsequently, as shown in FIG. 3B, the photoresist layer pattern 26 is used as an etching barrier, and the polysilicon layer 25 for hard mask is etched to form a slope of about 50 to 89 degrees to form a trapezoidal shape for the hard mask. The polysilicon film 25 is formed. At this time, in order to etch the polysilicon film 25 for the hard mask to form a slope, an etching gas such as Cl ₂ , HBr, SF ₆ , NF _3, or CxFy is used as the main etchant, and the O ₂ , N ₂ , Ar, He or CxHyFz or other gas is added to the process or a plasma stabilizing gas is used.

In addition, in order to etch the mask for the hard mask inclinedly, the chamber pressure during the etching process is in the range of 1mT ~ 100mT, the source source is adjusted to 100 ~ 2000Watt, the bias power is adjusted in the range of 1 ~ 2000Watt, Is adjusted to 0 ~ 300 ℃, the wafer lower electrode temperature is adjusted to -20 ~ 300 ℃, the flow rate of the etching gas is adjusted to 0 ~ 500sccm to proceed with the etching process.

In addition, the above-described process may be performed by inclining the photosensitive film pattern itself, or the above process may be performed by stacking the photosensitive film and the hard mask film in an inclined form.

Subsequently, as shown in FIG. 3C, the photoresist pattern 27 and the anti-reflection film 28 are removed, and the capacitor insulating layer 24 is etched using the hard mask polysilicon layer 25 patterned in an etched state as an etch barrier. Thus, the capacitor hole 27 is formed. When the capacitor insulating layer 25 is etched by using a trapezoidal hard mask, as the etching proceeds, the hard mask layer gradually widens so that the ions scattered by the inclined hard mask layer collide with the inside of the capacitor hole. As the position is gradually lowered, the collision does not occur only in a specific region, so that the upper end of the capacitor hole may be etched at the same time as the lower end to form a capacitor hole having a vertical profile.

Subsequently, as shown in FIG. 3D, a lower electrode 29 is formed in the capacitor hole 27, and a dielectric thin film and an upper electrode are formed thereon to complete the capacitor.

According to the present invention, it is possible to obtain a capacitor hole having a profile to be vertical by modifying only the hard mask etching process while applying the conventional etching process as it is, thereby forming a stable high density capacitor without additional cost.

The present invention described above can also be applied to self-aligned contact etching, line / space forming process, and the like.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The present invention can stably form the capacitor of the highly integrated semiconductor device without additional costs by optimizing only the hard mask etching process while applying the conventional etching process as it is. In addition, it is possible to maximize development stability and yield by minimizing development delays or device reliability problems that may occur due to the introduction of new materials or new processes.

Claims (6)

Forming an interlayer insulating film on the substrate: Forming a capacitor insulating film on the interlayer insulating film to a height at which the capacitor is formed; Forming a hard mask pattern inclined in a trapezoid shape on the capacitor insulating film; Forming a capacitor hole by using the hard mask pattern as an etch barrier to remove the capacitor insulating layer in the region where the capacitor is to be formed; Forming a lower electrode in the capacitor hole; And Forming a dielectric thin film and an upper electrode on the lower electrode Capacitor manufacturing method of a semiconductor device comprising a. The method of claim 1, Forming the hard mask pattern is Forming a hard mask film on the capacitor insulating film; Forming a photoresist pattern on the hardmask polysilicon layer for forming the capacitor hole; And And selectively removing the hard mask film using the photosensitive film pattern to form the hard mask pattern. The method of claim 2, The hard mask film is A method for manufacturing a capacitor of a semiconductor device, characterized in that the polysilicon film, silicon oxide film, silicon nitride film, tungsten film, tungsten nitride film, titanium film, titanium nitride film or tungsten silicide film. The method of claim 1, And forming a photosensitive film pattern having an inclined trapezoid shape on an inclined hard mask pattern in the trapezoidal shape. The method of claim 1, In order to etch the hard mask film, an etching gas such as Cl ₂ , HBr, SF ₆ , NF _3, or CxFy is used as a main etchant to add a gas such as O ₂ , N ₂ , Ar, He, or CxHyFz to proceed the process. A method for manufacturing a capacitor of a semiconductor device, characterized in that. The method of claim 1, In order to etch the hard mask film in an inclined manner, the chamber pressure during the etching process is in the range of 1 mT to 100 mT, the source source is adjusted to 100 to 2000 Watts, and the bias power is adjusted to 1 to 2000 Watts, and the chamber temperature is The method of manufacturing a capacitor of a semiconductor device, characterized in that to adjust to 0 ~ 300 ℃, to adjust the wafer lower electrode temperature to -20 ~ 300 ℃, the etching process by adjusting the flow rate of the etching gas to 0 ~ 500sccm.

Images