KR20040002234A - Method for forming a bit line of semiconductor device - Google Patents

Method for forming a bit line of semiconductor device Download PDF

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Publication number
KR20040002234A
KR20040002234A KR1020020037681A KR20020037681A KR20040002234A KR 20040002234 A KR20040002234 A KR 20040002234A KR 1020020037681 A KR1020020037681 A KR 1020020037681A KR 20020037681 A KR20020037681 A KR 20020037681A KR 20040002234 A KR20040002234 A KR 20040002234A
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South Korea
Prior art keywords
insulating film
forming
interlayer insulating
interlayer dielectric
bit lines
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KR1020020037681A
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Korean (ko)
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우탁균
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주식회사 하이닉스반도체
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Priority to KR1020020037681A priority Critical patent/KR20040002234A/en
Publication of KR20040002234A publication Critical patent/KR20040002234A/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H10B12/0335—Making a connection between the transistor and the capacitor, e.g. plug

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for fabricating a bitline of a semiconductor device is provided to reduce bitline parasitic capacitance and prevent the refresh of a chip from being decreased by forming an air layer in a space between bitline such that the air layer has a dielectric constant smaller than that of a SiO2-based interlayer dielectric. CONSTITUTION: The first interlayer dielectric(33) having a plurality of the first contact holes for the bitline(35) is formed on a substrate. A plurality of mutually isolated bitlines are formed on the first interlayer dielectric, burying the first contact holes, respectively. The first insulation layer having poor step coverage is formed on the resultant structure wherein the first insulation layer is deposited in the upper portion of the space more than in the lower portion of the space to generate a void between the bitlines. The second interlayer dielectric(43) as a planarization layer is formed on the first insulation layer wherein the second interlayer dielectric is formed on the void like a cover. The second interlayer dielectric, the first insulation layer and the first interlayer dielectric are etched to form a storage node contact hole by a photolithography process using a storage node contact mask. The second insulation layer spacer is formed on the inner wall of the storage node contact hole.

Description

반도체 소자의 비트라인 형성 방법{Method for forming a bit line of semiconductor device}Method for forming a bit line of semiconductor device

본 발명은 반도체 소자의 비트라인 형성 방법에 관한 것으로, 특히, 비트라인(Bit line) 사이의 공간에 공기층을 발생시켜 소자의 수율 및 신뢰성을 향상시키는 반도체 소자의 비트라인 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a bit line of a semiconductor device, and more particularly, to a method for forming a bit line of a semiconductor device, by generating an air layer in a space between bit lines to improve yield and reliability of the device.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 비트라인 형성 방법을 도시한 단면도이다.1A to 1C are cross-sectional views illustrating a bit line forming method of a semiconductor device according to the prior art.

도 1a를 참조하면, 트랜지스터를 포함한 하부 구조물(11) 상에 다수개의 비트라인용 콘택홀이 구비된 제 1 층간 절연막(13)을 형성한다.Referring to FIG. 1A, a first interlayer insulating layer 13 having a plurality of bit line contact holes is formed on a lower structure 11 including a transistor.

그리고, 상기 비트라인용 콘택홀을 포함한 제 1 층간 절연막(13) 상에 다결정 실리콘층과 절연막을 순차적으로 형성한다.A polycrystalline silicon layer and an insulating layer are sequentially formed on the first interlayer insulating layer 13 including the bit line contact hole.

이어, 비트라인용 마스크를 사용한 사진식각 공정으로 상기 절연막과 다결정 실리콘층을 식각하여 다수개의 비트라인(15)들을 형성한다. 이때, 상기 각 비트라인(15)은 그 상부에 상기 절연막의 하드 마스크층(17)을 구비하며 상기 비트라인용 콘택홀을 매립한다.Subsequently, a plurality of bit lines 15 are formed by etching the insulating layer and the polycrystalline silicon layer by a photolithography process using a bit line mask. At this time, each of the bit lines 15 includes a hard mask layer 17 of the insulating layer thereon and fills the contact holes for the bit lines.

도 1b를 참조하면, 상기 비트라인(15)들을 포함한 제 1 층간 절연막(13) 상에 SiO2계열의 제 2 층간 절연막(19)을 형성하고, 평탄화 시킨다.Referring to FIG. 1B, the SiO 2 series second interlayer insulating layer 19 is formed on the first interlayer insulating layer 13 including the bit lines 15 and planarized.

도 1c를 참조하면, 캐패시터의 저장전극용 콘택 마스크를 사용한 사진식각 공정으로 상기 제 2 층간 절연막(19)을 식각하고, 상기 제 1 층간 절연막(13)을 식각하여 저장전극용 콘택홀(21)을 형성한다.Referring to FIG. 1C, the second interlayer insulating layer 19 is etched by using a photolithography process using a storage electrode contact mask, and the first interlayer insulating layer 13 is etched to store the contact hole 21 for the storage electrode. To form.

그 후, 후속 공정으로 일반적인 캐패시터 형성 공정을 진행하여 상기 저장전극용 콘택홀(21)을 통하여 상기 하부 구조물(11)과 전기적으로 연결되는 캐패시터를 형성한다.Thereafter, a general capacitor forming process is performed in a subsequent process to form a capacitor electrically connected to the lower structure 11 through the storage hole contact hole 21.

종래 반도체 소자의 비트라인 형성 방법은 DRAM 셀 형성 공정에 있어서, 비트라인은 신호를 전달하는 라인으로 전류가 흐르게 되어 상기 비트라인 상호간에 기생 캐패시턴스(Capacitance)가 발생됨으로써 칩(Chip)의 리프레쉬(Refresh)가 감소되는 문제점이 있었다.In the conventional method of forming a bit line of a semiconductor device, in a DRAM cell forming process, a bit line causes a current to flow through a line for transmitting a signal, thereby generating parasitic capacitance between the bit lines, thereby refreshing the chip. ) Was reduced.

본 발명은 상기의 문제점을 해결하기 위해 안출한 것으로 비트라인 사이의 공간에 공기층을 발생시킴으로써, 비트라인 기생 캐패시턴스를 감소시키는 반도체 소자의 비트라인 형성 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a bit line of a semiconductor device which reduces bit line parasitic capacitance by generating an air layer in a space between bit lines.

도 1a 내지 도 1c는 종래 기술에 따른 반도체 소자의 비트라인 형성 방법을 도시한 단면도.1A to 1C are cross-sectional views illustrating a bit line forming method of a semiconductor device according to the prior art.

도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 비트라인 형성 방법을 도시한 단면도.2A through 2E are cross-sectional views illustrating a method of forming a bit line of a semiconductor device in accordance with an embodiment of the present invention.

< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>

11,31 : 하부 구조물13,33 : 제 1 층간 절연막11,31: Substructure 13,33: First interlayer insulating film

15,35 : 비트라인17,37 : 하드 마스크층15,35 bit line 17,37 hard mask layer

19,43 : 제 2 층간 절연막21,47 : 저장전극용 콘택홀19,43: Second interlayer insulating film 21,47: Contact hole for storage electrode

39 : 제 2 절연막41 : 보이드39: second insulating film 41: void

45 : 공기층49 : 제 3 절연막 스페이서45: air layer 49: third insulating film spacer

이상의 목적을 달성하기 위한 본 발명은,The present invention for achieving the above object,

기판 상에 다수개의 비트라인용 제 1 콘택홀이 구비된 제 1 층간 절연막을 형성하는 단계와,Forming a first interlayer insulating film having a plurality of first contact holes for bit lines on the substrate;

상기 제 1 층간 절연막 상에 상기 각각의 제 1 콘택홀을 매립하면서 서로 격리된 다수개의 비트라인들을 형성하는 단계와,Forming a plurality of bit lines isolated from each other by filling the first contact holes on the first interlayer insulating layer;

상기 비트라인들을 포함한 전면에 스텝 커버리지가 불량한 제 1 절연막을 형성하되, 상기 비트라인 사이의 공간에서 하부보다 상부에 상기 제 1 절연막의 증착량이 많아 상기 비트라인 사이에 보이드(Void)를 발생시키는 단계와,Forming a first insulating film having poor step coverage on the entire surface including the bit lines, and generating voids between the bit lines due to a large amount of deposition of the first insulating film above the lower part in the space between the bit lines; Wow,

상기 제 1 절연막 상에 평탄층인 제 2 층간 절연막을 형성하되, 뚜껑과 같이 상기 보이드 상부에 상기 제 2 층간 절연막을 형성하는 단계와,Forming a second interlayer insulating film that is a flat layer on the first insulating film, and forming the second interlayer insulating film on the void such as a lid;

저장전극 콘택용 마스크를 사용한 사진식각 공정으로 상기 제 2 층간 절연막, 제 1 절연막 및 제 1 층간 절연막을 식각하여 저장전극용 콘택홀을 형성하는 단계와,Etching the second interlayer insulating film, the first insulating film, and the first interlayer insulating film by a photolithography process using a storage electrode contact mask to form a contact hole for a storage electrode;

상기 저장전극용 콘택홀 내벽에 제 2 절연막 스페이서를 형성하는 단계를 포함한 반도체 소자의 비트라인 형성 방법을 제공하는 것과,Providing a method of forming a bit line of a semiconductor device, the method including forming a second insulating layer spacer on an inner wall of the contact hole for the storage electrode;

상기 제 1 절연막을 100 ∼ 3000Å의 두께로 형성하는 것과,Forming the first insulating film in a thickness of 100 to 3000 kPa,

상기 제 2 절연막을 100 ∼ 3000Å의 두께로 형성하는 것을 특징으로 한다.The second insulating film is formed to a thickness of 100 to 3000 kPa.

본 발명의 원리는 DRAM 셀에 있어서, 비트라인 사이에 발생되는 기생 캐패시턴스는 비트라인 사이의 절연막의 유전율과 비례하기 때문에 비트라인 사이를 절연시키기 위하여 종래에 형성했던 SiO2계열의 층간 절연막보다 유전율이 작은 공기층을 비트라인 사이의 공간에 발생시킴으로써, 비트라인 기생 캐패시턴스를 감소시켜 리프레쉬의 감소를 방지하기 위한 것이다.The principle of the present invention is that in the DRAM cell, the parasitic capacitance generated between the bit lines is proportional to the dielectric constant of the insulating film between the bit lines, so that the dielectric constant is higher than that of the SiO 2 series interlayer insulating film which is conventionally formed to insulate the bit lines. By generating a small air layer in the space between the bit lines, the bit line parasitic capacitance is reduced to prevent a decrease in refresh.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하면 다음과 같다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2e는 본 발명의 실시 예에 따른 반도체 소자의 비트라인 형성 방법을 도시한 단면도로서,“Ⅰ”는 비트라인과 수직하게 절단한 단면을 도시한 것이고,“Ⅱ”는 비트라인과 평행하게 비트라인 사이의 공간을 절단한 단면을 도시한 것이다.2A to 2E are cross-sectional views illustrating a method of forming a bit line of a semiconductor device according to an exemplary embodiment of the present invention, in which “I” illustrates a cross section cut perpendicular to the bit line, and “II” represents a bit line. The cross section which cuts the space between bit lines in parallel is shown.

도 2a를 참조하면, 트랜지스터를 포함한 하부 구조물(31) 상에 다수개의 비트라인용 콘택홀이 구비된 제 1 층간 절연막(33)을 형성한다.Referring to FIG. 2A, a first interlayer insulating layer 33 having a plurality of bit line contact holes is formed on a lower structure 31 including a transistor.

그리고, 상기 비트라인용 콘택홀을 포함한 제 1 층간 절연막(33) 상에 제 1다결정 실리콘층과 제 1 절연막을 순차적으로 형성한다.The first polycrystalline silicon layer and the first insulating layer are sequentially formed on the first interlayer insulating layer 33 including the bit line contact hole.

이어, 비트라인용 마스크를 사용한 사진식각 공정으로 상기 제 1 절연막과 제 1 다결정 실리콘층을 식각하여 다수개의 비트라인(35)들을 형성한다. 이때, 상기 각 비트라인(35)은 그 상부에 상기 제 1 절연막의 하드 마스크층(37)을 구비하며 상기 제 1 콘택홀을 매립한다.Subsequently, a plurality of bit lines 35 are formed by etching the first insulating layer and the first polycrystalline silicon layer by a photolithography process using a bit line mask. In this case, each of the bit lines 35 includes a hard mask layer 37 of the first insulating layer thereon and fills the first contact hole.

도 2b를 참조하면, 상기 비트라인(35)들을 포함한 제 1 층간 절연막(33) 상에 스텝 커버리지가 불량한 제 2 절연막(39)을 100 ∼ 3000Å의 두께로 형성한다.Referring to FIG. 2B, a second insulating film 39 having poor step coverage is formed on the first interlayer insulating film 33 including the bit lines 35 to a thickness of 100 to 3000 mW.

이때, 상기 제 2 절연막(39)은 스텝 커버리지가 불량하기 때문에 상기 비트라인(35) 사이의 공간에서 하부보다 상부에 상기 제 2 절연막(39)의 증착량이 많아 상기 비트라인(35) 사이에 보이드(41)를 발생시킨다.In this case, since the second insulating film 39 has poor step coverage, the amount of deposition of the second insulating film 39 is higher than the lower portion in the space between the bit lines 35, thereby voiding between the bit lines 35. (41) is generated.

도 2c를 참조하면, 상기 제 2 절연막(39) 상에 평탄층인 제 2 층간 절연막(43)을 형성한다.Referring to FIG. 2C, a second interlayer insulating film 43 that is a flat layer is formed on the second insulating film 39.

이때, 상기 제 2 층간 절연막(43)의 형성 공정으로 뚜껑과 같이 상기 보이드(41) 상부에 상기 제 2 층간 절연막(43)이 형성되어 공기층(45)을 발생시킨다.In this case, the second interlayer insulating layer 43 is formed on the void 41 like a lid in the process of forming the second interlayer insulating layer 43 to generate the air layer 45.

도 2d를 참조하면, 캐패시터의 저장전극용 콘택 마스크를 사용한 사진식각 공정으로 상기 제 2 층간 절연막(43), 제 2 절연막(39) 및 제 1 층간 절연막(33)을 식각하여 저장전극용 콘택홀(47)을 형성한다.Referring to FIG. 2D, the second interlayer insulating layer 43, the second insulating layer 39, and the first interlayer insulating layer 33 are etched by a photolithography process using a capacitor's storage electrode contact mask. Form 47.

도 2e를 참조하면, 상기 저장전극용 콘택홀(47)을 포함한 제 2 층간 절연막(43) 상에 스텝 커버리지가 불량한 제 3 절연막을 100 ∼ 3000Å의 두께로형성하고, 상기 제 3 절연막을 에치백(Etch-back)하여 상기 저장전극용 콘택홀(47) 내벽에 제 3 절연막 스페이서(Spacer)(49)를 형성한다.Referring to FIG. 2E, a third insulating film having poor step coverage is formed on the second interlayer insulating film 43 including the storage electrode contact hole 47 to a thickness of 100 to 3000 GPa, and the third insulating film is etched back. (Etch-back) to form a third insulating film spacer (49) on the inner wall of the storage electrode contact hole (47).

그 후, 후속 공정으로 일반적인 캐패시터 형성 공정을 진행하여 상기 저장전극용 콘택홀(21)을 통하여 상기 하부 구조물(11)과 전기적으로 연결되는 캐패시터를 형성한다.Thereafter, a general capacitor forming process is performed in a subsequent process to form a capacitor electrically connected to the lower structure 11 through the storage hole contact hole 21.

여기서, 상기 제 2 절연막 스페이서(49)를 형성하지 않고 캐패시터를 형성할 경우, 상기 공기층(45)을 통하여 이웃하는 캐패시터간에 서로 도통되기 때문에 이를 방지하기 위해 상기 제 2 절연막 스페이서(49)를 형성한다.In the case where the capacitor is formed without forming the second insulating layer spacer 49, the second insulating layer spacer 49 is formed to prevent the capacitors from being connected to each other through the air layer 45. .

본 발명의 반도체 소자의 비트라인 형성 방법은 비트라인 사이의 공간에 SiO2계열의 층간 절연막보다 유전율이 작은 공기층을 발생시킴으로써, 비트라인 기생 캐패시턴스를 감소시켜 리프레쉬의 감소를 방지함으로 소자의 수율 및 신뢰성을 향상시키는 효과가 있다.The method of forming a bit line of a semiconductor device of the present invention generates an air layer having a lower dielectric constant than that of a SiO 2 series interlayer insulating film in the space between the bit lines, thereby reducing bit line parasitic capacitance and preventing refresh, thereby improving device yield and reliability. Has the effect of improving.

Claims (3)

기판 상에 다수개의 비트라인용 제 1 콘택홀이 구비된 제 1 층간 절연막을 형성하는 단계와,Forming a first interlayer insulating film having a plurality of first contact holes for bit lines on the substrate; 상기 제 1 층간 절연막 상에 상기 각각의 제 1 콘택홀을 매립하면서 서로 격리된 다수개의 비트라인들을 형성하는 단계와,Forming a plurality of bit lines isolated from each other by filling the first contact holes on the first interlayer insulating layer; 상기 비트라인들을 포함한 전면에 스텝 커버리지가 불량한 제 1 절연막을 형성하되, 상기 비트라인 사이의 공간에서 하부보다 상부에 상기 제 1 절연막의 증착량이 많아 상기 비트라인 사이에 보이드를 발생시키는 단계와,Forming a first insulating film having poor step coverage on the entire surface including the bit lines, and generating voids between the bit lines due to a large amount of deposition of the first insulating film above the lower part in the space between the bit lines; 상기 제 1 절연막 상에 평탄층인 제 2 층간 절연막을 형성하되, 뚜껑과 같이 상기 보이드 상부에 상기 제 2 층간 절연막을 형성하는 단계와,Forming a second interlayer insulating film that is a flat layer on the first insulating film, and forming the second interlayer insulating film on the void such as a lid; 저장전극 콘택용 마스크를 사용한 사진식각 공정으로 상기 제 2 층간 절연막, 제 1 절연막 및 제 1 층간 절연막을 식각하여 저장전극용 콘택홀을 형성하는 단계와,Etching the second interlayer insulating film, the first insulating film, and the first interlayer insulating film by a photolithography process using a storage electrode contact mask to form a contact hole for a storage electrode; 상기 저장전극용 콘택홀 내벽에 제 2 절연막 스페이서를 형성하는 단계를 포함한 반도체 소자의 비트라인 형성 방법.And forming a second insulating film spacer on an inner wall of the contact hole for the storage electrode. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막을 100 ∼ 3000Å의 두께로 형성함을 특징으로 하는 반도체 소자의 비트라인 형성 방법.And forming the first insulating film in a thickness of 100 to 3000 GPa. 제 1 항에 있어서,The method of claim 1, 상기 제 2 절연막을 100 ∼ 3000Å의 두께로 형성함을 특징으로 하는 반도체 소자의 비트라인 형성 방법.And forming the second insulating film in a thickness of 100 to 3000 GPa.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579233B2 (en) 2004-12-31 2009-08-25 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby
US8198189B2 (en) 2009-05-11 2012-06-12 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices including air spacers separating conductive structures and contact plugs
US9178026B2 (en) 2012-08-22 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor devices and methods fabricating same
US9281361B2 (en) 2012-09-21 2016-03-08 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
US9601420B2 (en) 2012-09-06 2017-03-21 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
WO2019133094A1 (en) * 2017-12-29 2019-07-04 Micron Technology, Inc. A construction of integrated circuitry and dram construction

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7579233B2 (en) 2004-12-31 2009-08-25 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby
US8022455B2 (en) 2004-12-31 2011-09-20 Samsung Electronics Co., Ltd. Method of fabricating semiconductor device for reducing parasitic capacitance between bit lines and semiconductor device fabricated thereby
US8198189B2 (en) 2009-05-11 2012-06-12 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices including air spacers separating conductive structures and contact plugs
US8344517B2 (en) 2009-05-11 2013-01-01 Samsung Electronics Co., Ltd. Integrated circuit devices including air spacers separating conductive structures and contact plugs and methods of fabricating the same
US9178026B2 (en) 2012-08-22 2015-11-03 Samsung Electronics Co., Ltd. Semiconductor devices and methods fabricating same
US9601420B2 (en) 2012-09-06 2017-03-21 Samsung Electronics Co., Ltd. Semiconductor device and method of manufacturing the same
US9281361B2 (en) 2012-09-21 2016-03-08 Samsung Electronics Co., Ltd. Semiconductor devices and methods of fabricating the same
WO2019133094A1 (en) * 2017-12-29 2019-07-04 Micron Technology, Inc. A construction of integrated circuitry and dram construction
US10679996B2 (en) 2017-12-29 2020-06-09 Micron Technology, Inc. Construction of integrated circuitry and a DRAM construction

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