KR19990004868A - Semiconductor device manufacturing method - Google Patents

Abstract

The present invention forms a storage node in the cell region with a metal film, and simultaneously forms a metal film pattern on the peripheral circuit portion when the storage node is formed in the cell portion, thereby preventing the occurrence of a step, and the peripheral circuit on the metal film pattern. The metal contacts in the area are contacted to reduce the metal contact depth in the peripheral circuit area.

Description

Semiconductor device manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for facilitating metal contact in a peripheral circuit area in manufacturing a DRAM.

Typically, capacitors are only needed in the cell area in DRAM, so they are formed only in the cell area, which inevitably leads to gaps between cell prison and peripheral circuit areas. In particular, as the degree of integration increases, the height of the capacitor is inevitably increased in order to secure the capacitance necessary for a small area, thereby increasing the step height.

1A and 1B illustrate a DRAM manufacturing process according to the prior art. As shown in the drawing, a transistor structure including a word line 102 is formed on a silicon substrate 101 and a first interlayer insulating film 103 is formed. ) And then forming the bit line 104 and the second interlayer insulating film 105, and then forming the capacitor 106 and the third interlayer insulating film 107. We carry out.

Here, as shown in FIG. 1A, since there is a severe step between the cell region where the capacitor 106 is formed and the peripheral circuit region where the capacitor is not formed, as shown in FIG. 1B, the third interlayer insulating film 107 is formed. A chemical mechanical polishing (CMP) process must be performed for planarization. In this case, the depth of the metal contact 108 is inevitably deepened, thereby providing a cause of metal contact failure. Also, a simple CMP technique has a high capacitor height. In this case, the insulating film on the plate electrode, which is the capacitor upper electrode, is severely uneven, which causes a problem that the plate electrode is exposed. Therefore, more fundamentally, there is a demand for a method of performing a metal contact to the peripheral circuit area while eliminating the step between the cell area and the surrounding area.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a semiconductor device in which a metal contact is preferably made in a peripheral circuit region while overcoming a step between a cell region and a peripheral region.

1A and 1B show a DRAM manufacturing process according to the prior art.

2A to 2I are DRAM manufacturing process diagrams in accordance with one embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

203a: bitline contact plug

203b: Storage node contact plug on the capacitor

205: bit line

210a: storage node metal layer pattern

210b: metal pattern in the peripheral circuit area

214: wiring metal film

A semiconductor device manufacturing method of the present invention for achieving the above object comprises the steps of preparing a wafer on which transistors and bit lines are formed; Forming a first interlayer dielectric layer having a storage node contact portion and a metal contact portion in a peripheral region thereof; And forming a first metal layer on a front surface to fill the opening, and selectively patterning the first metal layer by etching to form a first pattern of a first metal layer for a storage node and a second pattern of a first metal layer for a metal contact. It comprises the step of forming. After the forming of the first pattern of the first metal layer and the second pattern of the first metal layer, forming a conductive film for the dielectric film of the capacitor and the plate electrode of the capacitor on the front surface thereof; Etching the conductive film and the dielectric film for the plate electrode to expose the second pattern of the first metal layer; Forming a second interlayer insulating film on the entire structure; Selectively etching the second interlayer insulating film to expose a surface of the second pattern of the first metal layer; And forming a second metal layer pattern contacted with the first metal layer second pattern.

In addition, the semiconductor device manufacturing method of the present invention comprises the steps of preparing a wafer, the transistor is formed, the bit line contact region and the storage node contact region is opened at the same time; Filling the polysilicon layer in the opening to form a bit line contact plug and a storage node contact plug, respectively; Forming a first insulating layer having surfaces of the bit line contact plug and the storage node contact plug open; Forming a bit line conductive layer pattern formed through the first insulating layer and contacted to the bit line contact plug; Forming a second insulating layer in which the semiconductor substrate for the metal contact of the storage node contact plug and the peripheral region is opened; And forming a first metal layer on a front surface to fill the opening, and selectively patterning the first metal layer by etching to form a first pattern of a first metal layer for a storage node and a second pattern of a first metal layer for a metal contact. Forming the first metal layer first pattern and the first metal layer second pattern; forming a conductive film for the dielectric film of the capacitor and the plate electrode of the capacitor on the front surface thereof; Etching the conductive film and the dielectric film for the plate electrode to expose the second pattern of the first metal layer; Forming a third insulating film on the entire structure; Selectively etching the third insulating layer to expose a surface of the second pattern of the first metal layer; And forming a second metal layer pattern contacting the first metal layer second pattern.

2A to 2I are DRAM manufacturing process diagrams according to an embodiment of the present invention, with reference to this embodiment of the present invention will be described in detail.

First, as shown in FIG. 2A, a transistor including a word line 202 is formed on a silicon substrate 201, and then a bit line contact plug 203a and a storage node contact plug 203b of a capacitor are formed. do. At this time, the bit line contact plug 203a and the storage node contact plug 203b of the capacitor may be simultaneously formed by opening the bit line contact and the storage node contact at the same time and then filling the opening with the polysilicon film. Subsequently, after the first interlayer insulating film 204 is formed, the bit line 205 connected to the bit line contact plug 203a through the first interlayer insulating film 204 is patterned, and then a second interlayer insulating film ( 206). The second interlayer insulating layer 206 is selectively etched to expose the storage node contact plug 203b and the silicon substrate 201 to which metal is to be contacted in the peripheral circuit area, thereby the storage node contact hole 207 and the peripheral circuit. Metal contact holes 208 in the area are simultaneously formed.

Subsequently, as shown in FIG. 2B, the metal film 210 is formed on the entire surface of the capacitor instead of the polysilicon film that has been conventionally used as a storage node material of the capacitor. Before forming the metal layer 210, a barrier metal 209 such as Ti / TiN may be formed to increase the spiking and adhesion with the lower silicon layer. The storage node contact plug 203b does not directly connect the storage node metal film 210 and the silicon substrate (which is actually an n-junction layer) to prevent an increase in junction leakage, which is particularly important in capacitors.

Subsequently, as shown in FIG. 2C, the storage node metal film pattern 210a is formed by a mask and an etching process, and the metal pattern 210b serving as a metal contact plug or internal connection is also formed in the metal contact area of the peripheral circuit area. Form. That is, unlike the conventional method of forming the storage node pattern only in the cell portion, the pattern is formed in the peripheral circuit portion. The metal pattern 210b formed in the peripheral circuit area has an advantage of lowering the depth of metal contact in subsequent processes.

Subsequently, as shown in FIG. 2D, the capacitor dielectric film 211 is formed on the entire surface, and as shown in FIG. 2E, a polysilicon film or a metal film is formed as the conductive film 212 for the plate electrode of the capacitor.

Subsequently, as illustrated in FIG. 2F, a plate electrode mask and an etching process are performed to etch the plate electrode conductive film 212 and the dielectric film 9211 in the peripheral circuit region to expose the metal pattern 210b. As shown in FIG. 2G, the planarized third interlayer insulating film 213 is formed on the entire structure. As shown in the drawing, the step difference due to the capacitors 210a, 211, and 212 in the cell region does not occur. Do not.

Subsequently, as shown in FIG. 2H, the third interlayer insulating film 213 is selectively etched to expose the metal pattern 210b of the peripheral circuit area, and then as shown in FIG. 2I, the wiring metal film 214. Is deposited and patterned. In this case, since the wiring metal film pattern 215 that contacts the peripheral circuit region is contacted on the plug-in metal pattern 210b, the contact depth is not deep, so that the step coverage may be good. Therefore, since the contact depth is not deep, the advantage that the wiring metal can be used as Al instead of W can greatly reduce the metal resistance.

As described above, the present invention facilitates the progress of the metallization process, which is a subsequent process, by essentially solving the step difference between the cell region and the peripheral circuit region by the capacitor, in the manufacture of the highly integrated DRAM, and at the same time as the capacitor formation process. By forming a metal pattern to serve as a contact plug, there is a very big advantage of using a metal wiring layer further. In addition, in the capacitor, it is preferable to increase the height of the capacitor to increase the capacitance, but the present invention can easily increase the height of the capacitor because the step is solved. In addition, the joint leakage problem that may be a problem when using the storage node as a metal film is solved by forming the storage node contact plug in advance. In addition, the metal pattern of the peripheral region patterned at the same time when the storage node is patterned may be used not only as a contact plug of a metal wire but also as a wire for internal connection.

The present invention is not limited to the above-described embodiments and the accompanying drawings, and various permutations, modifications, and changes are possible without departing from the spirit of the present invention. It will be obvious to him.

The present invention forms a storage node in the cell region with a metal film, and simultaneously forms a pattern in the peripheral circuit portion when the storage node is formed in the cell portion, thereby preventing the occurrence of a step, and reducing the metal contact depth in the peripheral circuit region. By making it small, it is effective to greatly improve reliability and yield by applying to the next generation DRAM device.

Claims (6)

Preparing a wafer on which transistors and bit lines are formed; Forming a first interlayer dielectric layer having a storage node contact portion and a metal contact portion in a peripheral region thereof; And A first metal layer is formed on the entire surface to fill the opening, and the patterned first metal layer is selectively etched to form a first pattern of the first metal layer for the storage node and a second pattern of the first metal layer for the metal contact. Steps to A semiconductor device manufacturing method comprising a. The method of claim 1, After forming the first metal layer first pattern and the first metal layer second pattern, Forming a conductive film for the dielectric film of the capacitor and the plate electrode of the capacitor on the front surface thereof; Etching the conductive film and the dielectric film for the plate electrode to expose the second pattern of the first metal layer; Forming a second interlayer insulating film on the entire structure; Selectively etching the second interlayer insulating film to expose a surface of the second pattern of the first metal layer; And Forming a second metal layer pattern contacted with the first metal layer second pattern A semiconductor device manufacturing method further comprising. The method according to claim 1 or 2, And the first metal layer is a multilayer metal layer comprising a barrier metal layer. Preparing a wafer in which a transistor is formed and at which a bit line contact portion and a storage node contact portion are simultaneously opened; Filling the polysilicon layer in the opening to form a bit line contact plug and a storage node contact plug, respectively; Forming a first insulating layer having surfaces of the bit line contact plug and the storage node contact plug open; Forming a bit line conductive layer pattern formed through the first insulating layer and contacted to the bit line contact plug; Forming a second insulating layer in which the semiconductor substrate for the metal contact of the storage node contact plug and the peripheral region is opened; And A first metal layer is formed on the entire surface to fill the opening, and the patterned first metal layer is selectively etched to form a first pattern of the first metal layer for the storage node and a second pattern of the first metal layer for the metal contact. Steps to A semiconductor device manufacturing method comprising a. The method of claim 4, wherein After forming the first metal layer first pattern and the first metal layer second pattern, Forming a conductive film for the dielectric film of the capacitor and the plate electrode of the capacitor on the front surface thereof; Etching the conductive film and the dielectric film for the plate electrode to expose the second pattern of the first metal layer; Forming a third insulating film on the entire structure; Selectively etching the third insulating layer to expose a surface of the second pattern of the first metal layer; And Forming a second metal layer pattern contacted with the first metal layer second pattern A semiconductor device manufacturing method further comprising. The method according to claim 4 or 5, And the first metal layer is a multilayer metal layer comprising a barrier metal layer.