KR20040001548A - Method for manufactruing capacitor in semiconductor device - Google Patents
Method for manufactruing capacitor in semiconductor device Download PDFInfo
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- KR20040001548A KR20040001548A KR1020020036780A KR20020036780A KR20040001548A KR 20040001548 A KR20040001548 A KR 20040001548A KR 1020020036780 A KR1020020036780 A KR 1020020036780A KR 20020036780 A KR20020036780 A KR 20020036780A KR 20040001548 A KR20040001548 A KR 20040001548A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
- H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
- H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
- H01L28/91—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions made by depositing layers, e.g. by depositing alternating conductive and insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic System by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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Abstract
Description
본 발명은 반도체 소자의 캐패시터 제조방법에 관한 것으로, 특히 정전 용량(capacitance)을 증대시키면서 안정적인 캐패시터를 형성할 수 있는 반도체 소자의 캐패시터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a capacitor of a semiconductor device, and more particularly to a method of manufacturing a capacitor of a semiconductor device capable of forming a stable capacitor while increasing capacitance.
최근, 디램(DRAM)을 비롯한 반도체 소자는 농도가 높아짐에 따라 셀 면적은 급격하게 축소되나, 디바이스의 특성을 일정하게 유지하기 위하여 다자인상의 셀 동작에 필요로 하는 일정 용량 이상의 전하 보전 용량의 확보를 위해 공정 개발과 동시에 소자의 신뢰성 확보가 중요하다.In recent years, semiconductor devices, including DRAM, have rapidly reduced cell area as concentration increases. However, in order to maintain a constant device characteristic, it is necessary to secure a charge holding capacity of a predetermined capacity or more required for multi-phase cell operation. It is important to secure the reliability of the device at the same time as the process development.
여기서, 반도체 메모리 장치의 정전 용량은 메모리 장치의 기억 용량을 결정하는 중요한 변수로서, 상기 정전 용량을 증가시키기 위하여 유전막의 유전율, 캐패시터의 유효면적, 또는 유전막의 두께를 변화시킴으로써 가능하다.Here, the capacitance of the semiconductor memory device is an important parameter for determining the memory capacity of the memory device, which is possible by changing the dielectric constant of the dielectric film, the effective area of the capacitor, or the thickness of the dielectric film in order to increase the capacitance.
이에 따라, 고유전률을 갖는 Ta2O5또는 TaON 박막을 이용하여 정전 용량을 증가시키거나, 캐패시터의 유효면적을 증가시킨다.Accordingly, the Ta 2 O 5 or TaON thin film having a high dielectric constant is used to increase the capacitance or increase the effective area of the capacitor.
상기 캐패시터의 유효면적의 증가는, 스토리지노드 전극 상부에 소위 HSG(Hemi hemispheric Grain)막을 성장시킴으로서 전극 표면적을 증가시킨다.Increasing the effective area of the capacitor increases the electrode surface area by growing a so-called Hemi hemispheric grain (HSG) film on top of the storage node electrode.
상기 HSG막을 성장시켜 정전 용량을 증가시키는 방법은 비정질 실리콘막이 다결정 실리콘막으로 상 변태하는 과정에서 특이한 물리적 현상을 이용한 것으로서, 기판에 비정질 실리콘을 증착한 후 열을 가하여 상기 비정질 실리콘막을 미세한 반구 모양의 그레인(grain)들을 형성하여 스토리지노드 전극의 유효면적을 보다 넓게 형성시킨다.The method of increasing the capacitance by growing the HSG film uses an unusual physical phenomenon in the process of transforming the amorphous silicon film into the polycrystalline silicon film. Grains are formed to form a larger effective area of the storage node electrode.
그러나, 종래의 방법은 실리콘 재질의 스토리지노드 전극 전면에 HSG막을 형성할 경우, 스토리지노드 전극의 면적 증가에 따른 캐패시터의 정전용량의 증가는어느 정도 기대할 수 있으나, 상기 HSG막을 포함한 캐패시터의 첨탑 부분이 상대적으로 취약해서 후속 공정을 거치는 동안 그레인이 떨어져서 파티클로 작용하는 문제점이 발생된다.However, in the conventional method, when the HSG film is formed on the entire surface of the storage node electrode made of silicon, the capacitance of the capacitor may increase to some extent due to the increase of the area of the storage node electrode. It is relatively fragile, causing grains to fall and act as particles during subsequent processing.
또한, 실리콘 재질의 스토리지노드 전극의 면저항값이 100Ω/Cm2으로 매우 높기 때문에 캐리어의 이동 시간이 지연되는 문제점이 있었다.In addition, since the sheet resistance of the storage node electrode made of silicon is very high as 100 Ω / Cm 2 , there is a problem that the movement time of the carrier is delayed.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 스토리지노드 전극으로서 HSG 구조의 텅스텐 실리사이드막을 이용함으로써, 캐리어의 이동 시간이 지연되는 현상을 억제하고 안정적인 캐패시터를 형성할 수 있는 반도체 소자의 캐패시터 제조방법을 제공하는데 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by using a tungsten silicide film having an HSG structure as a storage node electrode, a semiconductor device capable of suppressing a phenomenon in which carrier movement time is delayed and forming a stable capacitor can be formed. It is an object of the present invention to provide a capacitor manufacturing method.
도 1a 내지 도 1c는 본 발명의 반도체 소자의 캐패시터 제조방법을 설명하기 위한 단면도.1A to 1C are cross-sectional views illustrating a method for manufacturing a capacitor of a semiconductor device of the present invention.
* 도면의 주요 부분에 대한 부호 설명 *Explanation of symbols on the main parts of the drawings
1. 반도체 기판 2. 접합영역1. Semiconductor substrate 2. Junction area
3. 층간절연막 4,8. 개구부3. Interlayer insulating film 4,8. Opening
5. 도전 플러그 7. 캡 옥사이드막5. Conductive plug 7. Cap oxide film
9, 제 1실리콘 박막 9a. 스토리지노드 전극9, first silicon thin film 9a. Storage node electrode
11, 유전막 13. 제 2실리콘 박막11, dielectric film 13. Second silicon thin film
15. 텅스텐막 17. 플레이트 전극용 도전막15. Tungsten film 17. Conductive film for plate electrodes
상기와 같은 목적을 달성하기 위하여, 본 발명의 반도체 소자의 캐패시터 제조 방법은, 스토리지노드 전극을 포함한 반도체기판을 제공하는 단계와, 상기 구조의 기판 전면에 유전막, 실리콘 박막 및 텅스텐 박막을 차례로 형성하는 단계와, 결과물에 열처리를 실시하여 플레이트 전극용 텅스텐 실리사이드막을 형성하는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, the capacitor manufacturing method of the semiconductor device of the present invention, providing a semiconductor substrate including a storage node electrode, and sequentially forming a dielectric film, a silicon thin film and a tungsten thin film on the front of the substrate of the structure And performing a heat treatment on the resultant to form a tungsten silicide film for a plate electrode.
상기 실리콘 박막은 500∼550℃ 온도에서 저압화학기상증착하여 형성하며, 상기 텅스텐 박막은 350∼400℃ 온도에서 저압화학기상증착하여 형성하는 것이 바람직하다.The silicon thin film is formed by low pressure chemical vapor deposition at a temperature of 500 ~ 550 ℃, the tungsten thin film is preferably formed by low pressure chemical vapor deposition at a temperature of 350 ~ 400 ℃.
또한, 상기 열처리 공정은 800℃ 이하의 온도에서 진행하는 것이 바람직하다.In addition, the heat treatment step is preferably carried out at a temperature of 800 ℃ or less.
(실시예)(Example)
이하, 첨부한 도면을 참조하여, 본 발명의 반도체 소자의 캐패시터 제조방법을 상세히 설명한다.Hereinafter, a method of manufacturing a capacitor of a semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 도 1d는 본 발명에 따른 반도체 소자의 캐패시터 형성 방법을 설명하기 위한 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming a capacitor of a semiconductor device according to the present invention.
본 발명에 따른 반도체 소자의 캐패시터 형성 방법은, 도 1a에 도시된 바와 같이, 트랜지스터(transistor)(미도시)의 접합영역(소오스 또는 드레인)(2)와 접촉하는 제 1개구부(4)가 형성된 층간 절연막(3)을 구비하는 반도체 기판(1)이 제공된다.In the method for forming a capacitor of a semiconductor device according to the present invention, as shown in FIG. 1A, a first opening 4 is formed in contact with a junction region (source or drain) 2 of a transistor (not shown). There is provided a semiconductor substrate 1 having an interlayer insulating film 3.
이어, 상기 제 1개구부(4)를 포함한 층간절연막(3) 상에 화학기상증착(Chemical Vapor Deposition) 공정에 의해 다결정 실리콘층을 증착 및 에치백하여 제 1개구부(4)를 매립시키는 도전 플러그(5)를 형성한 후, 캐패시터 형성을 위한 캡 옥사이드막(7)을 증착한다. 그런다음, 포토리쏘그라피 (photolithography) 공정에 의해 상기 캡옥사이드막(7)을 식각하여 도전 플러그(4)를 노출시키는 제 2개구부(8)을 형성한다.Subsequently, a conductive plug is deposited and etched back on the interlayer insulating film 3 including the first openings 4 by a chemical vapor deposition process to bury the first openings 4. After forming 5), a cap oxide film 7 for capacitor formation is deposited. Then, the cap oxide film 7 is etched by a photolithography process to form a second opening 8 exposing the conductive plug 4.
그런 다음, 제 2개구부(8)를 포함한 기판 전면에 화학기상증착(Chemical Vapor Deposition) 공정에 의해 스토리지노드 전극용 제 1 비정질 실리콘 박막(9)을 형성한다. 이때, 상기 제 1실리콘 박막(9)은 인(Phosphorous)이 도핑되어 있다.Then, the first amorphous silicon thin film 9 for the storage node electrode is formed on the entire surface of the substrate including the second opening 8 by a chemical vapor deposition process. In this case, the first silicon thin film 9 is doped with phosphorous (Phosphorous).
이 후, 상기 제 1비정질 실리콘 박막을 에치백(etch back)하여 스토리지노드전극(9a)을 형성하고 나서, 스토리지노드 전극(9a)을 포함한 기판 전면에 Si3N4유전막(11)을 형성한다.Thereafter, the first amorphous silicon thin film is etched back to form a storage node electrode 9a, and then a Si 3 N 4 dielectric film 11 is formed on the entire surface of the substrate including the storage node electrode 9a. .
계속해서, Si3N4유전막(11) 상에 500∼550℃ 온도에서 인 도핑된 실리콘을 저압 화학기상증착하여 비정질의 제 2실리콘 박막(13)을 형성하고 나서, 연속해서, 350∼400℃ 온도에서 저압 화학기상증착하여 비정질의 텅스텐 박막(15)을 형성한다.Subsequently, low-pressure chemical vapor deposition of phosphorus-doped silicon at a temperature of 500 to 550 ° C. on the Si 3 N 4 dielectric film 11 to form an amorphous second silicon thin film 13 was continued, followed by 350 to 400 ° C. Low-pressure chemical vapor deposition at a temperature forms an amorphous tungsten thin film 15.
이어, 상기 결과물에 빠른 열처리(Rapid Thermal Anneal)(20)를 실시함으로서, 도 1c에 도시된 바와 같이, 텅스텐 박막과 제 2실리콘 박막이 화학 반응하여 플레이트 전극용 텅스텐 실리사이드막(17)을 형성한다. 이때, 빠른 열처리(20) 공정은 800℃ 미만의 온도에서 진행하여 웰 내부 도판트의 확산거리를 최소화하여 문턱 전압에 영향을 미치지 않도록 한다. 또한, 상기 텅스텐 실리사이드막 형성은 셀프 어라인 실리사이드 방식으로 진행하여 Si3N4유전막(11)과 텅스텐 실리사이드막(17)의 계면 열화 현상을 제거한다.Next, by performing a rapid thermal annealing 20 on the resultant, as shown in FIG. 1C, the tungsten thin film and the second silicon thin film are chemically reacted to form a tungsten silicide film 17 for a plate electrode. . At this time, the rapid heat treatment process 20 proceeds at a temperature of less than 800 ℃ to minimize the diffusion distance of the dopant in the well so as not to affect the threshold voltage. In addition, the formation of the tungsten silicide layer proceeds in a self-aligned silicide manner to remove the interface degradation between the Si 3 N 4 dielectric layer 11 and the tungsten silicide layer 17.
본 발명에 따르면, 캐패시터의 플레이트 전극으로서 10μΩ/Cm2미만의 면저항값을 가진 텅스텐 실리사이드막을 채택함으로써, 캐리어의 이동 시간이 지연되는 현상을 억제할 수 있다.According to the present invention, by adopting a tungsten silicide film having a sheet resistance value of less than 10 mu OMEGA / Cm 2 as the plate electrode of the capacitor, it is possible to suppress the phenomenon that the movement time of the carrier is delayed.
이상에서 자세히 설명한 바와같이, 본 발명은 캐패시터의 플레이트 전극으로서 10μΩ/Cm2미만의 면저항값을 가진 텅스텐 실리사이드막을 채택함으로써, 기존의 실리콘막보다 면저항값이 훨씬 낮기 때문에 캐리어의 이동 시간이 지연되는 현상이 억제된다.As described in detail above, the present invention adopts a tungsten silicide film having a sheet resistance value of less than 10 μΩ / Cm 2 as a plate electrode of a capacitor, thereby delaying carrier movement time because the sheet resistance value is much lower than that of a conventional silicon film. This is suppressed.
또한, 본 발명에서는 HSG 구조의 텅스텐 실리사이드막이 기존의 실리콘막보다 그레인 밀도가 크기 때문에 정전 용량을 증가시킬 뿐만 아니라 캐패시터의 첨탑 부분의 그레인이 떨어질 우려가 없다.In addition, in the present invention, since the tungsten silicide film having the HSG structure has a larger grain density than the conventional silicon film, not only does the capacitance increase, but there is no fear that the grain of the spire portion of the capacitor falls.
기타, 본 발명은 그 요지를 벗어나지 않는 범위내에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (5)
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| KR10-2002-0036780A KR100451516B1 (en) | 2002-06-28 | 2002-06-28 | Method for manufactruing capacitor in semiconductor device |
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| KR10-2002-0036780A KR100451516B1 (en) | 2002-06-28 | 2002-06-28 | Method for manufactruing capacitor in semiconductor device |
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| KR20040001548A true KR20040001548A (en) | 2004-01-07 |
| KR100451516B1 KR100451516B1 (en) | 2004-10-06 |
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| JPH03153065A (en) * | 1989-11-10 | 1991-07-01 | Sharp Corp | Capacity insulation film formation method |
| JP3419660B2 (en) * | 1997-10-01 | 2003-06-23 | 沖電気工業株式会社 | Method of forming capacitance section of semiconductor device, and method of forming capacitance section and gate section of semiconductor device |
| KR100292692B1 (en) * | 1998-09-10 | 2001-07-12 | 김영환 | Capacitor Manufacturing Method for Semiconductor Devices |
| KR100329741B1 (en) * | 1999-06-07 | 2002-03-21 | 박종섭 | Method for forming capacitor having tungsten silicide bottom electrode |
| KR100373159B1 (en) * | 1999-11-09 | 2003-02-25 | 주식회사 하이닉스반도체 | Method of manufacturing a capacitor in a semiconductor device |
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