JPH05299600A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a method of manufacturing a semiconductor device, where a silicon nitride film is excellent in electrical properties even if it is formed thin and a base electrode is protected against abnormal oxidation when the surface of the silicon nitride film is oxidized. CONSTITUTION:A field oxide film 2, a gate oxide film 3, and a gate electrode 4 are formed on a single crystal silicon substrate 1, then ions are implanted to form a source/drain region 5, and an oxide film 7 provided with a contact hole 6 is formed on all the surface of the source/drain region 5, and a polycrystalline silicon 8 is formed on the oxide film 7 and turned into single crystal by laser annealing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a DRAM, and more particularly, the capacity storage electrode of a stack type memory cell is made of single crystal silicon or polycrystalline silicon having a huge grain of 0.5 .mu.m or more. The present invention relates to the formation of the lower electrode of the capacitor.

[0002]

2. Description of the Related Art Conventionally, the lower and upper electrodes of a stack type memory cell have been formed of polycrystalline silicon containing P or As. The crystal grain size of the polycrystalline silicon was about 0.1 to 0.3 μm. FIG. 1 is a process cross-sectional view for explaining an embodiment of a method for manufacturing a semiconductor device of the present invention which will be described later, but in explaining a method for forming a lower electrode of a capacitor as a conventional method for manufacturing a semiconductor device, this figure will be referred to. 1 will be described.

First, as shown in FIG. 1A, a field oxide film 2 is formed on a silicon substrate 1, a gate oxide film 3 and a gate electrode 4 made of polycrystalline silicon are formed, and then,
Ions are implanted to form source / drain regions 5, and the entire surface except the contact holes 6 on the source / drain regions 5 is depressurized on a silicon wafer covered with an oxide film 7 obtained by a CVD method. Polycrystalline silicon 8 is formed with a thickness of 1000 Å to 4000 by a CVD (LP-CVD) method.
Å About forming. As a condition for forming the polycrystalline silicon 8 at this time, SiH ₄ is used as a gas, and
The pressure of the _four gases is 0.1 to 0.4 Torr, and the temperature is 580 to 650 ° C. The crystal grain size of the polycrystalline silicon 8 is as small as 0.02 to 0.1 μm, and the surface of the polycrystalline silicon has an uneven surface when viewed microscopically.

Next, as shown in FIG. 1B, phosphorus or A is added in order to make the polycrystalline silicon 8 conductive.
s is introduced into the polycrystalline silicon 8 by ion implantation or the like. Next, the polycrystalline silicon 8 is partially left by the lithography and etching technique to remove the DRA.
The storage electrode 9 of M capacity is formed.

Then, as shown in FIG. 1 (c), phosphorus or As in the polycrystalline silicon 8 is electrically activated by a heat treatment at 850 to 900 ° C., and then the LP-CVD method (SiH ₂ By the reaction of Cl ₂ and NH _3, the silicon nitride film 10 serving as a dielectric film is formed to a thickness of 5 to 10 μm at 600 ° C. to 800 ° C. and a pressure of 0.1 to 0.4 Torr).

Next, in order to reduce defects in the silicon nitride film 10, the surface of the silicon nitride film 10 is oxidized, for example, at 900 ° C. for 20 minutes in a wet atmosphere to form an oxide film 11.
To form.

Next, as shown in FIG. 1D, a polycrystalline silicon film 12 to be an upper electrode is partially formed on the entire surface,
Form the capacity of the DRAM.

[0008]

However, the above-described method for manufacturing a semiconductor device has the following problems, and therefore a thin silicon nitride film cannot be used as a dielectric.

That is, the silicon nitride film 1 which is a dielectric
When 0 is formed, the grain size of the underlying polycrystalline silicon film is small, and the surface thereof is not smooth, and fine unevenness remains formed. Further, the grain size of the polycrystalline silicon at that time is about 0.1 to 0.4 micron,
The fine irregularities are about 0.01 to 0.02 micron.

The TDDB (electrical reliability) of the silicon nitride film formed on the surface of the polycrystalline silicon in such a state deteriorates. It is considered that this is because electric field concentration occurs due to fine irregularities on the surface. The silicon nitride film formed on the surface of such polycrystalline silicon has weak oxidation resistance (the base electrode is oxidized when the surface of the silicon nitride film is oxidized), and has a drawback that it cannot be thinned. ..

It is considered that this is because fine grains of polycrystalline silicon grow in the heat treatment during the subsequent process and exert a stress on the silicon nitride film 10.

It is an object of the present invention to provide a method of manufacturing a semiconductor device, which solves the problem that a thin silicon nitride film cannot be used in forming a capacitance of a DRAM or the like among the problems of the above-mentioned prior art. To do.

[0013]

In order to solve the above-mentioned problems, the present invention is directed to forming a lower electrode of a capacitor,
Introducing a step of forming single crystal by laser annealing after forming polycrystalline silicon on the surface of a wafer where the entire surface is covered with an insulating film except for the part where the conductive layer made of single crystal silicon is exposed on the surface Is.

Further, for forming the lower electrode of the capacitor,
This method introduces a process of forming polycrystalline silicon having a huge grain of 0.5 μm or more on a wafer whose entire surface except a part is covered with an insulating film.

[0015]

According to the present invention, since the above steps are introduced in the formation of the lower electrode of the capacitor, after the polycrystalline silicon is formed, the polycrystalline silicon is formed by laser annealing using the contact portion with the underlying single crystal silicon as a seed. By changing the silicon to single crystal silicon, the surface becomes smooth and even if the silicon nitride film as a dielectric film formed on the upper surface is thinned, abnormal oxidation of the base electrode occurs when the surface of the nitride film is oxidized. And exhibits good electrical characteristics, thus eliminating the above-mentioned problems.

Further, as a lower electrode of the capacitor, 0.
Since polycrystalline silicon having a huge grain of 5 microns or more is formed, electric field concentration due to fine irregularities is unlikely to occur, and deterioration of electrical characteristics is suppressed, and a silicon nitride film as a dielectric film formed on the surface is suppressed. Even if it is thinned, abnormal oxidation of the base electrode does not occur when the surface of the nitride film is oxidized,
It exhibits good electrical properties and thus eliminates the abovementioned problems.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. 1 (a) to 1 (d) are process cross-sectional views of one embodiment of the present invention. In FIG. 1 (a) to 1 (d), first, in FIG. alike,
A field oxide film 2 is formed on a single crystal silicon substrate 1, a gate oxide film 3 and a gate electrode 4 made of polycrystalline silicon are formed, and then ions are implanted to form source / drain regions 5. First, polycrystalline silicon 8 is formed on the entire surface of the semiconductor wafer covered with the oxide film 7 obtained by the CVD method except for the contact hole 6 formed on the drain region 5. This film thickness is 0.
For example, silane is used as the forming condition, the pressure is 0.1 to 0.4 Torr, and the temperature is 580 ° C. to 650 ° C.

Next, laser annealing is performed. Since the film of polycrystalline silicon 8 is partially connected to the single crystal silicon substrate 1 through the contact hole 6, the film of polycrystalline silicon 8 is subjected to laser annealing by using the single crystal silicon of the part as a seed. Single crystallized. Thereafter, similarly to the conventional example described above, the capacitors are formed in the same manner as in the conventional example by going through the steps of FIGS. 1B to 1D.

Next, a second embodiment of the present invention will be described. In the second embodiment, on the wafer shown in FIG. 1A, ion beam etching or the like is performed on the oxide film 7 serving as the underlying insulating film before forming the film of the polycrystalline silicon 8 serving as the storage electrode. Thus, a pattern (not shown) for graphoepi is formed. As a result, it is possible to eliminate the difficulty of depositing polycrystalline silicon on the oxide film 7.

Next, as also shown in FIG. 1A, first, a film of polycrystalline silicon 8 is formed on the entire surface. The film thickness is about 0.1 to 0.4 μm. As the forming conditions, for example, silane is used, and the pressure is 0.1 to 0.4 μm.
Torr and temperature are 580 ° C to 650 ° C. Next, high-temperature heat treatment is performed and graphoepi is performed. As a result, the film of polycrystalline silicon 8 is monocrystallized. Next in FIG.
Capacitance is formed in the same manner as shown in (b) to FIG. 1 (d).

Next, a third embodiment of the present invention will be described. In the third embodiment, amorphous silicon is used as the storage electrode instead of conventional polycrystalline silicon.
As the forming method at this time, low pressure CVD is used as in the case of polycrystalline silicon. Disilane is used as the reaction gas. The reaction temperature is 450 ° C. to 550 ° C., and the reaction pressure is 0.1 to 0.4 Torr. The film thickness is 0.1 to 0.
It is about 4 microns. Next, the amorphous silicon is
Heat treatment at a temperature of 0 ° C to 600 ° C for 1 to 10 hours,
Enlarge grains to 0.5 microns or more. Next, the same capacitance formation as shown in FIGS. 1B to 1D is performed.

When polycrystalline silicon of this giant grain is used as a storage electrode and a silicon nitride film 10 is formed on the storage electrode, a change due to a difference in oxidation resistance between base electrodes is shown in FIG. FIG. 2 shows the case of 900 ° C. wet oxidation, in which the horizontal axis represents the film thickness of the silicon nitride film 10 and the vertical axis represents the film thickness of the silicon nitride film 10 after oxidation. A and broken line B are the case of this invention. The solid line A shows the case where the storage electrode underlying the silicon nitride film 10 is single crystal silicon, the broken line B shows the case of polycrystalline silicon with a huge grain of 0.5 μm or more, and the solid line C shows an example of a normal process. Shows the case. As is clear from FIG. 2, according to the present invention, even if the thickness of the silicon nitride film 10 is reduced, the oxidation resistance is excellent.

Next explained is the fourth embodiment of the invention. In the fourth embodiment, silane is used as a reaction gas when forming the amorphous silicon in the third embodiment. In that case, the forming condition is a temperature of 500 ° C.
˜550 ° C., pressure 0.1 to 0.4 Torr, film thickness 0.1 to 0.4 μm.

Further, as a fifth embodiment of the present invention, amorphous doped silicon containing phosphorus or arsenic from the time of film formation is used as a storage electrode. As the reaction gas, disilane and phosphine when phosphorus is doped are used. The formation conditions are a temperature of 450 ° C. to 550 ° C. and a reaction pressure of silane of 0.1 to 0.4 Torr. The film thickness is about 0.1 to 0.4 micron. At this time, the amount of phosphine is adjusted so that the concentration of phosphorus in the formed polycrystalline silicon is 1E20 to 1E21 pieces / cm ³ .

Next, heat treatment is performed at a temperature of 500 ° C. to 600 ° C. for 1 hour to 10 hours to enlarge the grains. In this case, a film having larger grains than that of the third embodiment can be obtained. Next, the same capacitance formation as shown in FIGS. 1B to 1D is performed. However, in this case,
It is not necessary to introduce the impurities into the formed polycrystalline silicon by the ion implantation or the like described in (b).

Next explained is the sixth embodiment of the invention. In the case of the sixth embodiment, silane and phosphine are used as the reaction gas used when the polycrystalline silicon is produced in the fifth embodiment. In that case, the forming conditions are a temperature of 550 ° C. to 600 ° C., a pressure of 0.1 to 0.4 Torr, and a film thickness of 0.1 to 0.4 μm. The amount of phosphine depends on the phosphorus concentration in the polycrystalline silicon.
Adjust from 1E20 to 1E21 pieces / cm ³ .

Next, heat treatment is performed at a temperature of 500 ° C. to 600 ° C. for 1 to 10 hours to enlarge the grains. Next, the same capacitance formation as shown in FIGS. 1B to 1D is performed. However, in this case, the introduction of impurities into the polycrystalline silicon by ion implantation or the like shown in FIG. 1B is unnecessary.

[0028]

As described above in detail, according to the present invention, polycrystalline silicon is laser-annealed to form single crystal silicon as the lower electrode of the capacitor, so that it is used as a dielectric film. Even if the silicon nitride film is thinned, it shows good electrical characteristics, and even if it is thinned,
When the surface of the silicon nitride film is oxidized, abnormal oxidation of the base electrode does not occur, so that the lower electrode of the capacitor having good characteristics can be formed.

Further, since the lower electrode is made of polycrystalline silicon having a huge grain of 0.5 μm or more, electric field concentration due to fine unevenness is less likely to occur, and the silicon nitride film used as the dielectric film can be thinned. It is possible to obtain a lower electrode of a capacitor which has excellent electrical characteristics and does not cause abnormal oxidation of the base electrode when the surface of the silicon nitride film is oxidized.

[Brief description of drawings]

FIG. 1 is a process sectional view of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an oxidation resistance characteristic diagram of a silicon nitride film on polycrystalline silicon formed by the method for manufacturing a semiconductor device of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Single crystal silicon substrate 2 Field oxide film 3 Gate oxide film 4 Gate electrode 5 Source / drain region 6 Contact hole 7 Oxide film 8 Polycrystalline silicon 9 Storage electrode 10 Silicon nitride film 11 Oxide film 12 Polycrystalline silicon film

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Nobuhiko Inoue 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (4)

[Claims] 1. A step of forming a conductive layer made of single crystal silicon in or on a surface of a semiconductor substrate, a step of forming an insulating film on the surface of the substrate including the conductive layer, and selectively forming the insulating film. Removing, forming a region where the conductive layer is exposed on the surface, forming a first film made of polycrystalline silicon on the insulating film including the region where the conductive layer is exposed on the surface, A laser annealing step for converting polycrystalline silicon of the first film into single crystal silicon; a step of implanting impurities into the first film; a heat treatment step for activating the implanted impurities; And a step of forming a dielectric film of a capacitor made of a silicon nitride film on the first film. 2. A step of forming a conductive layer in or on a surface of a semiconductor substrate; a step of forming an insulating film on the surface of the substrate including the conductive layer; and a step of selectively removing the insulating film to form the conductive layer. Forming a region where the layer is exposed on the surface, and forming a first conductive film made of polycrystalline silicon having a grain of 0.5 μm or more on the insulating film including the region where the conductive layer is exposed on the surface. And a step of forming a dielectric film of a capacitor made of a silicon nitride film on the first conductive film, the method of manufacturing a semiconductor device. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the conductive layer is made of polycrystalline silicon having a grain of 0.5 μm or more on the insulating film including a region exposed on the surface. As the step of forming the first conductive film, a second film made of amorphous silicon is formed on the insulating film including a region where the conductive layer is exposed on the surface by a chemical vapor deposition method using silane as a reaction gas. And a step of forming amorphous silicon of the second film from 500 ° C. to 600 ° C.
A heat treatment for 1 to 10 hours at a temperature of 1 to 10; a step of implanting impurities into the second film; and a heat treatment step for activating the implanted impurities. Production method. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the conductive layer is made of polycrystalline silicon having a grain of 0.5 μm or more on the insulating film including a region exposed on the surface. As the step of forming the first conductive film, a third layer of amorphous doped silicon is formed on the insulating film including the region where the conductive layer is exposed on the surface by chemical vapor deposition using silane and phosphine as reaction gases. And forming the third film of amorphous-doped silicon from 500 ° C. to 6 ° C.
And a step of performing heat treatment at a temperature of 00 ° C. for 1 to 10 hours.