KR20040001266A - method for manufacturing contact hole - Google Patents
method for manufacturing contact hole Download PDFInfo
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- KR20040001266A KR20040001266A KR1020020036406A KR20020036406A KR20040001266A KR 20040001266 A KR20040001266 A KR 20040001266A KR 1020020036406 A KR1020020036406 A KR 1020020036406A KR 20020036406 A KR20020036406 A KR 20020036406A KR 20040001266 A KR20040001266 A KR 20040001266A
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- contact hole
- forming
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- barrier metal
- metal line
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- 238000000034 method Methods 0.000 title claims abstract description 47
- 238000004519 manufacturing process Methods 0.000 title 1
- 229910052751 metal Inorganic materials 0.000 claims abstract description 70
- 239000002184 metal Substances 0.000 claims abstract description 70
- 230000004888 barrier function Effects 0.000 claims abstract description 35
- 238000005530 etching Methods 0.000 claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 229910052782 aluminium Inorganic materials 0.000 claims abstract description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract description 4
- 239000007789 gas Substances 0.000 claims description 9
- BSYNRYMUTXBXSQ-UHFFFAOYSA-N Aspirin Chemical compound CC(=O)OC1=CC=CC=C1C(O)=O BSYNRYMUTXBXSQ-UHFFFAOYSA-N 0.000 claims description 4
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 11
- 239000004411 aluminium Substances 0.000 abstract 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- 238000000151 deposition Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000002440 hepatic effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
- 230000000087 stabilizing effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
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- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 콘택홀 형성 방법에 관한 것으로, 보다 상세하게는 알루미늄막과 베리어 금속막의 2중 적층 구조를 가진 하부 금속라인을 노출시키는 콘택홀 형성에 있어서, 공정 안정화를 꾀할 수 있는 콘택홀 형성 방법에 관한 것이다.The present invention relates to a method for forming a contact hole, and more particularly, to a contact hole forming method capable of stabilizing a process in forming a contact hole exposing a lower metal line having a double stacked structure of an aluminum film and a barrier metal film. It is about.
반도체 소자의 집적도가 증가함에 따라 워드라인 및 비트라인의 크기가 작아지며, 이 뿐만 아니라 상기 라인들을 연결시키는 금속층 간의 콘택홀의 크기도 작아지고 있다.As the degree of integration of semiconductor devices increases, the size of word lines and bit lines decreases, as well as the size of contact holes between metal layers connecting the lines.
도 1a 내지 도 1c는 종래 기술에 따른 콘택홀 형성 방법을 설명하기 위한 공정단면도이다.1A to 1C are cross-sectional views illustrating a method of forming a contact hole according to the related art.
종래 기술에 따른 콘택홀 형성 방법은, 도 1a에 도시된 바와같이, 반도체기판(1) 상에 알루미늄막(Al막)과 베리어 금속막(TiN막)을 차례로 증착한 후, 리쏘그라피 공정에 의해 상기 막들을 식각하여 하부 금속라인(14)을 형성한다. 이때, 도면부호 3은 식각 후 잔류된 알루미늄막을 나타낸 것이고, 도면부호 5는 잔류된 베리어 금속막을 나타낸 것이다.In the conventional method for forming a contact hole, as shown in FIG. 1A, an aluminum film (Al film) and a barrier metal film (TiN film) are sequentially deposited on a semiconductor substrate 1, and then subjected to a lithography process. The films are etched to form the lower metal line 14. In this case, reference numeral 3 denotes an aluminum film remaining after etching, and reference numeral 5 denotes a residual barrier metal film.
이어, 도 1b에 도시된 바와 같이, 하부 금속라인(14)을 포함한 기판 전면에 층간절연막(8)을 형성하고, 포토리쏘그라피 공정에 의해 상기 층간절연막(8)을 식각하여 하부 금속라인(14)을 노출시키는 콘택홀(9)을 형성한다. 이때, 상기 콘택홀 식각 공정에서, 하부 금속라인(14) 상의 베리어 금속막이 완전히 식각된다.Subsequently, as shown in FIG. 1B, an interlayer insulating film 8 is formed on the entire surface of the substrate including the lower metal line 14, and the interlayer insulating film 8 is etched by a photolithography process to etch the lower metal line 14. The contact hole 9 exposing) is formed. At this time, in the contact hole etching process, the barrier metal film on the lower metal line 14 is completely etched.
그런 다음, 상기 콘택홀(9)을 포함한 층간절연막(8) 상에 스퍼터링 공정에 의해 텅스텐 등의 제 1도전막을 증착하고 씨엠피(Chemical Mechnical Polishing) 공정을 차례로 진행하여 하부 금속라인(14)과 연결되는 도전 플러그(10)를 형성한다.Then, a first conductive film such as tungsten is deposited on the interlayer insulating film 8 including the contact hole 9 by a sputtering process, and a chemical mechanical polishing process is performed in order to sequentially process the lower metal line 14 and the lower metal line 14. The conductive plug 10 to be connected is formed.
이 후, 도 1c에 도시된 바와 같이, 상기 도전 플러그(10)를 포함한 층간절연막 전면에 스퍼터링 공정에 의해 제 2도전막을 증착 및 패턴 식각하여 상부 금속라인(12)을 형성한다. 이때, 상부 금속라인(12)은 도전 플러그(10)를 통해 하부 금속라인(14)과 연결된다.Thereafter, as illustrated in FIG. 1C, the upper conductive metal layer 12 is formed by depositing and pattern-etching the second conductive layer on the entire surface of the interlayer insulating layer including the conductive plug 10 by a sputtering process. In this case, the upper metal line 12 is connected to the lower metal line 14 through the conductive plug 10.
종래의 기술에서는 콘택홀 형성 시 하부 금속라인 상의 베리어 금속막이 완전히 제거됨으로써, 하부 금속라인의 알루미늄막이 노출된다. 따라서, 상기 노출된 알루미늄막은 후속 공정인 도전플러그용 텅스텐 증착 공정에서 텅스텐과 반응하여 불안정한 막이 형성되는데, 이러한 불안정막의 형성을 막기 위해서는 텅스텐 증착 이전에 별도의 베리어 금속막을 형성해야 한다.In the related art, the barrier metal film on the lower metal line is completely removed when forming the contact hole, thereby exposing the aluminum film of the lower metal line. Accordingly, the exposed aluminum film reacts with tungsten in a tungsten deposition process for a conductive plug, which is a subsequent process, to form an unstable film. In order to prevent the formation of the unstable film, a separate barrier metal film must be formed before tungsten deposition.
그러나, 집적도 증가에 의한 콘택홀 크기가 작아짐에 따라, 별도의 베리어 금속막 증착 시 스텝 커버리지(step coverage)가 불량해짐으로써 콘택홀 바닥부분에서 베리어 금속막이 제대로 형성되지 않아 불량 원인으로 작용하는 문제점이 있었다.However, as the contact hole size decreases due to the increase in integration, the step coverage becomes poor when depositing a separate barrier metal film, so that the barrier metal film is not properly formed at the bottom of the contact hole, thereby causing a problem. there was.
이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 콘택홀 형성을 위한 식각 공정에서, 하부 금속라인의 베리어 금속막에 대한 선택비를 높임으로써, 후속 공정에서 별도의 베리어 금속막을 형성하는 단계를 생략할 수 있는 콘택 형성 방법을 제공함에 그 목적이 있다.Accordingly, the present invention has been made to solve the above problems, in the etching process for forming the contact hole, by increasing the selectivity to the barrier metal film of the lower metal line, to form a separate barrier metal film in a subsequent process It is an object of the present invention to provide a method for forming a contact in which a step can be omitted.
도 1a 내지 도 1c는 종래 기술에 따른 콘택홀 형성 방법을 설명하기 위한 공정단면도.1A to 1C are cross-sectional views illustrating a method of forming a contact hole according to the related art.
도 2a 내지 도 2e는 본 발명에 따른 콘택홀 형성 방법을 설명하기 위한 공정단면도.2A through 2E are cross-sectional views illustrating a method of forming a contact hole according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
100. 반도체 기판 102. 알루미늄막100. Semiconductor substrate 102. Aluminum film
104, 105. 베리어 금속막 110. 층간절연막104, 105. Barrier metal film 110. Interlayer insulating film
111. 콘택홀 112. 도전 플러그111. Contact Holes 112. Conductive Plugs
114. 상부 금속라인 130. 감광막 패턴114. Upper metal line 130. Photoresist pattern
124. 하부 금속라인124. Lower Metal Lines
상기 목적을 달성하기 위한 본 발명에 따른 콘택홀 형성 방법은 반도체 기판 상에 알루미늄막과 베리어 금속막의 2중 적층 구조의 하부 금속라인을 형성하는 단계와, 하부 금속라인을 포함한 기판 전면에 층간절연막을 형성하는 단계와, 포토리쏘그라피 공정에 의해 층간절연막을 식각하여 콘택홀을 형성하되, 상기 하부 금속라인의 베리어 금속막에 대한 선택비를 높여 상기 콘택홀 바닥부분에 상기 베리어 금속막을 잔류시키는 단계를 포함한 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a contact hole, the method comprising: forming a lower metal line having a double stacked structure of an aluminum film and a barrier metal film on a semiconductor substrate; Forming a contact hole by etching the interlayer insulating film by a photolithography process, and increasing the selectivity to the barrier metal film of the lower metal line to leave the barrier metal film at the bottom of the contact hole. It is characterized by including.
상기 베리어 금속막은 TiN막을 이용하며, 상기 TiN막은 화학기상증착 공정에 의해 형성하는 것이 바람직하다.The barrier metal film uses a TiN film, and the TiN film is preferably formed by a chemical vapor deposition process.
상기 콘택홀을 형성하는 단계는 C4F8및 O2식각 가스에 의해 건식 식각하며, C4F8가스와 O2가스는 1:1비율을 가진다. 또한, 상기 콘택홀 형성 단계는 마이크로웨이브 다운 스트림, ICP, ECR, TCP,헬리콘 중 어느 하나의 방식의 플라즈마 챔버를 사용한다.The forming of the contact hole is dry etching by using C 4 F 8 and O 2 etching gases, and the C 4 F 8 gas and the O 2 gas have a 1: 1 ratio. In addition, the contact hole forming step uses a plasma chamber of any one of microwave downstream, ICP, ECR, TCP, Helicon.
상기 콘택홀을 형성한 후에, 콘택홀을 매립시키는 도전 플러그를 형성하는 단계와, 결과물 상에 도전 플러그와 연결되는 상부 금속라인을 형성하는 단계를 추가할 수도 있다.After forming the contact hole, the method may further include forming a conductive plug for filling the contact hole, and forming an upper metal line connected to the conductive plug on the resultant.
이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2e는 본 발명에 따른 콘택홀 형성 방법을 설명하기 위한 공정단면도이다.2A through 2E are cross-sectional views illustrating a method of forming a contact hole according to the present invention.
본 발명에 따른 콘택홀 형성 방법은, 도 2a에 도시된 바와 같이, 먼저, 트랜지스터(미도시) 등이 제조된 반도체 기판(100) 상에 알루미늄막(102)과 베리어 금속막(104)의 2중 적층 구조를 가진 하부 금속라인(124)를 형성한다. 이때, 상기 베리어 금속막(104)으로는 TiN막을 이용하며, 상기 TiN막은 화학기상증착(Chemical Vapor Deposition)하여 형성한다.In the method for forming a contact hole according to the present invention, as shown in FIG. A lower metal line 124 having a stacked structure is formed. At this time, the barrier metal film 104 is a TiN film, and the TiN film is formed by chemical vapor deposition (Chemical Vapor Deposition).
이어, 도 2b에 도시된 바와 같이, 하부 금속라인(124)을 포함한 기판 전면에 층간절연막(110)을 형성한 후, 상기 층간절연막(110) 상에 콘택홀영역(미도시)이 정의된 감광막 패턴(130)을 형성한다.Subsequently, as shown in FIG. 2B, after forming the interlayer insulating film 110 on the entire surface of the substrate including the lower metal line 124, a photoresist film in which a contact hole region (not shown) is defined on the interlayer insulating film 110. The pattern 130 is formed.
그런 다음, 도 2c에 도시된 바와 같이, 상기 감광막 패턴(130)을 식각 장벽으로 하고 층간절연막(110)을 식각하여 콘택홀(111)을 형성한다. 이때, 상기 콘택홀(111) 형성을 위한 식각 공정에서, 식각가스로 1: 1 비율의 C-F 계열 가스(예를 들면, C4F8)와 O2가스(140)를 공급함으로서, 하부 금속라인(124)의 베리어 금속막에 대한 식각 선택비를 높여 베리어 금속막의 소정두께가 잔류되도록 한다. 또한, 상기 콘택홀(111) 형성을 위한 식각 공정은 마이크로웨이브 다운 스트림(microwave down stream), ICP(Inductively Coupled Plasma), ECR(Electron Cycle Resonance), TCP(Tri Coupled Plasma), 헬리콘(helicon) 중 어느 하나의 방식의 플라즈마 챔버(plasma chamber)를 사용한다. 한편, 도면부호 105는 콘택홀(111) 형성을 위한 식각 공정을 진행한 후 잔류된 베리어 금속막을 나타낸 것이다.Next, as shown in FIG. 2C, the contact layer 111 is formed by using the photoresist pattern 130 as an etch barrier and the interlayer insulating layer 110 is etched. At this time, in the etching process for forming the contact hole 111, by supplying a CF-based gas (for example, C 4 F 8 ) and O 2 gas 140 of the ratio 1: 1 to the etching gas, the lower metal line An etch selectivity with respect to the barrier metal film at 124 is increased so that a predetermined thickness of the barrier metal film remains. In addition, the etching process for forming the contact hole 111 may include microwave down stream, inductively coupled plasma (ICP), electrified cycle resonance (ECR), tricoupled plasma (TCP), and helicon (helicon). Either method of the plasma chamber (plasma chamber) is used. Meanwhile, reference numeral 105 denotes a barrier metal film remaining after the etching process for forming the contact hole 111.
이 후, 감광막 패턴을 제거하고 나서, 도 2d에 도시된 바와 같이, 콘택홀(111)을 포함한 기판 전면에 스퍼터링 공정에 의해 텅스텐막을 증착하고 씨엠피하여 콘택홀(111)을 매립시키는 도전 플러그(112)를 형성한다. 이때, 도전 플러그(112)는 콘택홀(111)의 바닥부분에 잔류된 베리어 금속막(105) 위에 형성되므로, 상기 베리어 금속막(105)에 의해 하부 금속라인(124)의 알루미늄막(102) 간의화학 반응이 차단된다.Thereafter, after removing the photoresist layer pattern, as shown in FIG. 2D, a tungsten film is deposited on the entire surface of the substrate including the contact hole 111 by a sputtering process, and the CMP is used to fill the contact hole 111. ). In this case, since the conductive plug 112 is formed on the barrier metal film 105 remaining at the bottom of the contact hole 111, the aluminum film 102 of the lower metal line 124 is formed by the barrier metal film 105. Hepatic chemical reactions are blocked.
이어, 도 2e에 도시된 바와 같이, 상기 도전 플러그(112)를 포함한 층간절연막(110) 전면에 스퍼터링 공정에 의해 다시 금속막을 증착 및 씨엠피 공정을 거쳐 상부 금속라인(114)을 형성한다. 이때, 상기 상부 금속라인(114)은 도전 플러그(112)를 통해 하부 금속라인(124)과 연결된다.Subsequently, as illustrated in FIG. 2E, the upper metal line 114 is formed on the entire surface of the interlayer insulating layer 110 including the conductive plug 112 by a sputtering process and a metal film 114 through a CMP process. In this case, the upper metal line 114 is connected to the lower metal line 124 through the conductive plug 112.
본 발명에 따르면, 콘택홀 형성을 위한 식각 공정에 있어서, 하부 금속라인의 베리어 금속막에 대한 식각 선택비를 높여 베리어 금속막을 잔류시킴으로써, 이 후의 도전 플러그용 텅스텐막 증착 시에 상기 텅승텐과 알루미늄막과 반응되는 것을 박을 수 있다.According to the present invention, in the etching process for forming the contact hole, by increasing the etching selectivity with respect to the barrier metal film of the lower metal line, the barrier metal film is left, so that the tungsten and aluminum in the subsequent deposition of the tungsten film for the conductive plug Can react with the membrane.
이상에서와 같이, 본 발명은 콘택홀 형성 시 하부 금속라인의 베리어 금속막에 대한 식각 선택비를 높임으로써, 콘택홀 마진을 확보하여 공정 안정화를 이룰 수 있다.As described above, the present invention increases the etching selectivity for the barrier metal layer of the lower metal line when forming the contact hole, thereby securing a contact hole margin and achieving process stabilization.
또한, 후속 공정에서 별도의 베리어 금속막 형성 공정을 생략할 수 있으므로 공정이 단순화되고 추가 비용이 들지 않아 원가 절감의 이점이 있다.In addition, since a separate barrier metal film forming process may be omitted in a subsequent process, the process may be simplified and no additional cost may be required to reduce costs.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
Claims (6)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020036406A KR20040001266A (en) | 2002-06-27 | 2002-06-27 | method for manufacturing contact hole |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020020036406A KR20040001266A (en) | 2002-06-27 | 2002-06-27 | method for manufacturing contact hole |
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| Publication Number | Publication Date |
|---|---|
| KR20040001266A true KR20040001266A (en) | 2004-01-07 |
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| Application Number | Title | Priority Date | Filing Date |
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| KR1020020036406A KR20040001266A (en) | 2002-06-27 | 2002-06-27 | method for manufacturing contact hole |
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| KR (1) | KR20040001266A (en) |
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2002
- 2002-06-27 KR KR1020020036406A patent/KR20040001266A/en not_active Application Discontinuation
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